JPH02146765A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To secure a sufficient capacitance regardless of reduction in occupied area of memory cell by making a second storage node electrode thin to an extent that a second capacitor electrode formed on the upper layer through the capacitor insulation film is embedded into the storage node contact. CONSTITUTION:In a semiconductor storage device in lamination-type capacitor structure where the capacitor is laminated through a storage contact 12 opened at insulation films 6, 8, and 11 covering the surface of a substrate forming a MOSFET, a first capacitor electrode consists of first and second storage node electrodes 13 and 20, the first storage node electrode 13 is formed on the insulation film 11, the second storage node electrode 20 is formed within the above storage node contact 12, a second capacitor electrode 15 which is formed at the upper layer through a capacitor insulation film 14 is formed thinly so that it can be embedded into the storage node contact 12, and it is formed on the upper-layer side from a bit line 10.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device and a method for manufacturing the same;
In particular, it relates to contact structures in MOS FETs, DRAMs, etc.

(Prior Art) In recent years, due to advances in semiconductor technology, particularly advances in microfabrication technology, so-called MO8 type DRAMs are rapidly becoming more highly integrated and have a larger capacity.

With this increase in integration, the area of capacitors that store information (charge) has decreased, resulting in problems such as erroneous reading of memory contents or soft errors in which memory contents are destroyed by alpha rays, etc. It has become. Furthermore, the gate length of transistors has become shorter, and reliability of transistors has also become a problem.

One way to solve these problems and achieve higher integration and larger capacity is to form a storage node made of polycrystalline silicon on a silicon substrate to expand the area occupied by the capacitor. Various methods have been proposed to increase the capacitance of the capacitor and increase the amount of stored charge.

One of them is to stack a MOS capacitor on a memory cell region and make conduction between one electrode of the capacitor and one electrode of a switching transistor formed on a semiconductor substrate. A memory cell structure called a stacked memory cell has been proposed in which the capacitance of a capacitor is increased.

As shown in FIGS. 11(a) to 11(C), this stacked memory cell has one memory cell area separated by an element isolation insulating film 105 formed in a p-type silicon substrate 101. Inside, a source and drain region 107 made of an n-swelled diffusion layer and a gate electrode 11 are formed between the source and drain region 107 with a gate insulating film 109 interposed therebetween.
0 and MOS as a switching transistor.
In addition to configuring the FET, a MOSFE is provided on the upper layer so as to contact 1 with the source region 107 of the MOS FET.
The gate electrode 110 of T and the MOSF of the adjacent memory cell
A capacitor is formed by sandwiching a capacitor insulating film 114 between a first capacitor electrode 113 formed on the gate electrode (word line) of the ET via an insulating film 111 and a second capacitor electrode 115. .

This stacked memory cell is formed as follows.

That is, this stacked memory cell has a source and drain region 107 made of an n-swelled diffusion layer in a p-type silicon substrate 101, and a gate electrode 110 with a gate insulating film 109 interposed between the source and drain region 107. is formed to form a MOSFET as a switching transistor.

Next, after forming a silicon oxide film as an insulating film 111 over the entire surface of the substrate, a storage node contact 117 for contacting the drain region 107 is formed, and a highly doped polycrystalline silicon layer is formed. A pattern of the first capacitor electrode 113 is formed.

Then, a capacitor insulating film 114 made of a silicon oxide film and a polycrystalline silicon layer are sequentially deposited on this first capacitor electrode 113.

Thereafter, ions such as phosphorus are implanted into the polycrystalline silicon layer, and heat treatment is performed at 900° C. for about 120 minutes to form a highly doped polycrystalline silicon layer having desired conductivity.

Finally, the highly doped polycrystalline silicon layer is patterned to form a MOS capacitor in which the capacitor insulating film 114 is sandwiched between the second capacitor electrode 115 and the first capacitor electrode 113.
A memory cell consisting of an ET and a MOS capacitor is obtained.

In such a configuration, the storage node electrode can be extended to above the element isolation region, and the step difference in the storage node electrode can be used, so the capacitance of the capacitor can be increased several to several tens of times compared to the planar structure. can.

Therefore, even if the memory cell area is reduced, the amount of stored charge can be prevented from decreasing.

Furthermore, the diffusion layer in the storage node section is only the diffusion layer 107 under the storage node electrode (first capacitor electrode 113), and the area of the diffusion layer that collects charges generated by α rays is extremely small, causing soft errors. It has a strong structure.

However, such a cell structure has the following drawbacks.

One of them is poor flatness and the resulting difficulty in processing.

That is, looking at the number of electrodes, since charge is stored in the storage node electrode 113, the number of electrodes is one more layer compared to a planar cell that stores charge on a normal silicon substrate.

For this reason, the higher the layer, the worse the flatness of the base layer.
Processing using photolithography and etching becomes difficult, and there is a problem in that open defects and short-circuit defects occur frequently in each electrode.

In other words, the difference in level between the storage node electrode, capacitor insulating film, and plate electrode increases the level difference between the top surface of the interlayer insulating film and the substrate, which not only reduces bit line metal coverage but also makes it difficult to process the bit line. It becomes difficult.

In addition, in such a multilayer capacitor, the actual area of the capacitor consists of the area of the upper surface of the first capacitor electrode located on the lower layer side and the side surface portion after pattern formation, and Assuming electrodes,
Particularly in the case of high integration, as the area occupied by memory cells decreases, the ratio of the side portions to the actual area increases. Therefore, in order to keep the capacitance constant, it is necessary to increase the thickness of the storage node electrode and increase the ratio of the side surface portion due to the step.

On the other hand, the first capacitor electrode usually has a film thickness of about 3000A, and it is said that it is desirable to form this pattern by anisotropic etching such as reactive ion etching. When using, the MO
Since the process involves processing a film formed on an undulating surface on which an SFET is formed, a long etching time is required. This type of anisotropic etching over a long period of time reduces the underlying M
There is a problem in that it has an adverse effect on the OSFET and tends to cause deterioration of transistor characteristics. Further, even if such long-time etching is performed, it is difficult to completely remove the film remaining on the sloped surface due to the undulations, and short circuits with adjacent memory cells often occur.

Furthermore, in the processing of the plate electrode 115, a bit line contact 117 for contacting the bit line 118 and the substrate, and a storage node electrode 113 are formed.
It is necessary to process the plate electrode 115 between the edges of the storage node electrode 113 and the edge of the storage node electrode 113, which causes many problems when achieving high integration due to the lack of dimensional space. For plate electrode 115
Processing is also extremely difficult.

(Problem to be Solved by the Invention) As described above, even in DRAMs with a stacked memory cell structure, as the elements become finer due to higher integration, the area occupied by the memory cells is reduced, and the conventional stacked memory cell structure becomes smaller. In cell structures, the area of the flat portion of the storage node electrode is becoming smaller and smaller, making it difficult to ensure sufficient capacitor capacity.

Furthermore, when forming a capacitor, poor flatness has been a major cause of hindering high integration, especially because it is difficult to process the upper layer plate electrode.

Furthermore, when patterning the first capacitor electrode, there are serious problems not only in terms of poor workability but also in deterioration of the underlying MOSFET due to long-term etching.

The present invention has been made in view of the above-mentioned circumstances, and provides a highly reliable memory cell structure and method for manufacturing the same, in which sufficient capacitor capacity can be secured despite the reduction in the area occupied by the memory cell. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) Therefore, in the present invention, a cell is formed by a MOSFET and a capacitor, a bit line is connected to either the source or the drain of the MOSFET, and a word line is connected to the gate electrode. A first capacitor electrode as a storage node electrode of the capacitor is connected to the other of the source or drain region of the MOSFET via a storage node contact opened in an insulating film covering the surface of the substrate on which the MOSFET is formed. In a semiconductor memory device having a stacked capacitor structure in which capacitors are stacked on the insulating film so as to be connected to each other, the first capacitor electrode is connected to a first storage node electrode formed on the insulating film;
The second capacitor electrode is formed of a second storage node electrode formed in the storage node contact and is formed in an upper layer with a capacitor insulating film interposed therebetween, to the extent that the second capacitor electrode is embedded in the storage node contact.
The second storage node electrode is formed thin and is formed in a layer above the bit line.

Further, in the method of the present invention, a bit line contact is formed on the surface of the glabella insulating film formed on the surface of the MOSFET,
After connecting a bit line to one of the source or drain of the MOSFET, a second capacitor electrode formed in an upper layer via a capacitor insulating film is thin enough to be buried in the storage node contact, and the second capacitor electrode is connected to the other of the source or drain of the MOSFET. A second storage node electrode is formed so as to be in contact with the second storage node electrode.

(Function) According to the above configuration, since the bit line is formed in a layer lower than the first capacitor electrode, the wiring in the lower layer is only the gate electrode when forming the bit line, so the flatness is good and processing is easy. It's easy.

Further, the patterning of the second capacitor electrode, that is, the plate electrode, can be formed without depending on the position of the bit line contact, and no dimensional allowance is required, so that space can be saved and processing is easy.

Further, since the inside of the storage node contact can also be used as a capacitor, the storage capacity can be increased without deteriorating the flatness.

That is, it is possible to solve the problem of poor flatness, which is a drawback of the stacked memory cell structure, and the difficulty in processing caused by it, and to achieve higher integration without reducing the storage capacity.

Additionally, as an additional effect, by forming the second storage node electrode thinly, it is possible to pattern it without being exposed to the etching agent for a long time, and it is also possible to pattern it with high precision by isotropic etching. Therefore, it is possible to prevent deterioration of the underlying MOSFET, and it is also possible to prevent short circuits between adjacent cells due to the electrode material remaining on the sloped portion.

Therefore, even when the area occupied by the memory cell is reduced, sufficient capacitor capacity can be ensured, and short circuits between adjacent cells will not occur.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1(a) to FIG. 1(d) are plan views showing two bits adjacent in the bit line direction of a DRAM having a stacked memory cell structure according to an embodiment of the present invention; B-B
'Cross-sectional view, c-c' cross-sectional view.

This DRAM includes a memory cell region formed in a p-type silicon substrate 1 and separated by an element isolation insulating film 2, and a gate electrode 4 formed on the substrate surface with a gate insulating film 3 interposed therebetween. The MOSFET is formed by forming a MOSFET including a source and a drain region 5, and a capacitor formed by sandwiching a capacitor insulating film 14 between storage node electrodes 13 and 20 and a plate electrode 15.

The feature of this DRAM is that the bit line 10 is a MOSFET.
The bit line contact 9 formed in the first interlayer insulating film 6 above is connected to a pad electrode 7 connected to one of the sos/drain 5 of the MOSFET, and runs over the element isolation region 2. , and storage node electrode 1
3 and 20 are located above the bit line, and the storage node electrode 20 is formed thinly, so that the capacitor insulating film and the plate electrode enter into the storage node contact 12, and the inside of the storage node electrode and The reason is that both outer sides are used as capacitors.

This storage node electrode is also connected to the pad electrode 7 connected to the other of the source/drain 5 of the MOSFET by the pad contact 12p formed in the first interlayer insulating film 6. The storage node contacts 12 are connected to each other through storage node contacts 12 formed in the film 6 , the second interlayer insulating film 8 , and the third interlayer insulating film 11 .

This third interlayer insulating film 11 is an insulating film for insulating the bit line 10 and the capacitor.

For other parts, the DRA has a normal stacked memory cell structure.
It is exactly the same as M.

That is, in an active region separated by an element isolation insulating film 2 formed in a p-type silicon substrate 1 with a specific resistance of about 5 Ω·Ctll, an n-swelled diffusion layer 5 constituting a source/drain region, A gate electrode 4 is formed between these source and train regions via a gate insulating film 3, and the MOSFE
The contact pad 9p formed in the first interlayer insulating film 6 formed on the upper layer contacts this n-swelled diffusion layer 5, and reaches the element isolation insulating film. A pad electrode 7 is formed as shown in FIG.
0 is formed.

Further, a pad electrode 7 is formed to contact the other side of the n-swelled diffusion layer 5 via a contact pad 12p formed in the first interlayer insulating film 6. The second interlayer insulating film 8
A storage node electrode 13, a capacitor insulator 11A14, and a plate electrode 15 are formed to fit into the contact hole via a storage node contact 12 formed in the third interlayer insulating film.

The gate electrodes 4 are continuously arranged in one direction of the memory array to form word lines.

Next, a method for manufacturing this DRAM will be explained with reference to the drawings.

2 to 10 are diagrams showing the manufacturing process of this DRAM, and in each figure, (a) to (d) are plan views showing two bits adjacent in the bit line direction, and A-
They are an A' sectional view, a BB' sectional view, and a cc' sectional view.

First, as shown in Fig. 2 (a) to (d), the specific resistance 5
A silicon oxide film 17 and a silicon nitride film 1 with a thickness of 50 nm are formed on the surface of a p-type silicon substrate 1 of about Ω·C11.
8 is formed and patterned, and boron ions are implanted using the patterns of the silicon oxide film 17 and the silicon nitride film 18 as masks to form a channel stopper impurity layer 16.

Next, as shown in FIGS. 3(a) to 3(d), an element isolation insulating film 2 is formed by selective oxidation. During this oxidation step, the channel stopper impurity layer 16 is diffused laterally and under the element isolation insulating film. This device isolation method is just an example, and it is not necessary to use this method.
Other methods may also be used.

As shown in FIGS. 4(a) to (1), after forming a silicon oxide layer 3' with a thickness of 10 nIn by thermal oxidation method, a 20 onl polycrystalline silicon layer 4' is deposited by CVD method. Furthermore, a silicon oxide film 6 as an interlayer insulating film is deposited and patterned by photolithography and reactive ion etching to form a gate insulating film 3 and a gate electrode 4.

Then, using this gate electrode 4 as a mask, As ions are implanted to form a source/drain region consisting of an n-swelled diffusion layer 5, and an M as a switching transistor is formed.
Form OS FET. The depth of this diffusion layer is, for example, about 150 rv.

After this, a film thickness of 100 n1Pi! was obtained by CVD method. An interlayer insulating film 6' made of a silicon oxide layer is deposited over the entire surface, and the entire surface is etched by a reactive ion etching method, so that it is left on the side surfaces of the gate electrode 4 in a self-aligned manner.

In this way, the source/drain regions are exposed and form the pad contact 9p.

12p is formed.

Furthermore, as shown in FIGS. 5(a) to 5(1), polycrystalline silicon with a thickness of about 50 nm is deposited on this upper layer by the CVD method, and arsenic or phosphorus ion implantation or phosphorus diffusion is performed. After doping is performed by etching, etc., the pad electrode 7 is patterned by reactive ion etching.

Next, as shown in FIGS. 6(a) to 6(d),
After depositing a second interlayer insulating film 8 with a thickness of about 300 nm over the entire surface, a bit line contact 9 is formed by photorin method and reactive ion etching. This interlayer insulating film 8 is formed by, for example, a CVD method and has a thickness of 10
Silicon oxide film with a thickness of about 350 nm, BP with a film thickness of about 350 nm
The SG film and the PSG film with a thickness of about 250 nm were sequentially deposited, the BPSG film and PSGl19 were melted at 900°C, and the PSG film and BPS film were melted with ammonium fluoride solution.
The G film is planarized by etching away the surface layer. After forming the bit line contact 9, a polycrystalline silicon film is further formed by, for example, a CVD method.
Further, molybdenum silica->noids are deposited on the entire surface by sputtering or EB evaporation, and both are etched by reactive ion etching to pattern the bit line 10. Here, since the level difference on the substrate surface is not so large, the interlayer insulating film 8 can be easily flattened, and no problem occurs in patterning. Further, since the contact level difference is relatively small, the bit line coverage is also good.

Thereafter, as shown in FIGS. 7(a) to 7(d), a third interlayer insulating film 11 having a thickness of about 200 nm is deposited on the entire surface. This interlayer insulating film 11 may be, for example, a silicon oxide film with a thickness of about 50 nm formed by the CVD method, a BPSG film with a thickness of about 300 nm, or a BPSG film with a thickness of 250 nm.
PSG films with a thickness of m culm were sequentially deposited, the 8PSG film and the PSG film were melted at 900''C in the same way as the second interlayer insulating film, and the PSG film and BPSG film were melted with ammonium fluoride solution.
The film is planarized by etching away the surface layer. Then, the film thickness is 30Qni to 600nun on the entire surface.
A polycrystalline silicon film is deposited and doped to form the first storage node electrode 13.

Then, as shown in FIGS. 8(a) to 8(d),
A storage node contact 12 is formed by photolithography and reactive ion etching.

Furthermore, as shown in FIGS. 9(a) to 9(d),
A polycrystalline silicon film 20 with a thickness of 800 A is deposited on the entire surface,
The second storage node electrode 20 is formed by ion implantation of arsenic or phosphorus or by phosphorus diffusion. Here, this polycrystalline silicon film is formed so thin that it does not completely fill the storage node contact. Also, at this time, the polycrystalline silicon film 2 in the storage node contact
The film thickness of 0 (second storage node electrode) is 8008, which is about one-fourth of the film thickness of the conventional first capacitor electrode. (Here, both the first and second storage node electrodes 13.20 play the role of first capacitor electrodes.

) Then, as shown in FIGS. 10(a) to 10(d), the polycrystalline silicon film 13. is etched by anisotropic etching.
20 to isolate capacitors between cells.

Then, on this upper layer, about 10 nl of silicon nitride film is deposited over the entire surface by CVD method, and then oxidized for about 30 minutes in a steam atmosphere at 950°C to form a capacitor with a two-layer structure of silicon oxide film and silicon nitride film. After forming an insulating film 14 and doping a polycrystalline silicon film with a thickness of 3,000 yen over the entire surface, patterning is performed by photolithography and reactive ion etching to form a second capacitor electrode 15 as a plate electrode. The RAM is completed as shown in FIGS. 1(a) to 1(d).

According to the above configuration, since the second storage node electrode 20 is thin, the capacitor insulating film 1 formed in the upper layer
4 and the plate electrode 15 are formed in such a shape that they are embedded in the storage node contact, so both the inner and outer side surfaces of the storage node electrode, which are curved depending on the shape of the storage node contact, can be used as the capacitor area. It is possible to prevent a reduction in storage capacity.

In addition, the bit line is formed in a layer above the storage node electrode and is not patterned on a step as in the conventional case, but the etching for the bit line contact is
The formation of the pad contact 9p formed on the second interlayer insulating film 6 and the bit line contact 9 formed on the second interlayer insulating film 8 are performed in two steps, and there is no need to worry about the electrode material remaining on the sloped part. , short circuits between adjacent cells can be avoided, and highly accurate patterning can be easily achieved. Further, since dimensional margins are not required during patterning, higher density can be achieved.

Further, although the second storage node electrode 20 is as thin as 800.8 mm, the polycrystalline silicon film is deposited extremely uniformly even on the steps, so that no step breakage occurs.

Furthermore, by increasing the thickness of the first storage node electrode 13, the surface area of the side surface of the edge of the first capacitor electrode can be increased.

Even in that case, the bit lines are already formed, so
The processing is not affected by the step of the first capacitor electrode.

Therefore, even when the area occupied by the memory cell is reduced, sufficient capacitor capacity can be ensured, and short circuits between adjacent cells will not occur.

Note that as the capacitor insulating film, in addition to a two-layer structure film of a silicon oxide film and a silicon nitride film, a silicon oxide film or a metal oxide film such as tantalum pentoxide (Ta20s) may be used.

Further, although a polycrystalline silicon film is used as the first capacitor electrode, it is not necessarily limited to a polycrystalline silicon film, and can be modified as appropriate, such as using a tungsten thin film.

Furthermore, in these embodiments, a DRAM with a stacked capacitor structure has been described, but a DRAM with a trench structure may also be used.
It is also applicable to M.

Furthermore, in the embodiment described above, the bit line and storage node electrode are formed through pads.
This invention is also effective in the case of direct connection. In this way, especially when directly contacting the source/drain region without using a pad electrode, by forming the first capacitor electrode thinly, as an incidental effect,
It is possible to pattern without being exposed to etching agents for a long time, and it is also possible to pattern with high precision by isotropic etching, so the underlying M
This is effective because it can prevent deterioration of the OSFET.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, the second
of the first capacitor electrode to the extent that the second capacitor electrode of the first capacitor electrode is embedded within the storage node contact.
The first storage node electrode is formed thinly and is formed in an upper layer than the bit line, and the first storage node electrode is thicker in the upper layer, which prevents a reduction in the capacitor area and allows for high integration. Even when the capacitance is increased, sufficient capacitance is maintained and reliability becomes high.

[Brief explanation of the drawing]

FIG. 1(a) to FIG. 1(d) are plan views showing two bits adjacent in the bit line direction of a DRAM having a stacked memory cell structure according to an embodiment of the present invention; B-B
'cross-sectional view, c-c' cross-sectional view, Figures 2 to 10 are diagrams showing the manufacturing process of this DRAM, and Figure 11 is a conventional DR
It is a figure showing AM. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Element isolation insulating film, 3... Gate insulating film, 4... Gate electrode, 5...
・N-type diffusion layer, 6, 8.11... interlayer insulating film, 7...
・Pad electrode, 9...Bit line contact l-110・
...Bit line, 12...Storage node contact, 13°20...First capacitor electrode (storage node electrode), 14...Capacitor insulating film, 16...
- Channel stopper impurity layer, 15... second capacitor electrode (plate electrode), 101... p-type silicon substrate, 105... element isolation insulating film, 106...
107... Source train region, 109... Gate insulating film, 110... Gate electrode, 111... Insulating film, 112... Storage node contact, 113
. . . first capacitor electrode, 114 . . . capacitor insulating film, 115 . . . second capacitor electrode, 116.
...Channel stopper impurity layer, 117... Bit line contact, 118... Bit line, 119... Insulating film. ○ Suku

Claims (5)

[Claims] (1) A cell is formed by a MOSFET and a capacitor, a bit line is connected to one of the source or drain of the MOSFET, a word line is connected to the gate electrode, and a capacitor is connected to the other of the source or drain region of the MOSFET. In a semiconductor memory device having a stacked capacitor structure in which capacitors are stacked via a storage node contact opened in an insulating film covering a substrate surface so as to be connected to a first capacitor electrode serving as a storage node electrode of the first capacitor electrode, One capacitor electrode is formed of first and second storage node electrodes, the first storage node electrode is formed on the insulating film, and the second storage node electrode is formed on the storage node contact. Furthermore, the second capacitor electrode formed in the storage node contact is thin enough to be embedded in the storage node contact through a capacitor insulating film, and is formed on the upper layer side than the bit line. A semiconductor memory device characterized in that it is formed in. (2) The semiconductor memory device according to claim 1, wherein the second storage node electrode is connected to a source or drain region of a MOSFET via a pad electrode. (3) The semiconductor memory device according to claim 1, wherein the bit line is arranged on an element isolation region between memory cells so as to be orthogonal to the word line. (4) The bit line is connected to the MOS via a pad electrode.
4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is connected to one of the source and drain regions of the FET. (5) A cell is formed by a MOSFET and a capacitor, and a storage node electrode of the capacitor is connected to the source or drain region of this MOSFET via a storage node contact opened in an insulating film covering the surface of the substrate on which the MOSFET is formed. A method for manufacturing a semiconductor memory device having a stacked capacitor structure in which capacitors are stacked on the insulating film such that a first capacitor electrode is connected to the insulating film includes a MOSFET forming step of forming a MOSFET on a semiconductor substrate; a bit line forming step of forming a bit line so as to contact the other source or drain region of the bit line; an interlayer insulating film deposition step of depositing an interlayer insulating film; and a step of depositing a first storage node electrode on this interlayer insulating film. Then, a storage node contact is opened in this interlayer insulating film and the first storage node electrode, and the MO
a first capacitor electrode forming step of forming a thin second storage node electrode in contact with one of the source or drain region of the SFET; and a capacitor insulating film forming a capacitor insulating film on the surface of the first capacitor electrode. A method of manufacturing a semiconductor memory device, comprising: a forming step; and a second capacitor electrode forming step of forming a second capacitor electrode on the surface of the capacitor insulating film.