JPH02304968A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable the length in short-side direction between cells per bit to be reduced further by using a lead-out electrode by a wiring layer which is different from a bit wire for connecting the bit wire and a diffusion layer of a switching transistor and by forming a bit contact on a field. CONSTITUTION:A take-out electrode 36 by a wiring layer which is different from a bit wire 39 is used for connecting the bit wire 39 and a diffusion layer of a switching transistor to form a bit contact on a field, thus enabling the take-out electrode 36 and the bit wire 39 to be overlapped each other. This permitted overlapping contributes to reduce a length A in short-side direction between cells and eliminates the bit-wire-contact margin at the field side, thus enabling the length A in short-side direction between cells up to l1 (gap between bit wires) + l2 (bit wire -bit contact margin) + l3 (bit contact dimensions).

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, particularly a DRAM memory cell and a manufacturing method thereof.

(Prior Art) Conventionally, a memory cell composed of one switching transistor and one capacitor has been widely used as a DRAM cell. In this type of memory cell, information is stored depending on the presence or absence of charge stored in the capacitor, and reading, writing, and memory holding operations are performed by turning on and off a switching transistor. Kiya
In order to preserve the charge state of the f-shita, a refresh operation is performed at regular intervals, but during this refresh period,
It is necessary for the capacitor to hold a sufficient amount of charge.

In actual devices, leakage currents in various paths,
Since there is an inflow of charges generated by the incidence of alpha particles, the capacitance value of the capacitor needs to be a certain value or more. On the other hand, the miniaturization of memory cells in order to increase the density of DRAMs is remarkable, and the capacitance value decreases accordingly, making it difficult to secure the capacity of the memory cells unless some kind of three-dimensional structure is used.

A stacked capacitor cell is an example of this type of cell structure. FIGS. 2(a) and 2(b) show conventional stacked capacitor cell structures. FIG. 5(a) is a planar pattern diagram, and FIG. 2(b) is a cross-sectional view taken along line c-d' in FIG. 2(a). An overview of a conventional stacked capacitor cell structure will be explained using the same figure. In the figure, 1 is a P-type silicon substrate, on which a field oxide film 2 is provided. The MOS type switching transistor includes a gate oxide film 3, a gate electrode 4, and a source/source.
It is composed of diffusion layers 51L and 5b forming a drain. The capacitor is still composed of a storage electrode 8, a dielectric thin film 9, and a cell rate electrode 10. The storage electrode 8 is connected to one diffusion layer 5b of the switching transistor through a connection opening 2 (hereinafter referred to as cell contact). has been done. The other diffusion layer 5a of the switching transistor is connected to the bit line 13 via the connection opening 12 (hereinafter referred to as bit contact) 66.11
The interlayer insulating film 14 is a passivation film.

In the stacked capacitor cell structure described above, as shown in FIG. 2(a), an alignment margin t is required between the storage electrode 8 and the bit contact 12, and the capacitor area becomes smaller by that amount. . Therefore, Literature I
EDM Technology digest.

T., Ema et al., 1988, “3-Dimen”
sional 5tackedCapacitor
Ce1l for 16M and 64MDR
A new stacked capacitor cell structure was proposed as disclosed in ``AMs'' pp592-595.
Figure (a) shows the plane pattern diagram, and figure (b) shows the same figure (
A sectional view taken along line d-d' in a) is shown, and FIG. The outline will be explained using the same figure.

In the figure, 15 is a P-type silicon substrate, and 16 is a field oxide film. The MO3 type switching transistor is composed of a gate oxide film 17, a gate electrode 18, and diffusion layers 19a and 19b forming a source and a drain. One diffusion layer 19m of the switching transistor is connected to a bit line 22 via a bit contact 21, and the other diffusion layer 19b is connected to a cell contact 24.
It is connected to a canopy motherboard composed of a stray electrode 25, a dielectric thin film 26, and a cell plate electrode 27. Reference numerals 20 and 23 are interlayer insulating films, and 28 is a mother passivation film. 2, the active region surrounded by the field oxide film is formed in a convex shape, the bit contact is shifted to the convex protrusion, and the bit line 22 is formed by field oxidation. By wiring on the upper layer of the film,
The bit contact-storage electrode margin shown in FIG. 2 is unnecessary, and the area of the strain electrode can be increased accordingly.

(Problem to be Solved by the Invention) However, in the stacked capacitor having the structure shown in FIGS. 3(a) to 3(c), the cell contact is formed after the bit line 22 is formed, so the active region is deformed into a convex shape. and drill a bit contact 21 in the convex protrusion,
In addition, the bit line 22 must be routed above the field oxide film, avoiding the active area. As a result, the length C in the short side direction between cells is as shown in the e-e' cross-sectional view of FIGS. 3(a) and 3(c). As shown in , the minimum at (bit line spacing)
+dx (bit line - bit contact margin) +as
There is a drawback that it cannot be made smaller than the value determined by (bit contact dimension) + d4 (bit line - bit contact margin).

(Means for Solving the Problems) In order to solve the above problems, the present invention uses an extraction electrode in a wiring layer different from the bit line to connect the bit line and the diffusion layer of the switching transistor, and connects the bit contact to the field. By forming this, it is possible to further reduce the length in the short side direction between cells per 1 bit.

(Function) According to the present invention, the take-out electrode connects the bit line and the diffusion layer. Since the take-out electrode is formed of a wiring layer different from the bit line and the bit line, the take-out electrode and the bit line overlap. can do. This allowed overlap contributes to the reduction of the length A in the short side direction between cells of 1 bit field and b, and the minimum length is Lx (bit line spacing) + 11 (bit line - bit contact) as shown in Fig. 1(a). margin) +t.

(bit contact dimensions).

(Example) Fig. 1 shows a plane pattern diagram and a cross-sectional structure of the first example of the present invention.
An active region is formed on a P-type silicon substrate 29 of approximately 15 to IXIQ"cy+s-' so as to be surrounded by a field oxide film 30, and a gate oxide film 3 is formed on the active region.
A switching transistor is formed by a gate electrode 32 and N+ diffusion layers 33a and 33b. One diffusion layer 33m of the switching transistor is connected to a lead-out electrode 36 via a contact 35, and the lead-out electrode 36 is connected to a bit line 39 on the p-field oxide film 30 by a bit contact 38. There is. The capacitor includes a storage electrode 42 and a dielectric thin film 43
and a cell plate electrode 44, and the storage electrode 42 is connected to the other diffusion layer 33b of the switching transistor through the cell contact 41. 34,
37.

40 is an interlayer insulating film, and 45 is a noccination film.

The gate electrode 32 of the switching transistor also serves as a word line. In the above configuration, by setting the word line to a high level, the switching transistor is turned on, and information is written to the capacitor through the bit line 39, and conversely, information is read from the capacitor to the bit line. Tashi. When the word line is at a low level, the switching transistor is turned off and the contents of the capacitor are held.

FIG. 4 is a sectional view of the manufacturing process showing the first embodiment of the present invention. Note that the film thickness is only an example and can be selected as appropriate. First, the impurity concentration IX10''~IX1016an-3
Although not shown, the P-type silicon substrate 29 of
5 x 1016 to 2 x 10 on the entire memory cell part substrate
After forming a P well with a concentration of about 170-3, LOCO
A field oxide film 30 of about 500 nm is formed using the S method. Next, the gate oxide film 31 of the switching transistor is grown to a thickness of about 15 nm by thermal oxidation, and the polysilicon 32 that will become the gate electrode is grown by low-pressure CVD.
Deposit about 300 nm over the entire surface. Next, in order to lower the resistance of polysilicon 32, polysilicon 32 is doped with phosphorus at a high concentration. Next, photolithography and etching/grinding, polysilicon 32, gate oxide film 31
pattern. Thereafter, fiN+ diffusion layers 33a and 33b are formed by ion-implanting arsenic, and as shown in FIG.
Obtain the structure shown in a). Next, a silicon oxide film 3 is formed by CVD.
4 is deposited to a thickness of about 100 to 200 nm over the entire surface, and a contact hole 35 for connecting one diffusion layer 331L of the switching transistor to the extraction electrode 36 is opened by ordinary photolithography and etching.

Furthermore, the polysilicon 36 that will become the extraction electrode is processed by low pressure CVD.
The film is deposited to a thickness of about 200 nm over the entire surface by a method and doped with phosphorus at a high concentration to obtain the structure shown in FIG. 4(b). Next, the polysilicon 36 is patterned by photolithography and etching to form an extraction electrode 36'.
An oxide film 37 is deposited to a thickness of about 100 to 200 nm using the CVD method. Here, the extraction electrode is formed by field oxidation and extends to the top of the film.

A contact can be formed on the field oxide film. Then, a contact hole 38 is opened to connect the extraction electrode 36 and the upper layer wiring. In the present invention, by forming the bit contact on the field oxide film, it is possible to eliminate the margin between the bit line and the bit contact on the field side in the short side direction of the cell. Furthermore, by low pressure CVD method, J25
After depositing polysilicon with a thickness of approximately 0 nm over the entire surface and doping it with phosphorus at a high concentration, tungsten silicide with a thickness of approximately 150 nm is deposited over the entire surface using a sputtering method to form a tungsten polycide layer 39 that will become a bit line. , 4th
The structure shown in Figure (C) is obtained. Next, the tungsten polycide layer 39 is turned by photolithography and etching to form a bit line 39', and a silicon oxide film 40 is deposited to a thickness of about 100 to 200 nm by CVD. Through the above steps, the characteristic structure of the memory cell of the present invention is realized.The cell contact 41 is opened by zero-order photolithography and etching, and the polysilicon 42, which will become the storage electrode, is formed to a thickness of about 200 nm over the entire surface by low-pressure CVD. The structure shown in FIG. 4(d) is obtained by doping a high concentration of phosphorus to reduce the resistance. Next, a storage electrode 42' is formed by patterning the polysilicon 42 by photolithography, processing, and etching, and a silicon nitride film 43, which will become the dielectric thin film of the capacitor, is deposited by low-pressure CVD.
The nitride film is deposited to a thickness of 5 to 10 nm by a method, and then annealed in a wet oxygen atmosphere at around 900° C. in order to lower the defect density of the nitride film and increase its breakdown voltage. Further, silicon 44, which will become a cell plate electrode, is deposited on the entire surface by low pressure CVD and doped with phosphorus at a high concentration. Finally, a nitride film 45 is applied as a noccination film to obtain the final structure shown in FIG. 4(a).

FIG. 5 is a sectional view of a manufacturing process showing a second embodiment of the present invention. Note that the film thickness is only an example and can be selected as appropriate. First, a P-type silicon substrate 29 with an impurity concentration of about 1x10 to 1x1016 crn-3 is formed as shown in the figure, but a P well is formed on the substrate of the entire memory cell section with a concentration of about 5x10 to 2x1017 cm-'. .

A field oxide film 47 of about 500 nm is formed using the LOCO8 method. Next, a gate oxide film 48 of the switching transistor is grown to a thickness of about 15 nm by a thermal oxidation method, and silicon 49, which will become a gate electrode, is deposited to a thickness of about 300 nm over the entire surface by a low pressure CVD method. Next, in order to lower the resistance of polysilicon 49,
dope with high concentration of phosphorus.

Thereafter, a silicon oxide film 50 with a thickness of about 100 nm is deposited by CVD to obtain the structure shown in FIG. 5(a). Next, the oxide film 50, polysilicon 49, and gate oxide film 48 are turned by photolithography and etching. After that, the N+ diffusion layer 511 is formed by ion-implanting arsenic.
L, 51b is formed. After that, a silicon oxide film 5 is formed using the CVD method.
2 was deposited to a thickness of about 200 nm to obtain the structure shown in FIG. 5(b). Next, anisotropic etching is applied to the gate electrode 49 of the switching transistor. A sidewall 52' is then formed on the sidewall of the oxide film 50. Thereafter, polysilicon 53 that will become an electrode is deposited at 200 n by a low pressure CVD method.
The fifth layer is deposited on the entire surface, and then coated with a high concentration of phosphorus.
The structure shown in Figure (C) is obtained. Next, the electrode 53 is patterned by photolithography and etching. In this step, the electrode 53 and the diffusion N5 of the switching transistor are
Contacts with 1a and sxb are formed in a self-aligned manner, and at the same time, an extraction electrode for opening a bit contact is formed on the field oxide film. Next, a silicon oxide film 54 of about 200 nm is deposited by the CVD method, and a bit contact hole 55 is further opened. Thereafter, a tungsten pre-cide layer 56, which will become a bit line, is formed by low pressure CVD and Snontta methods in the same manner as in the second embodiment to obtain the structure shown in FIG. 5(d). The final structure shown in FIG. 5(a) is obtained by performing the same process as shown in FIG. 4(C) and thereafter.

(Effects of the Invention) As explained in detail above, according to the present invention, the bit line is connected to the diffusion layer of the switching transistor using an extraction electrode formed on a wiring layer different from that of the bit line, and the bit contact is formed on the field. is forming. According to this method, the through-hole electrode and the bit line shown in FIG. 1(e) can overlap with each other. This allowed overlap contributes to reducing the inter-cell length A in the short side direction, and it is possible to eliminate the (bit helix - bit contact margin) on the field side. Therefore, the inter-cell length A in the short side direction can be reduced to a minimum of 41 (bit line interval) + t2 (bit line - bit contact margin) + ts (bit contact dimension).

[Brief explanation of the drawing]

FIG. 1 shows the first embodiment of the present invention, FIG. 2 shows a conventional stacked capacitor cell structure (1), FIG. 3 shows a conventional stacked capacitor cell structure (2>, and FIG. 4 shows the present invention). 5 is a process sectional view of the first embodiment of the invention, and FIG. 5 is a process sectional view of the second embodiment of the invention. 29...P-type silicon substrate, 30... Field oxide film, 31... Gate insulating film, 32... Gate electrode, 3
3a, 33b...N+ diffusion layer, 35...Contact hole, 36...Takeout electrode, 38...Bit contact, 39...Bit line, 41...Cell contact, 42...Storage Electrode, 43... Dielectric thin film, 44... Cell plate, 34, 37, 40
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Claims (2)

[Claims] (1) A field oxide film selectively formed on a first conductivity type semiconductor substrate and a gate extending in one direction on an active region surrounded by the oxide film form a word line. Consisting of a MOS type switching transistor and a capacitor connected to the first diffusion layer of the second conductivity type of the switching transistor through the first connection opening and formed in a stacked manner on the active region and the field region. In a one-transistor/one-capacitor DRAM cell, a second diffusion layer of a second conductivity type of the switching transistor is connected via a second connection opening provided on an active region immediately adjacent to the switching transistor, and a take-out electrode formed extending above the field oxide film in the same direction as the word line, and connected to a portion of this electrode extending above the field oxide film via a bit line connection opening; A semiconductor memory device further comprising a bit line formed perpendicularly to the word line in an upper layer of the field oxide film. (2) In a method for manufacturing a one-transistor/one-capacitor type DRAM cell, (a) a field oxide film is selectively formed on a first conductivity type semiconductor substrate, and a gate is formed on an active region surrounded by the field oxide film. a step of sequentially forming an insulating film, a gate electrode serving as a word line, and a second conductivity type diffusion layer to form a MOS switching transistor; A first connection opening is formed on the first diffusion layer of the second conductivity type, and an extraction electrode is connected to the first diffusion layer of the second conductivity type through the first connection opening. (c) After that, an insulating film is formed on the entire surface of the substrate, and an insulating film is formed on the portion of the extraction electrode that extends onto the field oxide film. a step of opening a bit line connection opening and forming a bit line connected to the extraction electrode through the opening in the upper layer of the field oxide film so as to be orthogonal to the word line; (d) after that; , forming an insulating film on the entire surface of the substrate, forming a second connection opening with the storage electrode on the second diffusion layer of the second conductivity type of the switching transistor; and forming a storage electrode connected through the second connection opening on the active region and the field region; (e) after that, a dielectric thin film and a ground electrode are formed on the upper layer of the storage electrode 1. A method of manufacturing a semiconductor device, comprising a step of sequentially laminating layers to form a capacitor.