JPS63131566A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the dispersion of the capacitance of a capacitor due to mask displacement during the formation of a flat section between word lines in a field oxide film, and to obtain uniform memory characteristics by burying an insulating film between adjacent word lines and flatly constituting a section between the word lines on the field oxide film. CONSTITUTION:An insulating film 10 consisting of SiO2, etc., is shaped between two adjacent word lines 4 on a thick field oxide film 7 in thickness the same as or larger than the word lines. consequently, a section between the two word lines is flattened, and a lower electrode 5 for a capacitor is formed in the flattened region. Accordingly, even when mask alignment is displaced between the word lines 4 and the capacitor lower electrode 5, capacitor capacitance is not shaped on the side wall sections of the word lines, thus acquiring uniform capacitor characteristics required for a high-integration memory.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a dynamic MO8 random access memory (hereinafter abbreviated as dynamic MO8-RAM) that can be highly integrated and has little variation in characteristics. ) regarding memory cells.

[Conventional technology]

In a one-transistor type dynamic MO8 RAM consisting of one MOS transistor and one capacitor, it is necessary to increase the capacitance value of the storage capacitor in order to increase the amount of stored signals. To this end, Japanese Patent Publication No. 60-2784 discloses a structure in which a capacitor is also formed in a stacked manner above the word line 3.4 as shown in FIG.

In this conventional structure, since the lower electrode 5 of the capacitor also overlaps the word line 4 on the thick field oxide film 7, the capacitor lower electrode 5 overlaps the word line 4 in the capacitor manufacturing process as shown in FIG. On the other hand, if a misalignment of the mask occurs.

One of the opposing capacitor lower electrodes 5 has an end on the upper part of the word line, and the lower electrode 5 is not formed on the side wall of the word line, but the other capacitor lower electrode 8 is on the side wall of the word line 4. It is also formed in the part. If the capacitor upper electrode 6 is formed with such mask misalignment, the capacitor on the right side in FIG. The capacitor on the left side also has a large capacitance value. In this way, in the conventional structure, the capacitance value varies greatly due to mask alignment misalignment.

Memo: Sufficient consideration was not given to variations in IJ'W properties.

[Problem that the invention seeks to solve]

In the above conventional technology, large-capacity dynamic MO8R and AM, which integrate memory cells of several hundred obits or more, have large variations in characteristics during the manufacturing process, which is a major obstacle in the production of large-capacity dynamic MOS RAM, which requires uniform characteristics. Become.

The object of the present invention is to solve the above-mentioned problems of the prior art.

It is an object of the present invention to provide a memory cell for use in a large-capacity dynamic MO8RAM, which reduces variations in characteristics due to mask misalignment during the manufacturing process, specifically, variations in capacitance of a capacitor.

[Means for solving problems]

In order to achieve the above object, one aspect of the present invention is to embed an insulating film between adjacent word lines existing on a thick field so that the space between the word lines on the field oxide film is flat.

[Effect]

With the above means, the lower electrode of the capacitor does not enter the side wall of the word line on the field oxide film, so even if mask misalignment occurs in the manufacturing process, no capacitor capacitance is formed on the side wall of the word line.

Variations in capacitor capacitance due to mask misalignment are eliminated, and uniform memory characteristics can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1 and FIGS. 4 to 6.

FIG. 1 shows a cross-sectional structure of a memory cell according to the present invention. The figure shows two memory cell pits, with the word line 3 serving as the gate electrode and the high concentration n-swelling diffusion layer 2 serving as the source.
Drain. Transfer game) MOS) transistors are also shown, one on each side. A capacitor lower electrode 5 for storage capacitance is formed in a stacked manner on top of the word line 4 . The upper electrode 6 of the capacitor is formed on the lower electrode 5 with a thin insulating film 9 interposed therebetween. As a feature of the present invention shown in FIG. 1, an insulating film 10 such as 5i02 is formed between two adjacent word lines 4 on a thick field oxide film 7 with a thickness equal to or greater than that of the word lines. Therefore, the area between the two word lines is flattened, and the lower electrode 5 of the capacitor is formed in this flattened region. Therefore, even if a mask misalignment occurs between the word line 4 and the capacitor lower electrode 5, capacitor capacitance will not be formed on the side wall of the word line as shown in FIG. 3, which is necessary for highly integrated memory. Therefore, uniform capacitor characteristics can be obtained.

Note that in FIG. 1, the same polycrystalline silicon as the lower electrode 5 of the capacitor is formed on the top of the high concentration diffusion layer 2 of the transfer MO8) transistor on which the capacitor is not stacked, and on top of this, aluminum is formed to form the data line. It forms an electrode hole with the electrode.

FIG. 4 shows a planar pattern of a memory cell according to the present invention. An insulating film is buried in a region 11 between two word lines 40 on the thick field oxide film 8 to flatten the step. Therefore.

Even if the end of the lower electrode 5 of the capacitor exceeds the word line 4 and extends into the field portion 8 due to mask misalignment, the variation in capacitance of the capacitor due to the word line step difference is very small.

FIG. 5 is a process diagram showing a method for manufacturing a memory cell structure according to the present invention. First, a field oxide film 8 with a thickness of 0.2 to 1.0 μm. Then, a thin gate oxide film 12 of 5 to 5 Q nm is formed (FIG. 5A). Next, a gate electrode 4 made of polycrystalline silicon, a silicide layer, or a multilayer film thereof, and an insulating film 13 made of an 8i0z film above the gate electrode 4 are formed. Using this gate electrode as a mask, 10% of n-type impurities were added.
12~10110l4'' ion implantation n shadow area 1
6 (Figure 5B). Next, chemical vapor phase reaction method (hereinafter referred to as CVD method) is applied to the S i 02 film 14 e O
, 1 to 0.5 μm, and a photoresist pattern 15 is formed so as to cover between the two word lines 40 (fifth
Figure C). Next, the above 8i is etched by anisotropic dry etching.
When the 02 film 14 is etched, a spacer 17 is formed on the side wall of the gate pole 4, which will become the word line of the memory, and a spacer 17 is formed between adjacent word lines 4 on the field oxide film.
8i0z film is embedded and flattened (Fig. 5D)
). The degree of flattening increases as the distance between adjacent word lines becomes narrower, so it is preferable to set the distance between the word lines to the minimum distance allowable in the lithography process. After that, the n-type high concentration layer 2 that will become the source and drain and the capacitor lower electrode 5 are formed of polycrystalline silicon, and a thin insulating film 9 of 4 to 200 m is formed thereon using a 5i02 film, 5isN< film, or other high dielectric constant film. An insulating film is formed, and a capacitor upper electrode 6 is formed on the insulating film using polycrystalline silicon, silicide, a multilayer film thereof, or a high melting point metal film.
form (Fig. 5E). Finally, a surface protective film 18 such as a PSG film and an electrode hole 19. Electrode wiring 20 is formed to constitute a memory cell (FIG. 5F).

FIG. 6 shows another manufacturing method for flattening the space between adjacent word lines. In this method, a spacer of 5iOz film is formed on the side wall of the word line without forming the photonist film 15'f shown in Figure 5C, and then a solution of 5iCh grains dissolved in an organic solvent is applied. 5iQ221 is embedded in one step.

〔Effect of the invention〕

According to the present invention, it is possible to reduce to less than 1/4 the variation in characteristics in the manufacturing process of memory cells used in large-capacity dynamic MO8RAMs that are fully integrated with megabits or more on one chip. This will make a significant contribution.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2 and 3 are vertical cross-sectional views of a conventional semiconductor device, FIG. 4 is a plan layout diagram of an embodiment of the present invention, and FIGS. 5 and 6 are diagrams showing the manufacturing process of an embodiment of the present invention. It is. 1...Silicon substrate, 2.16...N swelling diffusion layer, 3
゜4...word line, 5. 8... Capacitor lower electrode, 6... Capacitor lower electrode, 7, 9, 10,
11°12.13, 14, 17, 18.21...Insulating film. 19... Electrode hole, 15... E) l/cyst membrane, 20
···electrode. Kaya) Figure I Rod 2 Figure 1 ￥3 Figure 4 Figure 11 Zetsubo Eno Buried Prisoner Toiso

Claims (1)

[Claims] 1. Consisting of an insulated gate field effect transistor and a charge storage capacitor provided on a semiconductor substrate, an electrode for the storage capacitor is formed on a word line and a field insulating film, which serves as the gate electrode of the field effect transistor. In a stacked dynamic semiconductor memory device, which is formed so as to overlap the word lines that are formed, an insulating film is buried between the adjacent word lines on the field insulating film and is flattened. A semiconductor memory device characterized in that a storage capacitor lower electrode is formed so that an end thereof is located in a flattened region.