JPH0795566B2 - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0795566B2 JPH0795566B2 JP60279559A JP27955985A JPH0795566B2 JP H0795566 B2 JPH0795566 B2 JP H0795566B2 JP 60279559 A JP60279559 A JP 60279559A JP 27955985 A JP27955985 A JP 27955985A JP H0795566 B2 JPH0795566 B2 JP H0795566B2
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- electrode
- trench
- insulating film
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000003990 capacitor Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims 2
- 239000010408 film Substances 0.000 description 29
- 238000009792 diffusion process Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 230000005260 alpha ray Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体メモリ装置の構成要素として広く利用
されるDRAMセルに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM cell widely used as a constituent element of a semiconductor memory device.
従来の技術 近年、半導体メモリ装置の高密度化が進み、特にDRAMの
高集積化，大量容化は著しい。このようなDRAMセルの発
展はそのチップサイズの半分以上の面積を占めるメモリ
セルの高密度化技術の発展に負う所が大きい。現在、一
層の高密度化を目的として種々の立体構造DRAMセルが提
案されて来ている。従来、この種の立体構造DRAMセル
は、一例として第２図に示す様な構成であった。第２図
において、１はビットラインを形成するドレイン、２は
信号読み出し用トランスファゲートを構成するMOSトラ
ンジスタのゲート酸化膜、３はワード線を構成する、例
えば，ポリシリコンで形成されたゲート電極、４はメモ
リセルのソース拡散部、５はメモリセルのキャパシタを
構成する絶縁薄膜、６はセルプレートと称される例えば
ポリシリコンを用いたキャパシタ用プレート電極、７は
セル間分離用絶縁膜、８は基板、10は層間絶縁膜であ
る。これはいわゆるトレンチ構造と言われるメモリセル
構造の一例である。この構造は、トレンチを基板８の深
さ方向に形成するため、トレンチ深さの制御により蓄積
用容量もメモリセルとして必要とされる値（50fF以上と
一般にいわれている。）を充分確保できる。また、この
構造においては、トレンチを単に信号蓄積キャパシタと
してだけでなく素子分離にも利用しており、セル間分離
用絶縁膜７を厚くとることによりセル間リーク電流を充
分低くとることができる。2. Description of the Related Art In recent years, the density of semiconductor memory devices has increased, and DRAMs have been particularly highly integrated and mass-produced. The development of such a DRAM cell depends largely on the development of a high-density memory cell technology which occupies an area of more than half of the chip size. At present, various three-dimensional structure DRAM cells have been proposed for the purpose of further increasing the density. Conventionally, this type of three-dimensional structure DRAM cell has a structure as shown in FIG. 2 as an example. In FIG. 2, 1 is a drain forming a bit line, 2 is a gate oxide film of a MOS transistor forming a transfer gate for signal reading, 3 is a word line, for example, a gate electrode formed of polysilicon, Reference numeral 4 is a source diffusion portion of a memory cell, 5 is an insulating thin film that constitutes a capacitor of the memory cell, 6 is a capacitor plate electrode called a cell plate using, for example, polysilicon, 7 is an insulating film for separating cells, and 8 Is a substrate, and 10 is an interlayer insulating film. This is an example of a so-called trench structure memory cell structure. In this structure, since the trench is formed in the depth direction of the substrate 8, the storage capacitance can be sufficiently secured (generally said to be 50 fF or more) for the storage capacitor by controlling the trench depth. Further, in this structure, the trench is used not only as a signal storage capacitor but also for element isolation, and the inter-cell leakage current can be made sufficiently low by making the inter-cell isolation insulating film 7 thick.
立体化構造セルの別の一例として、スタックト構造があ
り、これは第３図に示す様な構成である（例えば、1985
・６・３・日経エレクトロニクスP209〜231）。第３図
において、１はビットラインを形成するドレイン、２は
信号読み出し用トランスファゲートとなるMOSトランジ
スタのゲート酸化膜、３はワード線を構成する、例え
ば、ポリシリコンで形成されたゲート電極、４はメモリ
セルのソース拡散部、５はメモリセルのキャパシタを構
成する絶縁膜、６はセルプレートを形成する、例えば、
ポリシリコンを用いたプレート電極、７はセル間分離用
絶縁膜、８は基板、９はメモリセルのソース部を構成す
る導電性電極、10は層間絶縁膜である。キャパシタは、
プレート電極６とメモリセルのソース部を形成する導電
性電極９との間に形成され、同電極９のワード線上の部
分や側面部をキャパシタとして利用できることにより、
セル容量の増加が得られる。α線ソフトエラーはメモリ
セルのソース部下のpn接合領域に形成される空乏層をα
粒子が通過することにより生ずるが、このスタック構造
では、メモリセルのソース拡散部と基板との間のpn接合
領域が、従来の平面型や前述のトレンチ構成メモリセル
に比べて非常に小さく、そのためα線ソフトエラーに対
して極めて強くなる。As another example of the three-dimensional structure cell, there is a stacked structure, which has a structure as shown in FIG.
・ 6 ・ 3 ・ Nikkei Electronics P209-231). In FIG. 3, 1 is a drain forming a bit line, 2 is a gate oxide film of a MOS transistor serving as a transfer gate for signal reading, 3 is a word line, for example, a gate electrode formed of polysilicon, 4 Is a source diffusion portion of a memory cell, 5 is an insulating film that constitutes a capacitor of the memory cell, and 6 is a cell plate.
A plate electrode made of polysilicon, 7 is an insulating film for separating cells, 8 is a substrate, 9 is a conductive electrode forming a source portion of a memory cell, and 10 is an interlayer insulating film. The capacitor is
Since it is formed between the plate electrode 6 and the conductive electrode 9 forming the source portion of the memory cell, the word line portion and side surface portion of the electrode 9 can be used as a capacitor,
An increase in cell capacity is obtained. The α-ray soft error is due to the depletion layer formed in the pn junction region under the source part of the memory cell by α
This is caused by the passage of particles, but in this stack structure, the pn junction region between the source diffusion part of the memory cell and the substrate is very small as compared with the conventional planar type or the above-mentioned trench configuration memory cell, and Extremely strong against α-ray soft error.
発明が解決しようとする問題点 このような従来の構成では、トレンチ構造、スタックト
構造のそれぞれについて次の様な問題があった。Problems to be Solved by the Invention In such a conventional configuration, there are the following problems for each of the trench structure and the stacked structure.
まずトレンチ構造のメモリセルは、蓄積容量については
トレンチを所定の深さに選べば必要な大きさの値が得ら
れるが、基板深部にトレンチを埋込んでいるため、プレ
ート電極下の基板中の空乏層が大きくなり、α線ソフト
エラー率が同一容量の平面型セルに比べて一桁以上も大
きくなる。そのため、α線ソフトエラー率を低くするに
は平面上のキャパシタセル面積部分を大きくしたりする
必要があり、高集積化には不利となる。First, in a memory cell with a trench structure, the required value can be obtained for the storage capacity if the trench is selected to have a predetermined depth, but since the trench is embedded deep in the substrate, the The depletion layer becomes large, and the α-ray soft error rate becomes more than an order of magnitude higher than that of a planar cell having the same capacity. Therefore, in order to reduce the α-ray soft error rate, it is necessary to increase the area of the capacitor cell area on the plane, which is disadvantageous for high integration.
これに対し、トレンチの側面あるいは底面にイオンを打
ち込む事により、いわゆるHi−Ｃ構造を形成して空乏層
の伸びを押える事もできるが、高濃度注入の結果として
リーク電流の増大や、プロセスの複雑化などが生じ、実
用上問題がある。またトレンチの面にそって、薄い絶縁
膜を形成する必要があるが、トレンチの面の結晶軸に対
する方位によって、絶縁膜（例えばSiO2）の酸化レート
が異なり、一様な厚さの絶縁膜を成長させることが難し
く、絶縁耐圧のバラツキと低下が生じ実用上問題となっ
ている。On the other hand, by implanting ions into the side surface or the bottom surface of the trench, a so-called Hi-C structure can be formed to suppress the extension of the depletion layer, but as a result of high-concentration implantation, an increase in leakage current and process There is a problem in practical use due to complication. In addition, it is necessary to form a thin insulating film along the surface of the trench, but the oxidation rate of the insulating film (eg, SiO 2 ) differs depending on the orientation of the surface of the trench with respect to the crystal axis, and the insulating film having a uniform thickness is formed. Are difficult to grow, and variations and lowering of the withstand voltage occur, which is a practical problem.
また、メモリセルのキャパシタを構成する絶縁膜の誘電
率の増大と絶縁耐圧の増大の両立のために、前記絶縁膜
にSi3N4とSiO2との多層構造を用いる必要があるが、ト
レンチ内壁を構成する基板の単結晶シリコンに、Si2N3
のストレスによる影響が発生し、基板シリコンに欠陥等
が形成されリーク電流が大きくなり実用上問題となる。Further, in order to increase the dielectric constant of the insulating film that constitutes the capacitor of the memory cell and increase the dielectric strength at the same time, it is necessary to use a multilayer structure of Si 3 N 4 and SiO 2 for the insulating film. Si 2 N 3 was added to the single crystal silicon of the substrate that constitutes the inner wall.
The influence of the stress occurs, and defects and the like are formed in the substrate silicon, and the leak current becomes large, which is a practical problem.
これらの問題は、高集積化大容量化を更に推し進める際
には、一層重大な障害となることは明らかである。Obviously, these problems will become more serious obstacles when further increasing the degree of integration and capacity.
一方、スタックト構造は、メモリセルのソース拡散部と
基板とpn接合部の領域が小さく、そのためソフトエラー
に強いという利点をもつ。また素子分離幅が平面型セル
に比べて大きくとれ、素子間リークを容易に押えること
ができる。しかし、その構造上メモリセル容量の増大に
限界があり、素子の微細化高集積化に伴ってメモリセル
容量が不足する。On the other hand, the stacked structure has an advantage that the region of the source diffusion portion of the memory cell, the substrate, and the pn junction is small, and therefore is resistant to soft error. In addition, the element isolation width can be made larger than that of the flat type cell, and the leak between the elements can be easily suppressed. However, there is a limit to the increase in the memory cell capacity due to its structure, and the memory cell capacity becomes insufficient with the miniaturization and high integration of elements.
本発明はこのような問題点を解決するもので、蓄積容量
の増大を実現し、高集積化，大容量化が可能で、ソフト
エラー率、リーク電流が大幅に低減し、キャパシタを構
成する絶縁膜の形成が容易なメモリセル構造を備えた半
導体メモリ装置を提供することを目的としたものであ
る。The present invention solves such a problem, realizes an increase in storage capacity, enables high integration and large capacity, significantly reduces the soft error rate and leakage current, and improves the insulation of a capacitor. An object of the present invention is to provide a semiconductor memory device having a memory cell structure in which a film can be easily formed.
問題点を解決するための手段 この問題点を解決するために本発明は、FCCセルをはじ
めとするトレンチ構造とスタックト構造の長所を共に有
する新規な構造のメモリセルを有する半導体メモリ装置
を提供するものである。Means for Solving the Problems In order to solve the problems, the present invention provides a semiconductor memory device having a memory cell having a novel structure having both advantages of a trench structure including FCC cells and a stacked structure. It is a thing.
本発明は、２本のワード線間にトレンチが形成され、ワ
ード線上及びトレンチ内壁に層間絶縁膜が形成され、ス
タックト構造のキャパシタが前記層間絶縁膜上及びフィ
ールド酸化膜上に形成され、メモリセルのソース部接触
リードを構成する導電性電極とメモリセルのソース拡散
部との電気的コンタクト部がトレンチ内面で形成されも
のである。According to the present invention, a trench is formed between two word lines, an interlayer insulating film is formed on the word line and on the inner wall of the trench, and a capacitor having a stacked structure is formed on the interlayer insulating film and the field oxide film. The electric contact portion between the conductive electrode forming the source portion contact lead and the source diffusion portion of the memory cell is formed on the inner surface of the trench.
作用 本発明によると、トレンチ構造内の側壁の一部でソース
拡散部と接触し、かつ、同トレンチ内部からワード線上
に基板と絶縁的に延在する導電性電極をキャパシタ用の
第１の電極とし、この上に、誘電体を介して、第２の電
極を形成した立体構造のメモリ用キャパシタが得られ、
ソフトエラー，リーク電流特性の高性能のものが得られ
る。According to the present invention, the conductive electrode that is in contact with the source diffusion portion at a part of the side wall in the trench structure and that extends insulatively from the inside of the trench on the word line to the substrate is the first electrode for the capacitor. Then, a three-dimensional structure memory capacitor in which a second electrode is formed on this via a dielectric is obtained,
High-performance soft error and leak current characteristics can be obtained.
実 施 例 第１図は本発明の一実施例による半導体メモリ装置のメ
モリセル部の要部側断面図である。第１図において、１
はビットラインを形成するドレイン、２は信号読み出し
用トランスファゲートを構成するMOSトランジスタのゲ
ート酸化膜、３はワード線を構成する、ポリシリコンで
形成されたゲート電極、４はトレンチ内の側面に拡がる
メモリセルのソース拡散部、５はメモリセルのキャパシ
タを構成するsiO2絶縁膜、６は、ソース拡散部４とトレ
ンチの側面の一部でセルプレートを形成するポリシリコ
ンを用いたプレート電極（第２の電極）、７はセル間分
離用絶縁膜、８は基板、９はメモリセルのソース拡散部
とはトレンチの側壁の一部で接触し、トレンチ内壁およ
びトレンチの周辺の基板上に形成されたポリシリコンを
用いた導電性電極（第１の電極）、10は層間絶縁膜であ
る。キャパシタは、プレート電極６とメモリセルのソー
ス部を形成する導電性電極９との間に形成される。Practical Example FIG. 1 is a side sectional view of an essential part of a memory cell portion of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, 1
Is a drain forming a bit line, 2 is a gate oxide film of a MOS transistor forming a transfer gate for signal reading, 3 is a word line, and a gate electrode is formed of polysilicon. 4 is spread on the side surface in the trench. The source diffusion portion of the memory cell, 5 is a SiO 2 insulating film that constitutes a capacitor of the memory cell, and 6 is a plate electrode (first electrode) using polysilicon that forms a cell plate at a part of the side surface of the source diffusion portion 4 and the trench. 2 electrode), 7 is an insulating film for separating cells, 8 is a substrate, 9 is a part of the side wall of the trench that contacts the source diffusion portion of the memory cell, and is formed on the inner wall of the trench and the substrate around the trench. A conductive electrode (first electrode) using polysilicon, 10 is an interlayer insulating film. The capacitor is formed between the plate electrode 6 and the conductive electrode 9 forming the source part of the memory cell.
この構成により、次の様な作用がある。This configuration has the following effects.
蓄積容量がトレンチ内に埋め込まれた部分とそれ以外の
平面上の部分から成っており、さらにトレンチ内の部分
は、導電性電極９の表面のすべてがセルキャパシタとな
るために容量が極めて増大する。同じセル面積、同じト
レンチ深さの従来形トレンチ構造と比較してもセル容量
は倍以上となる。検討によれば、セル面積が８μm2の場
合、トレンチ深さを３μｍとることによりセル容量を16
0fFとることができ、セル面積が５μm2の場合には、同
じくトレンチ深さを３μｍとして、セル容量を110fFと
ることができ、１つのメモリセルに最低必要とされる容
量の50fFを充分に満たすことができる。The storage capacitance is composed of a portion buried in the trench and a portion on the other plane, and in the portion inside the trench, the capacitance is extremely increased because the entire surface of the conductive electrode 9 becomes a cell capacitor. . Compared with the conventional trench structure having the same cell area and the same trench depth, the cell capacity is more than doubled. According to the examination, when the cell area is 8 μm 2 , the cell capacity is 16 μm when the trench depth is 3 μm.
When the cell area is 5 μm 2 , the cell capacity can be 110 fF with the trench depth of 3 μm, and the minimum required capacity of 50 fF for one memory cell can be sufficiently satisfied. be able to.
またソース部の面積を設計上、あるいはプロセス技術上
許容できる限り小さくすることにより、メモリセルのソ
ース拡散部４と基板８との間のpn接合領域を小さくする
ことができるため、メモリセルのリーク電流を極めて小
さくとることができる。また前記pn接合領域が小さいた
め、それに伴う空乏層も非常に小さくなり、これにより
α線ソフトエラーを抜本的に低減させることができる。
加えてキャパシタとなる薄い絶縁膜５をポリシリコンか
らなる導電性電極９の表面を酸化させて場合、ポリシリ
コンの酸化レートは方位に依存せず一様な厚さの絶縁膜
を成長させることができ、絶縁耐圧のばらつきと低下を
押えることができる。Further, by making the area of the source portion as small as possible in terms of design or process technology, the pn junction region between the source diffusion portion 4 of the memory cell and the substrate 8 can be made small. The current can be made extremely small. Further, since the pn junction region is small, the depletion layer accompanying it is also very small, which can drastically reduce the α-ray soft error.
In addition, when the surface of the conductive electrode 9 made of polysilicon is oxidized by the thin insulating film 5 to be a capacitor, the oxidation rate of polysilicon can grow an insulating film having a uniform thickness regardless of the orientation. Therefore, it is possible to suppress the variation and decrease in the withstand voltage.
さらにメモリセルのキャパシタを構成する絶縁膜として
Si3N4とSiO2との多層構造を用いた場合でも、メモリセ
ルのキャパシタを構成する電極をポリシリコンで形成す
れば、Si3N4のストレスによる影響を基板８に及ぼさず
に吸収できることになり多層絶縁膜の安定形成にも極め
て有利となる。Furthermore, as an insulating film that constitutes the capacitor of the memory cell
Even if a multilayer structure of Si 3 N 4 and SiO 2 is used, if the electrodes forming the capacitor of the memory cell are made of polysilicon, the influence of the stress of Si 3 N 4 can be absorbed without affecting the substrate 8. This is extremely advantageous for stable formation of the multi-layer insulating film.
発明の効果 以上の様に、本発明によれば、半導体メモリ装置は蓄積
容量を極めて大きくできるばかりでなく、ソフトエラー
率及びリーク電流を抜本的に低減でき、プロセス上絶縁
薄膜の形成も容易となる。従って本発明は半導体メモリ
装置の一層の高集積化、大容量化を極めて容易に実現さ
せるという効果が得られる。As described above, according to the present invention, not only the storage capacity of the semiconductor memory device can be extremely increased, but also the soft error rate and the leak current can be drastically reduced, and the insulating thin film can be easily formed in the process. Become. Therefore, according to the present invention, it is possible to obtain an effect that the higher integration and the larger capacity of the semiconductor memory device can be realized very easily.
第１図は本発明の一実施例による半導体メモリセル部を
示す要部側断面図、第２図は従来のトレンチ構造の１例
であるFCC構造メモリセルを示す要部側断面図、第３図
は従来のスタックト構造メモリセルを示す要部側断面図
である。 １……ビットラインを形成するドレイン、２……ゲート
絶縁膜、３……ワードラインを形成するゲート電極、４
……メモリセルのソース拡散部、５……メモリセルのキ
ャパシタを構成する絶縁膜、６……プレート電極、７…
…分離用絶縁膜、８……基板、９……メモリセルのソー
ス部を構成する導電性電極、10……層間絶縁膜。FIG. 1 is a side sectional view showing an essential portion of a semiconductor memory cell portion according to an embodiment of the present invention, and FIG. 2 is a side sectional view showing an essential portion of a FCC structure memory cell which is an example of a conventional trench structure. FIG. 1 is a side sectional view of a main part showing a conventional stacked structure memory cell. 1 ... Drain forming bit line, 2 ... Gate insulating film, 3 ... Gate electrode forming word line, 4
...... Source diffusion part of memory cell, 5 ... Insulating film that constitutes the capacitor of memory cell, 6 ... Plate electrode, 7 ...
... Separation insulating film, 8 ... Substrate, 9 ... Conductive electrode that constitutes the source portion of the memory cell, 10 ... Interlayer insulating film.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/108 Ｈ０１Ｌ 27/04 Ｃ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 27/108 H01L 27/04 C
Claims (2)
効果トランジスタ、同トランジスタのソース領域に接触
するトレンチ構造部および前記トレンチ構造部に近接し
た位置に素子分離領域を有するとともに、前記ソース領
域とは前記トレンチ構造部の側壁の一部分で接触し、前
記ソース領域との接続部以外の半導体基板とは層間絶縁
膜により絶縁され、かつ前記素子分離領域上に延在され
た第１の電極、前記第１の電極上に形成された誘電体膜
および前記誘電体の上に形成された第２の電極からなる
キャパシタをそなえた半導体メモリ装置。1. An insulated gate field effect transistor in a predetermined region of a semiconductor substrate, a trench structure portion in contact with a source region of the transistor, and an element isolation region in a position close to the trench structure portion. Is in contact with a part of the side wall of the trench structure portion, is insulated from the semiconductor substrate other than the connection portion with the source region by an interlayer insulating film, and extends over the element isolation region, the first electrode, A semiconductor memory device comprising a dielectric film formed on a first electrode and a capacitor formed of a second electrode formed on the dielectric.
ト形電界効果トランジスタのゲート電極上に延在された
構成の特許請求の範囲第１項記載の半導体メモリ装置。2. The semiconductor memory device according to claim 1, wherein the first electrode extends over the gate electrode of the insulated gate field effect transistor via an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60279559A JPH0795566B2 (en) | 1985-12-12 | 1985-12-12 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60279559A JPH0795566B2 (en) | 1985-12-12 | 1985-12-12 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62137863A JPS62137863A (en) | 1987-06-20 |
| JPH0795566B2 true JPH0795566B2 (en) | 1995-10-11 |
Family
ID=17612658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60279559A Expired - Lifetime JPH0795566B2 (en) | 1985-12-12 | 1985-12-12 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0795566B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661672B2 (en) * | 1987-08-18 | 1994-08-17 | 日立精機株式会社 | Pallet with indexing device |
| JPS6447068A (en) * | 1987-08-18 | 1989-02-21 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| JP2794750B2 (en) * | 1989-03-07 | 1998-09-10 | 日本電気株式会社 | Semiconductor memory cell and manufacturing method thereof |
| KR930007194B1 (en) * | 1990-08-14 | 1993-07-31 | 삼성전자 주식회사 | Semiconductor device and its manufacturing method |
| US5156993A (en) * | 1990-08-17 | 1992-10-20 | Industrial Technology Research Institute | Fabricating a memory cell with an improved capacitor |
| JP2643860B2 (en) * | 1994-10-26 | 1997-08-20 | 日本電気株式会社 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62136069A (en) * | 1985-12-10 | 1987-06-19 | Hitachi Ltd | Semiconductor device and manufacture of the same |
-
1985
- 1985-12-12 JP JP60279559A patent/JPH0795566B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62137863A (en) | 1987-06-20 |
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