JP2645008B2 - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JP2645008B2 JP2645008B2 JP62076609A JP7660987A JP2645008B2 JP 2645008 B2 JP2645008 B2 JP 2645008B2 JP 62076609 A JP62076609 A JP 62076609A JP 7660987 A JP7660987 A JP 7660987A JP 2645008 B2 JP2645008 B2 JP 2645008B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- groove
- silicon film
- island
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000003860 storage Methods 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 230000015654 memory Effects 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 7
- 230000014759 maintenance of location Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は半導体記憶装置に関し、特に溝型の積層キャ
パシタを有するダイナミックメモリセルに関する。The present invention relates to a semiconductor memory device, and more particularly to a dynamic memory cell having a groove-type multilayer capacitor.
（従来の技術） ダイナミックメモリをはじめとする半導体記憶装置
は、微細加工技術の進歩に伴ってその記憶容量が約３年
で４倍の速度で増大している。このため、限られたシリ
コンチップ上に大量のメモリセルを集積する必要から、
メモリセルの面積を縮小せざるをえない。しかし、メモ
リセルのキャパシタンスの値は、ソフトエラーを防止す
るため、及びセンスアンプに読み出す際のS/N比を確保
するために数＋fFという比較的大きな値を維持する必要
がある。このため、MOS構造のセルキャパシタの酸化膜
を薄膜化してきたが、半導体基板の表面を利用する構造
では、最早キャパシタンスの増大を図ることが困難とな
ってきた。(Prior Art) With the advance of microfabrication technology, the storage capacity of semiconductor memory devices such as dynamic memories has increased four times in about three years. Because of this, it is necessary to integrate a large number of memory cells on a limited silicon chip.
The area of the memory cell must be reduced. However, the value of the capacitance of the memory cell needs to be maintained at a relatively large value of several + fF in order to prevent a soft error and to secure an S / N ratio when reading out to the sense amplifier. For this reason, the oxide film of the cell capacitor having the MOS structure has been reduced in thickness. However, it has become difficult to increase the capacitance in the structure using the surface of the semiconductor substrate.
このようなことから、メモリセルに溝型キャパシタを
使用する方法やセルのまわりに溝を形成し、その側壁を
利用してキャパシタを形成する方法が提案されている
（例えば、S,Nakajima et al,“An Isolation−Merg
ed Vertical Capacitor Cell For Large Capacit
y DRAM",International Electron Device Meeting
Technical Digest,講演番号9.4pp240〜243,1984）。For this reason, a method of using a grooved capacitor in a memory cell or a method of forming a groove around a cell and using a side wall thereof to form a capacitor has been proposed (for example, S, Nakajima et al.). , “An Isolation-Merg
ed Vertical Capacitor Cell For Large Capacit
y DRAM ", International Electron Device Meeting
Technical Digest, lecture number 9.4pp240-243,1984).
こうした、セルのまわりに溝を形成して、その側壁を
利用したキャパシタのダイナミックメモリセルの製造工
程を第３図及び第４図に示す。第３図は第４図のＢ−
Ｂ′線に沿った断面構造である。まず、Ｐ型のシリコン
基板21の表面に格子状に溝22を堀り、１個のメモリセル
領域を島状に残す。続いて、島状になったシリコン領域
23の側壁を利用して第１層の多結晶シリコン膜24を設
け、ストレージノードの拡散層（N+層）25とバリードコ
ンタクト26で接続する。一方、シリコン領域23の側壁に
設けた第１層の多結晶シリコン膜24の表面を酸化して薄
い酸化膜27を形成し、この後第２層の多結晶シリコン膜
28を埋め込む。この第２層の多結晶シリコン膜28をセル
プレートとすることで、多結晶シリコン膜24,28間のキ
ャパシタを形成する。さらに、島状になったシリコン領
域23の表面にワード線29を設けてセルトランスファート
ランジスタを形成する。そして、このワード線29と直交
するようにビット線30を設けて、セルトランスファート
ランジスタのドレイン拡散層（N+層）31に接続させる。FIGS. 3 and 4 show a manufacturing process of such a dynamic memory cell of a capacitor in which a groove is formed around the cell and the side wall is used. FIG. 3 is a cross-sectional view of FIG.
It is a cross-sectional structure along the line B '. First, grooves 22 are dug out in a lattice pattern on the surface of a P-type silicon substrate 21 to leave one memory cell region in an island shape. Then, the island-shaped silicon area
A first-layer polycrystalline silicon film 24 is provided using the side wall 23 and is connected to a diffusion layer (N + layer) 25 of a storage node by a buried contact 26. On the other hand, the surface of the first-layer polycrystalline silicon film 24 provided on the side wall of the silicon region 23 is oxidized to form a thin oxide film 27, and thereafter, the second-layer polycrystalline silicon film 24 is formed.
Embed 28. By using the polycrystalline silicon film 28 of the second layer as a cell plate, a capacitor between the polycrystalline silicon films 24 and 28 is formed. Further, a word line 29 is provided on the surface of the island-shaped silicon region 23 to form a cell transfer transistor. Then, a bit line 30 is provided so as to be orthogonal to the word line 29, and is connected to a drain diffusion layer (N + layer) 31 of the cell transfer transistor.
この構造のメモリセルの特徴は、島状になったシリコ
ン領域23の側壁を有効に利用しており、比較的小さな面
積で大きなキャパシタンスを得られることである。A feature of the memory cell having this structure is that the side wall of the island-shaped silicon region 23 is effectively used, and a large capacitance can be obtained with a relatively small area.
上述した従来のダイナミックメモリセルには次のよう
な欠点があった。すなわち、島状のシリコン領域23の側
壁に形成した第１層の多結晶シリコン層24のストレージ
ノードはVssからVccの電位で振幅する。したがって、側
壁に寄生のトランジスタが形成され、ビット線30と接続
したドレイン拡散層31とストレージノード側の拡散層25
間にリーク電流が発生する。このリーク電流により、メ
モリセルの記憶保持時間が著しく劣化される。The conventional dynamic memory cell described above has the following disadvantages. That is, the storage node of the first polycrystalline silicon layer 24 formed on the side wall of the island-shaped silicon region 23 oscillates at a potential of Vss to Vcc. Therefore, a parasitic transistor is formed on the side wall, and the drain diffusion layer 31 connected to the bit line 30 and the diffusion layer 25 on the storage node side are formed.
Leakage current occurs between them. Due to this leak current, the storage retention time of the memory cell is significantly deteriorated.
この対策としては、島状のシリコン領域23の側壁表面
にフィールド反転防止用のイオン注入又は拡散を行う
か、厚いフィールド酸化膜を形成する方法があるが、い
ずれも根求対策となり得ない。As a countermeasure, there is a method of performing ion implantation or diffusion for preventing field inversion on the side wall surface of the island-shaped silicon region 23, or forming a thick field oxide film.
（発明が解決しようとする問題点） 本発明は上記問題点を解決するためになされたもの
で、従来の製造工程を大きく変更することなく、高い記
憶保持特性を有する半導体記憶装置を提供することを目
的とする。(Problems to be Solved by the Invention) The present invention has been made in order to solve the above problems, and provides a semiconductor memory device having high storage retention characteristics without largely changing a conventional manufacturing process. With the goal.
［発明の構成］ （問題点を解決するための手段と作用） すなわち、本発明は半導体記憶装置は、半導体基板
と、この半導体基板の表面に形成された格子状の溝及び
この溝で囲まれた島状領域と、この隣接する島状領域そ
れぞれに前記溝を挟んで互いに向かい合うように設けら
れたセルトランジスタと、前記島状領域それぞれの周囲
側壁を連続して囲みかつ溝底部の半導体基板と電気的接
続がなされたセルプレート電極となる第１の多結晶シリ
コン膜と、この第１の多結晶シリコン膜で覆われた溝内
の側壁両側に薄い絶縁膜を介し対向して設けられ前記島
状領域それぞれの周囲を連続して囲んだストレージノー
ドとなる第２の多結晶シリコン膜と、この第２の多結晶
シリコン膜で囲まれた溝中央部の埋め込み絶縁膜とを具
備したことを特徴とする。[Structure of the Invention] (Means and Action for Solving the Problems) That is, according to the present invention, a semiconductor memory device includes a semiconductor substrate, a lattice-shaped groove formed on the surface of the semiconductor substrate, and the semiconductor memory device. And a cell transistor provided in each of the adjacent island regions so as to face each other with the groove interposed therebetween, and a semiconductor substrate continuously surrounding the peripheral side walls of each of the island regions and at the bottom of the groove. A first polycrystalline silicon film serving as a cell plate electrode to which electrical connection is made, and the island provided on both sides of a side wall in a groove covered with the first polycrystalline silicon film via a thin insulating film; A second polycrystalline silicon film serving as a storage node that continuously surrounds the periphery of each of the linear regions, and a buried insulating film at the center of the trench surrounded by the second polycrystalline silicon film. When That.
（実施例） 以下、図面を参照して本発明の実施例を詳細に説明す
る。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例であるダイナミックメモリ
セルの断面図、第２図は平面図で、第１図は第２図のＡ
−Ａ′線に沿った断面構造である。図中、Ｐ型のシリコ
ン基板１の表面に格子状に溝（深さ〜数μｍ）２を形成
し、１個のメモリセルあたり１個の島状のシリコン領域
３を形成する。次に、この島状のシリコン領域３の側壁
及び底部を利用して第１層の多結晶シリコン膜４を設け
る。そして、溝２の下部にはN+拡散層５を形成して第１
層の多結晶シリコン膜４と接続させ、このN+拡散層５に
セルプレート電位を印刷する。続いて、第１層の多結晶
シリコン層４の表面を酸化して薄い酸化膜６を形成す
る。さらに、この薄い酸化膜６を介して第１層の多結晶
シリコン膜４の内側に第２層の多結晶シリコン膜７を形
成する。次に、溝２の絶縁膜18で埋め込むことにより、
セル間の第２層の多結晶シリコン膜７間を絶縁させる。
また、第２層の多結晶シリコン膜７は溝２の角部におい
て、セルストレージノードの拡散層９とバリードコンタ
クト10で接続させる。一方、島状になったシリコン領域
３の表面にワード線11を設けて、セルトランスファート
ランジスタを形成する。また、ワード線11と直交するよ
うにビット線12を設けて、セルトランスファートランジ
スタのドレイン拡散層（N+）13に接続させる。ワード線
11として第３層に多結晶シリコン膜がシリサイドが望ま
しい。一方、ビット線12は第４層の多結晶シリコン膜が
シリサイドまたはアルミニウムのような金属配線とす
る。FIG. 1 is a cross-sectional view of a dynamic memory cell according to an embodiment of the present invention, FIG. 2 is a plan view, and FIG.
It is a cross-sectional structure along the line -A '. In the figure, grooves (depth to several μm) 2 are formed in a lattice pattern on the surface of a P-type silicon substrate 1, and one island-shaped silicon region 3 is formed for each memory cell. Next, a first-layer polycrystalline silicon film 4 is provided using the side walls and the bottom of the island-shaped silicon region 3. Then, an N + diffusion layer 5 is formed below the groove 2 to form the first
The N + diffusion layer 5 is connected to the polycrystalline silicon film 4 and a cell plate potential is printed on the N + diffusion layer 5. Subsequently, the surface of the first polycrystalline silicon layer 4 is oxidized to form a thin oxide film 6. Further, a second-layer polycrystalline silicon film 7 is formed inside the first-layer polycrystalline silicon film 4 with the thin oxide film 6 interposed therebetween. Next, by embedding with the insulating film 18 of the groove 2,
The second layer polycrystalline silicon film 7 is insulated between cells.
Further, the polycrystalline silicon film 7 of the second layer is connected to the diffusion layer 9 of the cell storage node at the corner of the groove 2 by the buried contact 10. On the other hand, a word line 11 is provided on the surface of the island-shaped silicon region 3 to form a cell transfer transistor. Further, a bit line 12 is provided so as to be orthogonal to the word line 11, and is connected to a drain diffusion layer (N + ) 13 of the cell transfer transistor. Word line
It is preferable that the polycrystalline silicon film be silicide in the third layer. On the other hand, the bit line 12 has a fourth-layer polycrystalline silicon film formed of metal wiring such as silicide or aluminum.
この構造のメモリセルによれば、島状のシリコン領域
３の側壁に形成される寄生トランジスタのオン電圧をセ
ルプレート電位で制御することが可能となり、絶縁膜に
印加される電界を最小にするため1/2Vcc電位とした場
合、この電圧でリーク電流が流れない条件（側壁の表面
濃度、フィールド酸化膜）を設定すれば、比較的容易に
高い記憶保持特性を有したダイナミックメモリセルを実
現できる。According to the memory cell having this structure, the on-voltage of the parasitic transistor formed on the side wall of the island-shaped silicon region 3 can be controlled by the cell plate potential, and the electric field applied to the insulating film can be minimized. In the case where the potential is set to 1/2 Vcc, a dynamic memory cell having a high storage retention characteristic can be relatively easily realized by setting conditions under which a leak current does not flow at this voltage (sidewall surface concentration, field oxide film).
また、上記構造は、製造工程的にも従来工程を変更す
ることなく実現でき、さらに側壁表面にフィールド反転
防止用の高濃度のイオン注入または拡散をする必要がな
く、また島状のシリコン領域３の側壁表面に厚いフィー
ルド酸化膜を形成する必要もなく極めて製造が容易にな
る。Further, the above structure can be realized without changing the conventional process in the manufacturing process, further, it is not necessary to perform high concentration ion implantation or diffusion on the side wall surface to prevent field inversion, and the island-shaped silicon region 3 It is extremely easy to manufacture without having to form a thick field oxide film on the surface of the side wall.
［発明の効果］ 以上のように本発明によれば、半導体基板の表面に格
子状に溝を形成して島状領域を設け、この島状領域の側
壁に第１の多結晶シリコン膜を設けてメモリセルのプレ
ート電極とし、さらのその内側に絶縁膜を介して第２の
多結晶シリコン膜を溝内で対向するように設け、これを
メモリセルのストレージノードとした構造とし、島状領
域の側壁に形成される寄生トランジスタのオン電圧をセ
ルプレート電位で制御できるようにしたので、島状領域
の側壁に形成される寄生トランジスタによるリーク電流
を抑制することが可能であり、極めて高い記憶保持特性
を有する半導体記憶装置を実現できる。[Effects of the Invention] As described above, according to the present invention, island-shaped regions are provided by forming grooves in a grid on the surface of a semiconductor substrate, and the first polycrystalline silicon film is provided on the side walls of the island-shaped regions. And a second polycrystalline silicon film is further provided on the inside thereof so as to face the inside of the groove through an insulating film via an insulating film, and this is used as a storage node of the memory cell. The on-voltage of the parasitic transistor formed on the side wall of the cell can be controlled by the cell plate potential, so that the leakage current due to the parasitic transistor formed on the side wall of the island region can be suppressed, and extremely high memory retention A semiconductor memory device having characteristics can be realized.
第１図は本発明の一実施例に係るダイナミックメモリセ
ルの断面図、第２図は同じく平面図、第３図は従来のダ
イナミックメモリセルの断面図、第４図は同じく平面図
である。 １……シリコン基板、２……溝、３……シリコン領域、
４……第１の多結晶シリコン膜、５……N+拡散層、７…
…第２の多結晶シリコン膜。1 is a sectional view of a dynamic memory cell according to an embodiment of the present invention, FIG. 2 is a plan view of the same, FIG. 3 is a sectional view of a conventional dynamic memory cell, and FIG. 1 ... silicon substrate, 2 ... groove, 3 ... silicon area,
4... First polycrystalline silicon film, 5... N + diffusion layer, 7.
... Second polycrystalline silicon film.
Claims (1)
成された格子状の溝及びこの溝で囲まれた島状領域と、
この隣接する島状領域それぞれに前記溝を挟んで互いに
向かい合うように設けられたセルトランジスタと、前記
島状領域それぞれの周囲側壁を連続して囲みかつ溝底部
の半導体基板と電気的接続がなされたセルプレート電極
となる第１の多結晶シリコン膜と、この第１の多結晶シ
リコン膜で覆われた溝内の側壁両側に薄い絶縁膜を介し
対向して設けられ前記島状領域それぞれの周囲を連続し
て囲んだストレージノードとなる第２の多結晶シリコン
膜と、この第２の多結晶シリコン膜で囲まれた溝中央部
の埋め込み絶縁膜とを具備したことを特徴とする半導体
記憶装置。A semiconductor substrate, a lattice-shaped groove formed on the surface of the semiconductor substrate, and an island region surrounded by the groove;
A cell transistor provided in each of the adjacent island-shaped regions so as to face each other with the groove interposed therebetween, and a peripheral sidewall of each of the island-shaped regions was continuously surrounded and electrically connected to the semiconductor substrate at the bottom of the groove. A first polycrystalline silicon film serving as a cell plate electrode is provided on both sides of a side wall in a trench covered with the first polycrystalline silicon film with a thin insulating film interposed therebetween. A semiconductor memory device comprising: a second polycrystalline silicon film to be a storage node continuously surrounded; and a buried insulating film at a center of a groove surrounded by the second polycrystalline silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62076609A JP2645008B2 (en) | 1987-03-30 | 1987-03-30 | Semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62076609A JP2645008B2 (en) | 1987-03-30 | 1987-03-30 | Semiconductor storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63241961A JPS63241961A (en) | 1988-10-07 |
| JP2645008B2 true JP2645008B2 (en) | 1997-08-25 |
Family
ID=13610079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62076609A Expired - Lifetime JP2645008B2 (en) | 1987-03-30 | 1987-03-30 | Semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2645008B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2517015B2 (en) * | 1987-11-06 | 1996-07-24 | シャープ株式会社 | Method of manufacturing semiconductor memory |
| US5047815A (en) * | 1988-08-18 | 1991-09-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device having a trench-stacked capacitor |
| JP3466851B2 (en) * | 1997-01-20 | 2003-11-17 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0793366B2 (en) * | 1984-10-08 | 1995-10-09 | 日本電信電話株式会社 | Semiconductor memory and manufacturing method thereof |
-
1987
- 1987-03-30 JP JP62076609A patent/JP2645008B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| 日経マイクロデバイス、１９８７年１月号、ＰＰ．５９−７３ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63241961A (en) | 1988-10-07 |
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