JPS62248248A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the storage capacitance of a memory cell by forming a first capacitor section buried into a trench and a second capacitor section shaped to a planar shape. CONSTITUTION:A first capacitor uses an insulating thin-film 10a shaped on the inner wall of a trench as a dielectric and a first polysilicon layer 11 burying a high impurity-concentration region and the inside of the trench and connected to a source region as a counter electrode. A second capacitor consists of the first polysilicon layer 11, an insulating thin film 10b as a dielectric laminated on the polysilicon layer 11 and a second polysilicon layer 12 connected to the high impurity-concentration region in a substrate 1. Accordingly, the storage capacitance of a memory cell is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to the structure of a memory cell serving as an information storage section.

(Prior Art) In recent years, the degree of integration of semiconductor memory devices, especially DRAMs, has been remarkable. This DRAM.

A memory cell array consisting of a capacitor that stores stored information in the form of charge and a switching transistor that reads and writes the charge is arranged in an array, and a peripheral circuit is formed on the same chip. As the capacity and integration have increased, the memory cell array has come to occupy most of the chip area, and miniaturization of individual memory cells has become essential for increasing the capacity and integration. For this reason, recently, memory cells having trench capacitors as shown in FIG. 2, which can ensure sufficient storage capacity even when miniaturized, are being adopted.

This trench capacitor has a trench formed in the Si substrate 21, and a MOS transistor which is a switching transistor electrically connected to the semiconductor substrate surface on the inner wall of the trench.
A structure in which the source part 22 of the transistor is used as one capacitor electrode, an oxide film is grown on the inner wall of the trench as a capacitor insulating film 23, and polysilicon, for example, is deposited thereon as a cell plate electrode 24 that serves as the other capacitor electrode. It has become. Charge as stored information is exchanged from the trench capacitor section via the source section 22 to the drain section 26 forming part of the bit line 25 by turning on and off the above-mentioned MOS transistor. Note that 28 is a gate oxide film, and 29 is a gate electrode.

(Problems to be Solved by the Invention) However, a problem with this type of memory cell is that the capacitor part is formed in a trench buried deep in the substrate, so the effective area of the capacitor part becomes large. 9
Although sufficient cumulative capacitance can be secured, when the information "1" is maintained in the capacitor, that is, when the source part 22 and the surface of the Si substrate 21 on the inner wall of the trench are in a high potential state, a depletion layer 27 is formed in these parts. spreads, and the amount of electrons generated when α rays emitted from the package material housing the chip pass through the Si substrate 21 increases, making the capacitor softer than a planar cell capacitor with the same storage capacity. There was a problem in that the error rate worsened by one order of magnitude or more. Furthermore, if the information held between adjacent cell capacitors is different,
That is, when there is a potential difference between the cell capacitors, the depletion layers of both cell capacitors are connected and a so-called punch-through current flows due to the potential gradient, and this current becomes a leakage current that indicates the pause time, which indicates the memory retention ability of the DRAM. There was a problem that the characteristics deteriorated.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate having a low impurity concentration region formed on a low impurity concentration region on a high impurity concentration region. M for reading the signal
(OS transistor and its MOS) - A trench is formed adjacent to the source region of the transistor and penetrates into the high impurity concentration region of the semiconductor substrate, and an insulating thin film formed on the inner wall of this trench is used as a dielectric, and the high impurity concentration region is and a first capacitor portion having a first polysilicon layer filled in the trench and electrically connected to the source region as a counter electrode, and a first polysilicon layer extending to a required portion; A second capacitor section is formed of a laminated insulating thin film as a dielectric, a second polysilicon layer electrically connected to a high impurity concentration region of a semiconductor substrate, and an interlayer is formed on the second capacitor section. The bit line conductive layer is formed through an insulating layer and electrically connected to the drain region of the MOS transistor.

(Function) According to this configuration, the capacitance of the memory cell capacitor is determined by the capacitance of the trench portion between the high concentration region of the semiconductor substrate and the first polysilicon layer, and the capacitance of the trench portion between the first polysilicon layer and the second polysilicon layer. This is the sum of the capacitances of the flat capacitors between the polysilicon layer and the capacitor, and even if the capacitor reaches a high potential, the highly doped substrate prevents the expansion of the depletion layer in the capacitor part, and the electrons generated by α rays are The collection amount is drastically reduced and bunch-through current between adjacent cells is also suppressed. Furthermore, the parallel combination of two capacitors significantly increases storage capacity compared to conventional trench capacitors, allowing further miniaturization of memory cells.

(Example) Examples will be described below with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a memory cell portion of a semiconductor memory device showing one embodiment of the present invention. 1 is 10
2 is a p-type St substrate with a high concentration of about 100% /ffl, and serves as one plate electrode of the cell capacitor section. 2 is a p-type Si epitaxial layer grown on it, with a lower concentration than that of the p-type Si substrate 1. 3 is a p-type isolation diffusion layer for preventing the generation of parasitic MOS transistors, 4 is an isolation oxide film thereon, 5 is a gate oxide film of a MOS transistor which is a switching transistor, 6 is its gate electrode, and 7 is a drain. It is connected to the bit line at the n0 diffusion.

8 is a source n3 diffusion part, 9 is an interlayer insulating film between each electrode, l
Oa and IOb are insulating thin films constituting the dielectric of the cell capacitor section, 11 is a storage electrode of the capacitor section made of polysilicon, and 12 is the other plate electrode of the capacitor section made of polysilicon; 1 (not shown) is the SL substrate. 1 is electrically connected to. 13 is an AQ wiring for the bit line.

The cell capacitor with the above structure consists of a first capacitor part buried in a trench and a second capacitor part formed in a plane. Even when the dimensions are reduced, the absolute value of the storage capacitance can be adjusted according to the design specifications by appropriate distribution of trench depth and planar portion.

In addition, by reducing the area of the source n0 diffusion part 8 to the allowable limit in terms of design and process, the junction diffusion area can be reduced, making it possible to improve the leakage characteristics that determine the refresh operation, and furthermore, use a highly doped substrate. Since the expansion of the depletion layer on the inner wall of the trench and on the substrate side can be sufficiently suppressed, the amount of collected electrons generated by α rays is reduced, and leakage current between adjacent cells is also suppressed.

(Effects of the Invention) As explained above, according to the present invention, the storage capacity of memory cells can be increased, the soft error resistance is sufficient, leakage between cells can be ignored, and the structure can be miniaturized. This enables even higher integration and larger capacity to be achieved6.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a memory cell portion of a semiconductor memory device showing an embodiment of the present invention, and FIG. 2 is a sectional view of a memory cell portion of a conventional trench structure. 1...High concentration p-type S1 substrate, 2...Low concentration p-type epitaxial layer, 3...Diffusion layer for element isolation, 4.
... Oxide film for element isolation, 5... Gate oxide film of MOS transistor, 6... Gate electrode of MOS transistor, 7... Drain n+ diffusion part, 8... Source n+ diffusion part, 9...・Interlayer insulation film, IOa, IO
b... Capacitor insulating thin film, 11... Storage electrode, 12... Plate electrode, 13... AD wiring for bit line. Patent applicant: Matsushita Electronics Co., Ltd. Figure 1

Claims (1)

[Claims] A signal readout MOS transistor formed on the low impurity concentration region of one conductivity type semiconductor substrate having a low impurity concentration region on the high impurity concentration region, and the semiconductor substrate formed adjacent to the source region of the MOS transistor. A trench that penetrates into a high impurity concentration region of the substrate, and an insulating thin film formed on the inner wall of this trench as a dielectric, and a trench that fills the high impurity concentration region and the trench and is electrically connected to the source region. a first capacitor portion having one polysilicon layer as a counter electrode, the first polysilicon layer extending to a required portion, an insulating thin film as a dielectric layered thereon, and a height of the semiconductor substrate. A second capacitor section made of a second polysilicon layer electrically connected to the impurity concentration region; 1. A semiconductor memory device comprising a conductive layer for a bit line which are connected to each other, and wherein the first capacitor section and the second capacitor section are used as a memory cell capacitor.