JPS63318151A - Dram memory cell - Google Patents

Dram memory cell

Info

Publication number
JPS63318151A
JPS63318151A JP62153436A JP15343687A JPS63318151A JP S63318151 A JPS63318151 A JP S63318151A JP 62153436 A JP62153436 A JP 62153436A JP 15343687 A JP15343687 A JP 15343687A JP S63318151 A JPS63318151 A JP S63318151A
Authority
JP
Japan
Prior art keywords
capacitor
lower electrode
type
diffusion layer
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62153436A
Other languages
Japanese (ja)
Inventor
Kenji Anzai
賢二 安西
Akito Nishitani
西谷 明人
Ichiro Murai
一郎 村井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62153436A priority Critical patent/JPS63318151A/en
Publication of JPS63318151A publication Critical patent/JPS63318151A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase the charge storage capacity by increasing the junction capacity only in the diffused layer part connected to a capacitor lower electrode. CONSTITUTION:A field oxide film 22 is formed in a non-active region on a P type silicon substrate 21 while a gate oxide film 23, a gate electrode 24 and a pair of N type diffused layers 25a, 25b are formed in an active region to constitute a transistor. A part of the N type diffused layer 25b is connected to a capacitor lower electrode 28 on an insulating film 26 through a selfcontact 27 as an opening made in overall surface of the insulating film 26 and the gate oxide film 23 on the substrate 21 and then a capacitor dielectric film 28 and a capacitor upper electrode 30 are arranged on the capacitor lower electrode 28 to constitute a memory capacitor. Furthermore, in the P type silicon substrate 21, an impurity region 31 is formed only below one N type diffused layer 25b connected to the capacitor lower electrode 28.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、1トランジスタ、1キヤノぐシタ型のDR
AM (ダイナミック・ランダム拳アクセスeメそりン
メモリセルに勿するものである。
[Detailed Description of the Invention] (Industrial Application Field) This invention is a one-transistor, one-canon type DR
AM (dynamic random access memory cell).

(従来の技術) 一般にDRAMのメモリセルは、1トランジスタ・1キ
ヤパシタからなり、キャパシタに電荷を蓄積することに
より情報の記憶を行っている。従来、この種のメモリセ
ルとしては、2次元の平面構造からなるプレーナ型メモ
リセルが用いられてきたが、メグビット級のDRAMで
は、キャノぐシタを上方に積み上けるスタック型メモリ
セルや、半導体基板に溝を堀ジ、該溝内にキャノぐシタ
を形成するトレンチ型メモリセルといった3次元構造化
により実効的なキャノぐシタ面積を増大させるメモリセ
ルが使われ始めている。その理由は、キャパシタの容量
が小はい(すなわち、キャパシタに蓄積される電荷蓋が
少ない)場合、回路の誤動作(記憶信号が小さいため)
や、アルファ線によるンフトエラーが起こりやすくなる
などの問題が住じることにある。
(Prior Art) A DRAM memory cell generally consists of one transistor and one capacitor, and stores information by accumulating charge in the capacitor. Conventionally, planar memory cells with a two-dimensional planar structure have been used as this type of memory cell, but in megbit-class DRAMs, stacked memory cells in which cells are stacked upward, or semiconductors are used. Memory cells are beginning to be used that increase the effective canopy area through three-dimensional structuring, such as trench-type memory cells in which a trench is dug in a substrate and a canopy is formed within the trench. The reason is that if the capacitance of the capacitor is small (i.e. less charge is stored in the capacitor), the circuit malfunctions (because the stored signal is small)
This can lead to problems such as increased susceptibility to nufting errors due to alpha rays.

第2図は従来の通常のスタック型メモリセルの断面図で
ある。この図において、1Fipuシリコン基板であり
、このP型シリコン基板1上の非能動領域にフィールド
酸化膜2が形、成される一方、能動領域にゲート酸化膜
3.ゲート電極4および一対のN型拡散層5a、5bが
形成されトランジスタが構成されている。そして、その
トランジスタを構成する一方のN型拡散層5bの一部が
、基板1上の全面の絶縁膜6およびゲート酸化膜3の開
孔部7(以後セルフコンタクトと記す)を通して該絶縁
膜6上のN型ポリシリコンよりなるキャパシタ下部電極
8に接続されておシ、このキャパシタ下部電極8上にキ
ャ/、oシタ誘電体膜9、更にN型ポリシリコンよりな
るキャパシタ上部電極10が配餘されメモリキャノにシ
タが構成される。
FIG. 2 is a cross-sectional view of a conventional conventional stacked memory cell. In this figure, a 1-Fipu silicon substrate is shown, and a field oxide film 2 is formed in the non-active region on this P-type silicon substrate 1, while a gate oxide film 3 is formed in the active region. A gate electrode 4 and a pair of N-type diffusion layers 5a and 5b are formed to constitute a transistor. Then, a part of one N-type diffusion layer 5b constituting the transistor passes through the insulating film 6 on the entire surface of the substrate 1 and the opening 7 (hereinafter referred to as self-contact) in the gate oxide film 3. It is connected to the upper capacitor lower electrode 8 made of N-type polysilicon, and on this capacitor lower electrode 8, a capacitor dielectric film 9, and further a capacitor upper electrode 10 made of N-type polysilicon are disposed. Then, the memory is configured.

この構造では、上方に積み上けられたメモリキャパシタ
およびP型シリコン基板1とN型拡散層5bによる接合
容量とから一定の容量を得ることができる。
In this structure, a certain capacity can be obtained from the memory capacitor stacked above and the junction capacitance formed by the P-type silicon substrate 1 and the N-type diffusion layer 5b.

(発明が解決しようとする問題点) しかしながら、上記のような従来のスタック型メモリセ
ルは次のような欠点を有している。まず、上方に積み上
げられたメモリキャパシタでは、電荷蓄積容量を増大ざ
ぜるため、凹凸を設けて実効的な表面積を増大式ぜる、
あるいはキャパシタ誘電体膜9を薄くするなどの構造が
考えられるが、誘電体膜9を薄くした場合は、耐圧の低
下および電荷の漏れが間組とクク、また前者の凹凸を設
ける場合は、七の後の微細パターン形成が困難となる。
(Problems to be Solved by the Invention) However, the conventional stacked memory cell as described above has the following drawbacks. First, in the memory capacitors stacked upward, in order to increase the charge storage capacity, unevenness is provided to increase the effective surface area.
Alternatively, a structure such as making the capacitor dielectric film 9 thinner can be considered, but if the dielectric film 9 is made thinner, the withstand voltage will drop and the leakage of charge will occur. Subsequent fine pattern formation becomes difficult.

このように、メモリキャパシタでは、物理的またはプロ
セス的な制約に工って一定値以上の電荷蓄積容量を得る
ことは難しい。次に、P型シリコン基板lとN型拡散層
5bによる接合容■は、基本的匹は、低濃度側に該当す
るP型シリコン基板lの濃度を良くすれば空乏層拡がシ
が抑えられ接合容量か増加するが、P型シリコン基板1
とキャパシタ下部電極に接続でれるN型拡散層5b以外
の接合容量も同時に増加するため、トランジスタ延いて
は回路のスピードの低下、あるいは充放電電荷増による
消費電流の増加をもたらしてしまう。
As described above, in a memory capacitor, it is difficult to obtain a charge storage capacity of a certain value or more by modifying physical or process constraints. Next, regarding the junction capacity (2) between the P-type silicon substrate 1 and the N-type diffusion layer 5b, basically, if the concentration of the P-type silicon substrate 1, which corresponds to the low concentration side, is increased, the expansion of the depletion layer can be suppressed. Junction capacitance increases, but P-type silicon substrate 1
Since the junction capacitance other than the N-type diffusion layer 5b connected to the lower electrode of the capacitor also increases at the same time, this results in a reduction in the speed of the transistor and the circuit, or an increase in current consumption due to an increase in charging and discharging charges.

以上のように、従来のスタック型メモリセルでは、半導
体プロセスまたは物理的制約、あるいは回路性能上の制
約から、一定値以上の電荷蓄積容量を得ることはできな
かった。
As described above, in conventional stacked memory cells, it has not been possible to obtain a charge storage capacity of a certain value or more due to semiconductor process, physical constraints, or circuit performance constraints.

この発明は、以上述べた半導体プロセスまたは物理的制
約および回路性能上の問題を伴うことなく電荷蓄積容量
を増加させることのできるスタック型のDRAMメモリ
セルを提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a stacked DRAM memory cell whose charge storage capacity can be increased without the above-mentioned semiconductor process or physical limitations and circuit performance problems.

(問題点を解決するための手段) この発明は、スタック型の1トランジスタ・1キヤノぐ
シタDRAMメモリセルにおいて、キャパシタ下部電極
と接続されるトランジスタの一方の拡散層の領域下での
養牛導体基板に、該基板の不純物一度より筒い高濃度不
純物領域を形成するものである。
(Means for Solving the Problems) The present invention provides a stacked one-transistor/one-canon DRAM memory cell in which a feeding conductor is formed under a diffusion layer region of one of the transistors connected to a capacitor lower electrode. A highly concentrated impurity region is formed in a substrate, which is longer than the impurities in the substrate.

(作 用) 上記のような構造によれば、高濃度不純物領域により、
キャパシタ下部電極に接続てれる拡散層部分でのみ接合
容量が増大し、電荷蓄積容量が増大する。
(Function) According to the above structure, due to the high concentration impurity region,
Junction capacitance increases only in the diffusion layer portion connected to the capacitor lower electrode, and charge storage capacity increases.

(実施例) 以下この発明の一実施例を図面を参照して説明する。第
1図はこの発明の一実施例の断面図である。この図にお
いて、21はP型シリコン基板であシ、この基板21上
の非能動領域にフィールド酸化膜22が形成される一方
、能動領域にゲート酸化膜23.ゲート電極24および
一対のN型拡散層25a、25bが形成されトランジス
タカ構成されている。そして、そのトランジスタを構成
する一方のN型拡散層25bの一部が、基板21上の全
面の絶縁膜26およびゲート酸化膜23に開けた開孔部
であるセルフコンタクト27’&Aして該絶縁膜26上
のN型ポリシリコンよりなるキャノ々シタ下部t&28
に接続されておジ、このキャパシタ下部電極28上にキ
ャパシタ誘電体膜29、更にN型ポリシリコンよりなる
キャパシタ上部電極30が配置されメモリキャノぐシタ
が構成されている。また、P型シリコン基板21内には
、前記トラン7スタの一対の拡散層25a、25bのう
ち、前記キャパシタ下部電極28と接続される一方のN
型拡散層25bの下に限定して、しかも、この例では、
その一方のN型拡散層25b下のうち、該拡散層25b
が前記キャパシタ下部電極28と接続される領域の下に
限定して、P型シリコン基板21の不純物濃度(1×1
014〜5×1016cIn−3)より高い不純物濃度
(I X 1017〜l X 1018cm−3)の、
基板21と同極性(P型)の不純物領域31が形成され
る。したがって、このメモリセルによれば、キャパシタ
下部電極28に接続される拡散層25bの部分でのみ接
合容量が増大し、電荷蓄積容量が増大する。
(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention. In this figure, reference numeral 21 denotes a P-type silicon substrate, on which a field oxide film 22 is formed in the non-active region, while a gate oxide film 23 is formed in the active region. A gate electrode 24 and a pair of N-type diffusion layers 25a and 25b are formed to constitute a transistor. Then, a part of one N-type diffusion layer 25b constituting the transistor forms a self-contact 27'&A, which is an opening formed in the insulating film 26 and gate oxide film 23 on the entire surface of the substrate 21, and forms the insulating film 27'&A. Canopy lower part t&28 made of N-type polysilicon on film 26
A capacitor dielectric film 29 and a capacitor upper electrode 30 made of N-type polysilicon are arranged on the capacitor lower electrode 28 to form a memory canister. Further, in the P-type silicon substrate 21, one of the pair of diffusion layers 25a and 25b of the transistor 7 is connected to the capacitor lower electrode 28.
Limited to the area below the type diffusion layer 25b, and in this example,
The diffusion layer 25b under one of the N-type diffusion layers 25b
The impurity concentration (1×1
014~5x1016cIn-3) with a higher impurity concentration (Ix1017~lx1018cm-3),
An impurity region 31 having the same polarity (P type) as the substrate 21 is formed. Therefore, according to this memory cell, the junction capacitance increases only in the portion of the diffusion layer 25b connected to the capacitor lower electrode 28, and the charge storage capacity increases.

なお、上記一実施例では、キャ)J?シシタ部電極28
と接続される部分に限定してN型拡散層25b下に高濃
度不純物領域31を形成したが、N型拡散層25bの下
全体に高濃度不純物領域を形成するようにしてもよい。
Note that in the above embodiment, ca) J? Shishita part electrode 28
Although the high concentration impurity region 31 is formed under the N type diffusion layer 25b only in the portion connected to the N type diffusion layer 25b, the high concentration impurity region 31 may be formed entirely under the N type diffusion layer 25b.

(発明の効果) 以上絆述したように、この発明のDRAMメモリセルに
よれば、キャパシタ下部電極に接続される拡散層部分で
のみ接合容量を増大させ、電荷蓄積容量を増大させるよ
うにしたので、メモリキャノξシタ面8jを変えること
なく電荷蓄積容iを増加させることができ、メモリキャ
パシタに凹凸を設けて実効的な表面積を増大させる必要
がなくなる。
(Effects of the Invention) As described above, according to the DRAM memory cell of the present invention, the junction capacitance is increased only in the diffusion layer portion connected to the capacitor lower electrode, and the charge storage capacity is increased. , it is possible to increase the charge storage capacity i without changing the memory capacitor ξ storage surface 8j, and there is no need to increase the effective surface area by providing unevenness on the memory capacitor.

そのため、その後の微細ノ々ターン形成に支障をきたす
ようなプロセス的な問題が発生しないで電荷蓄積容量を
増加できる利点がある。1だ、キヤ、eシタ訪電体膜厚
を薄くすることなく電荷蓄積容量を増加できるので、訪
電体族を薄くした時に発生する耐圧の低下および電荷の
漏れなど物理的間融を伴うことなく電荷蓄積容量の増加
が可能となる。
Therefore, there is an advantage that the charge storage capacity can be increased without causing any process problems that would hinder the subsequent formation of fine notation turns. 1) Since the charge storage capacity can be increased without reducing the thickness of the current visiting body, physical melting such as a decrease in withstand voltage and charge leakage that occur when the current visiting body is made thinner can be increased. This makes it possible to increase the charge storage capacity without any problems.

また、接合容量の増加は、キャパシタ下部電極に接続さ
れる拡散層部分でのみ行われておジ、L&がって、トラ
ンジスタ延いては回路のスピードの低下あるいは充放*
を荷増による消費電流の増加をもたらすなどの問題を付
随することなく電荷蓄積容量を増加できる利点がある。
In addition, the increase in junction capacitance occurs only in the diffusion layer connected to the lower electrode of the capacitor.
This has the advantage that the charge storage capacity can be increased without causing problems such as an increase in current consumption due to an increase in load.

【図面の簡単な説明】[Brief explanation of the drawing]

M1図はこの発明のDRAMメモリセルの一実施例を示
す断面図、第2図は従来のDRAMメモリセルの断面図
である。 21・・・P型シリコン基板、23・・・ゲート酸化膜
、24・・・ゲート電極、25a、25b・・・N型拡
散層、28・・・キャパシタ下部電極、29・・・キャ
ノゼシタ訪電体膜、30・・・キャパシタ上部電極、3
1・・・高濃度不純物領域。 特許出願人 沖電気工業株式会社 本#ef4−5 aイ列のフターツク型メεソ仁ツム第
1図 <t9のスタック1′ノとり仁ル s  2  図
FIG. M1 is a sectional view showing an embodiment of the DRAM memory cell of the present invention, and FIG. 2 is a sectional view of a conventional DRAM memory cell. 21... P-type silicon substrate, 23... Gate oxide film, 24... Gate electrode, 25a, 25b... N-type diffusion layer, 28... Capacitor lower electrode, 29... Capacitor power visit Body membrane, 30... Capacitor upper electrode, 3
1...High concentration impurity region. Patent Applicant: Oki Electric Industry Co., Ltd. Book #ef4-5 A-row lid-type method Fig. 1 < t9 stack 1' notch hole s 2 Fig.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板にゲート酸化膜、ゲート電極および一
対の拡散層からなるトランジスタを形成するとともに、
該トランジスタの一方の拡散層に接続されるキャパシタ
下部電極、その上のキャパシタ誘電体膜、その上のキャ
パシタ上部電極からなるメモリキャパシタを前記基板上
に形成したスタック型の1トランジスタ、1キャパシタ
DRAMメモリセルにおいて、 キャパシタ下部電極と接続される一方の拡散層の領域下
でのみ半導体基板に、該基板の不純物濃度より高い高濃
度不純物領域を形成したことを特徴とするDRAMメモ
リセル。
(1) Forming a transistor consisting of a gate oxide film, a gate electrode, and a pair of diffusion layers on a semiconductor substrate, and
A stacked one-transistor, one-capacitor DRAM memory in which a memory capacitor consisting of a capacitor lower electrode connected to one diffusion layer of the transistor, a capacitor dielectric film thereon, and a capacitor upper electrode thereon is formed on the substrate. 1. A DRAM memory cell characterized in that a high concentration impurity region higher than the impurity concentration of the semiconductor substrate is formed in the semiconductor substrate only under the region of one diffusion layer connected to the lower electrode of the capacitor.
(2)高濃度不純物領域は、キャパシタ下部電極と接続
される一方の拡散層下のうち、特に該拡散層がキャパシ
タ下部電極と接続される領域下に限定して基板に形成し
たことを特徴とする特許請求の範囲第1項記載のDRA
Mメモリセル。
(2) The high concentration impurity region is formed on the substrate only under one of the diffusion layers connected to the capacitor lower electrode, particularly under the region where the diffusion layer is connected to the capacitor lower electrode. DRA according to claim 1
M memory cell.
JP62153436A 1987-06-22 1987-06-22 Dram memory cell Pending JPS63318151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62153436A JPS63318151A (en) 1987-06-22 1987-06-22 Dram memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62153436A JPS63318151A (en) 1987-06-22 1987-06-22 Dram memory cell

Publications (1)

Publication Number Publication Date
JPS63318151A true JPS63318151A (en) 1988-12-27

Family

ID=15562481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62153436A Pending JPS63318151A (en) 1987-06-22 1987-06-22 Dram memory cell

Country Status (1)

Country Link
JP (1) JPS63318151A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04278579A (en) * 1991-02-25 1992-10-05 Samsung Electron Co Ltd Semiconductor memory device using stack-shaped capacitor
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5659191A (en) * 1990-05-01 1997-08-19 Mitsubishi Denki Kabushiki Kaisha DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5489791A (en) * 1990-04-27 1996-02-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5672533A (en) * 1990-04-27 1997-09-30 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5659191A (en) * 1990-05-01 1997-08-19 Mitsubishi Denki Kabushiki Kaisha DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof
US5949110A (en) * 1990-05-01 1999-09-07 Mitsubishi Denki Kabushiki Kaisha DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof
JPH04278579A (en) * 1991-02-25 1992-10-05 Samsung Electron Co Ltd Semiconductor memory device using stack-shaped capacitor

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