JPS63318151A - Dram memory cell - Google Patents

Dram memory cell

Info

Publication number
JPS63318151A
JPS63318151A JP62153436A JP15343687A JPS63318151A JP S63318151 A JPS63318151 A JP S63318151A JP 62153436 A JP62153436 A JP 62153436A JP 15343687 A JP15343687 A JP 15343687A JP S63318151 A JPS63318151 A JP S63318151A
Authority
JP
Japan
Prior art keywords
capacitor
lower electrode
formed
capacitor lower
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62153436A
Inventor
Kenji Anzai
Ichiro Murai
Akito Nishitani
Original Assignee
Oki Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Ind Co Ltd filed Critical Oki Electric Ind Co Ltd
Priority to JP62153436A priority Critical patent/JPS63318151A/en
Publication of JPS63318151A publication Critical patent/JPS63318151A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10808Dynamic random access memory structures with one-transistor one-capacitor memory cells the storage electrode stacked over transistor

Abstract

PURPOSE:To increase the charge storage capacity by increasing the junction capacity only in the diffused layer part connected to a capacitor lower electrode. CONSTITUTION:A field oxide film 22 is formed in a non-active region on a P type silicon substrate 21 while a gate oxide film 23, a gate electrode 24 and a pair of N type diffused layers 25a, 25b are formed in an active region to constitute a transistor. A part of the N type diffused layer 25b is connected to a capacitor lower electrode 28 on an insulating film 26 through a selfcontact 27 as an opening made in overall surface of the insulating film 26 and the gate oxide film 23 on the substrate 21 and then a capacitor dielectric film 28 and a capacitor upper electrode 30 are arranged on the capacitor lower electrode 28 to constitute a memory capacitor. Furthermore, in the P type silicon substrate 21, an impurity region 31 is formed only below one N type diffused layer 25b connected to the capacitor lower electrode 28.
JP62153436A 1987-06-22 1987-06-22 Dram memory cell Pending JPS63318151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62153436A JPS63318151A (en) 1987-06-22 1987-06-22 Dram memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62153436A JPS63318151A (en) 1987-06-22 1987-06-22 Dram memory cell

Publications (1)

Publication Number Publication Date
JPS63318151A true JPS63318151A (en) 1988-12-27

Family

ID=15562481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62153436A Pending JPS63318151A (en) 1987-06-22 1987-06-22 Dram memory cell

Country Status (1)

Country Link
JP (1) JPS63318151A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04278579A (en) * 1991-02-25 1992-10-05 Samsung Electron Co Ltd Manufacture of dynamic memory cell using stacked capacitor
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5659191A (en) * 1990-05-01 1997-08-19 Mitsubishi Denki Kabushiki Kaisha DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5489791A (en) * 1990-04-27 1996-02-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5672533A (en) * 1990-04-27 1997-09-30 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5659191A (en) * 1990-05-01 1997-08-19 Mitsubishi Denki Kabushiki Kaisha DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof
US5949110A (en) * 1990-05-01 1999-09-07 Mitsubishi Denki Kabushiki Kaisha DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof
JPH04278579A (en) * 1991-02-25 1992-10-05 Samsung Electron Co Ltd Manufacture of dynamic memory cell using stacked capacitor

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