JPS63318151A - Dram memory cell - Google Patents

Abstract

PURPOSE:To increase the charge storage capacity by increasing the junction capacity only in the diffused layer part connected to a capacitor lower electrode. CONSTITUTION:A field oxide film 22 is formed in a non-active region on a P type silicon substrate 21 while a gate oxide film 23, a gate electrode 24 and a pair of N type diffused layers 25a, 25b are formed in an active region to constitute a transistor. A part of the N type diffused layer 25b is connected to a capacitor lower electrode 28 on an insulating film 26 through a selfcontact 27 as an opening made in overall surface of the insulating film 26 and the gate oxide film 23 on the substrate 21 and then a capacitor dielectric film 28 and a capacitor upper electrode 30 are arranged on the capacitor lower electrode 28 to constitute a memory capacitor. Furthermore, in the P type silicon substrate 21, an impurity region 31 is formed only below one N type diffused layer 25b connected to the capacitor lower electrode 28.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention is a one-transistor, one-canon type DR
AM (dynamic random access memory cell).

(Prior Art) A DRAM memory cell generally consists of one transistor and one capacitor, and stores information by accumulating charge in the capacitor. Conventionally, planar memory cells with a two-dimensional planar structure have been used as this type of memory cell, but in megbit-class DRAMs, stacked memory cells in which cells are stacked upward, or semiconductors are used. Memory cells are beginning to be used that increase the effective canopy area through three-dimensional structuring, such as trench-type memory cells in which a trench is dug in a substrate and a canopy is formed within the trench. The reason is that if the capacitance of the capacitor is small (i.e. less charge is stored in the capacitor), the circuit malfunctions (because the stored signal is small)
This can lead to problems such as increased susceptibility to nufting errors due to alpha rays.

FIG. 2 is a cross-sectional view of a conventional conventional stacked memory cell. In this figure, a 1-Fipu silicon substrate is shown, and a field oxide film 2 is formed in the non-active region on this P-type silicon substrate 1, while a gate oxide film 3 is formed in the active region. A gate electrode 4 and a pair of N-type diffusion layers 5a and 5b are formed to constitute a transistor. Then, a part of one N-type diffusion layer 5b constituting the transistor passes through the insulating film 6 on the entire surface of the substrate 1 and the opening 7 (hereinafter referred to as self-contact) in the gate oxide film 3. It is connected to the upper capacitor lower electrode 8 made of N-type polysilicon, and on this capacitor lower electrode 8, a capacitor dielectric film 9, and further a capacitor upper electrode 10 made of N-type polysilicon are disposed. Then, the memory is configured.

In this structure, a certain capacity can be obtained from the memory capacitor stacked above and the junction capacitance formed by the P-type silicon substrate 1 and the N-type diffusion layer 5b.

(Problems to be Solved by the Invention) However, the conventional stacked memory cell as described above has the following drawbacks. First, in the memory capacitors stacked upward, in order to increase the charge storage capacity, unevenness is provided to increase the effective surface area.
Alternatively, a structure such as making the capacitor dielectric film 9 thinner can be considered, but if the dielectric film 9 is made thinner, the withstand voltage will drop and the leakage of charge will occur. Subsequent fine pattern formation becomes difficult.

As described above, in a memory capacitor, it is difficult to obtain a charge storage capacity of a certain value or more by modifying physical or process constraints. Next, regarding the junction capacity (2) between the P-type silicon substrate 1 and the N-type diffusion layer 5b, basically, if the concentration of the P-type silicon substrate 1, which corresponds to the low concentration side, is increased, the expansion of the depletion layer can be suppressed. Junction capacitance increases, but P-type silicon substrate 1
Since the junction capacitance other than the N-type diffusion layer 5b connected to the lower electrode of the capacitor also increases at the same time, this results in a reduction in the speed of the transistor and the circuit, or an increase in current consumption due to an increase in charging and discharging charges.

As described above, in conventional stacked memory cells, it has not been possible to obtain a charge storage capacity of a certain value or more due to semiconductor process, physical constraints, or circuit performance constraints.

SUMMARY OF THE INVENTION An object of the present invention is to provide a stacked DRAM memory cell whose charge storage capacity can be increased without the above-mentioned semiconductor process or physical limitations and circuit performance problems.

(Means for Solving the Problems) The present invention provides a stacked one-transistor/one-canon DRAM memory cell in which a feeding conductor is formed under a diffusion layer region of one of the transistors connected to a capacitor lower electrode. A highly concentrated impurity region is formed in a substrate, which is longer than the impurities in the substrate.

(Function) According to the above structure, due to the high concentration impurity region,
Junction capacitance increases only in the diffusion layer portion connected to the capacitor lower electrode, and charge storage capacity increases.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention. In this figure, reference numeral 21 denotes a P-type silicon substrate, on which a field oxide film 22 is formed in the non-active region, while a gate oxide film 23 is formed in the active region. A gate electrode 24 and a pair of N-type diffusion layers 25a and 25b are formed to constitute a transistor. Then, a part of one N-type diffusion layer 25b constituting the transistor forms a self-contact 27'&A, which is an opening formed in the insulating film 26 and gate oxide film 23 on the entire surface of the substrate 21, and forms the insulating film 27'&A. Canopy lower part t&28 made of N-type polysilicon on film 26
A capacitor dielectric film 29 and a capacitor upper electrode 30 made of N-type polysilicon are arranged on the capacitor lower electrode 28 to form a memory canister. Further, in the P-type silicon substrate 21, one of the pair of diffusion layers 25a and 25b of the transistor 7 is connected to the capacitor lower electrode 28.
Limited to the area below the type diffusion layer 25b, and in this example,
The diffusion layer 25b under one of the N-type diffusion layers 25b
The impurity concentration (1×1
014~5x1016cIn-3) with a higher impurity concentration (Ix1017~lx1018cm-3),
An impurity region 31 having the same polarity (P type) as the substrate 21 is formed. Therefore, according to this memory cell, the junction capacitance increases only in the portion of the diffusion layer 25b connected to the capacitor lower electrode 28, and the charge storage capacity increases.

Note that in the above embodiment, ca) J? Shishita part electrode 28
Although the high concentration impurity region 31 is formed under the N type diffusion layer 25b only in the portion connected to the N type diffusion layer 25b, the high concentration impurity region 31 may be formed entirely under the N type diffusion layer 25b.

(Effects of the Invention) As described above, according to the DRAM memory cell of the present invention, the junction capacitance is increased only in the diffusion layer portion connected to the capacitor lower electrode, and the charge storage capacity is increased. , it is possible to increase the charge storage capacity i without changing the memory capacitor ξ storage surface 8j, and there is no need to increase the effective surface area by providing unevenness on the memory capacitor.

Therefore, there is an advantage that the charge storage capacity can be increased without causing any process problems that would hinder the subsequent formation of fine notation turns. 1) Since the charge storage capacity can be increased without reducing the thickness of the current visiting body, physical melting such as a decrease in withstand voltage and charge leakage that occur when the current visiting body is made thinner can be increased. This makes it possible to increase the charge storage capacity without any problems.

In addition, the increase in junction capacitance occurs only in the diffusion layer connected to the lower electrode of the capacitor.
This has the advantage that the charge storage capacity can be increased without causing problems such as an increase in current consumption due to an increase in load.

[Brief explanation of the drawing]

FIG. M1 is a sectional view showing an embodiment of the DRAM memory cell of the present invention, and FIG. 2 is a sectional view of a conventional DRAM memory cell. 21... P-type silicon substrate, 23... Gate oxide film, 24... Gate electrode, 25a, 25b... N-type diffusion layer, 28... Capacitor lower electrode, 29... Capacitor power visit Body membrane, 30... Capacitor upper electrode, 3
1...High concentration impurity region. Patent Applicant: Oki Electric Industry Co., Ltd. Book #ef4-5 A-row lid-type method Fig. 1 < t9 stack 1' notch hole s 2 Fig.

Claims (2)

[Claims] (1) Forming a transistor consisting of a gate oxide film, a gate electrode, and a pair of diffusion layers on a semiconductor substrate, and
A stacked one-transistor, one-capacitor DRAM memory in which a memory capacitor consisting of a capacitor lower electrode connected to one diffusion layer of the transistor, a capacitor dielectric film thereon, and a capacitor upper electrode thereon is formed on the substrate. 1. A DRAM memory cell characterized in that a high concentration impurity region higher than the impurity concentration of the semiconductor substrate is formed in the semiconductor substrate only under the region of one diffusion layer connected to the lower electrode of the capacitor. (2) The high concentration impurity region is formed on the substrate only under one of the diffusion layers connected to the capacitor lower electrode, particularly under the region where the diffusion layer is connected to the capacitor lower electrode. DRA according to claim 1
M memory cell.