JPS60128657A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce distance between groove-shaped capacitors and to improve device capability to withstand errors in software by a method wherein a groove- shaped capacitor is provided with a region diffused with an impurity as the second capacitor electrode and an opposed electrode as their first capacitor electrode. CONSTITUTION:A part of each of activation regions 24a, 24b and both ends of an activation region 24c are respectively provided with groove-shaped capacitors 25a-25d. The groove-shaped capacitors 25a, 25b are positioned adjacent to each other. The groove-shaped capacitor 25a is provided with a groove 26a, typically 3mum deep, extending from the surface of a p type Si layer 22 to the inside of an Si substrate 21. In the p type Si layer 22 and Si substrate 21 inside the groove 26a, an n type diffused region 27a doped to be of the second conductivity type is formed. In a groove-shaped capacitor 25a designed as such, an electrode 29 serves as the first capacitor electrode while the n type diffused region 27a serves as the second capacitor electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the structure of a trench type capacitor as a memory portion is improved.

[Technical background of the invention and its problems]

Semiconductor storage devices, including dynamic memory,
Its storage capacity increased to 4 in about 3 years due to advances in microfabrication technology.
It is growing twice as fast. The memory cell area continues to be rapidly reduced as storage capacity increases, but the storage capacitor value of the memory cell is being adjusted to prevent soft errors and to ensure the S/N ratio for sensing by the sense amplifier. Therefore, it is necessary to maintain a large value of several tens of fF.

Incidentally, conventionally, in order to increase the capacitor value per unit area, the insulating film of the MOS structure constituting the storage capacitor has been made thinner, or the insulating film material has been changed from silicon oxide film to silicon nitride film. However, these Q-1-1p capacitors utilize the surface of the semiconductor substrate to form a MOS IM structure, so as the cell area becomes smaller, there is a natural limit to the ability to obtain a human capacitor value. there were.

For this reason, recently H. Sunami et al.
”A Corrugated Capacitor C
e1l (CCC) for fvl egabit
Dynamic Ivl OSMeIortea”,
l international E Electric [
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)igcsj, KM performance number 26.9, l1l), 8
In 2006-808Dcc, 1982, he announced a MOS memory having a trench type capacitor with the structure shown in FIG. That is,
Reference numeral 1 in FIG. 1 is, for example, a p-type silicon substrate, and a deep groove 2 (for example, about 3 to 5 μm) is provided extending from the surface of the substrate 1 to the inside. A capacitor electrode 3 made of a first layer of polycrystalline silicon is provided from the inside of the trench 2 to the periphery of the opening with a capacitor insulating film 4 interposed therebetween.

This capacitor insulating film 4 is made of Si 02 /Si 3 N
It consists of a three-layer film of 4/St 02. Such a substrate 1,
The groove portion 2, the capacitor insulating film 4, and the capacitor electrode 3 constitute a groove type capacitor 5-. Further, n+ type source and drain regions 6.7 electrically isolated from each other are provided on the surface of the silicon substrate 1 adjacent to the trench capacitor 5-. On a portion of the substrate including at least between these source and drain regions 6 and 7,
A gate electrode 9 made of a second layer of polycrystalline silicon is provided with a gate oxide film 8 interposed therebetween. These source and drain regions 6.7, gate oxide film 8, and gate electrode 9 constitute transfer 1 to transistor 10. Furthermore,
The source region 6 is in contact with the insulating film 4 of the trench capacitor 5-, and the drain region 7 is connected to a bit line (not shown). In addition, 9- in the figure is the adjacent y
This is the gate electrode of a memory cell.

However, the ~10S memory shown in FIG. 1 mentioned above is partially described in the literature. The disadvantage is that the distance between the trench capacitors between memory cells cannot be shortened, and high-density memory cells cannot be realized. That is, in general, the junction capacitance of the drain of transfer transistor 1 to transistor constituting a memory cell is:
Reductions are required to reduce bit line capacitance. For this reason, it is necessary to lower the concentration of the p-type silicon substrate, but this causes a depletion layer to extend in the substrate near the MOS IM capacitor, making it easier for the pan-de-through phenomenon to occur. Such a pan-de-through phenomenon can generally be prevented by implanting impurity ions from near the surface of the silicon substrate. However, in a trench capacitor 5 made by forming a deep trench 2 in a silicon substrate 1 as shown in FIG.
Since it is difficult to implant impurity ions deep into the silicon substrate 1, a punch-through phenomenon occurs near the bottoms of adjacent full cavities, and this has a serious drawback in that it cannot be prevented. . Therefore, in the conventional structure, it is necessary to leave a long distance between the trench capacitors between memory cells, making it extremely difficult to realize a high density memory cell.

In addition, in the structure shown in Fig. 1, the depletion layer is extended by the trench capacitor 5- deep in the silicon substrate 1, and the charge generated by the large sword of α rays is easily collected by the funneling phenomenon, so it is difficult to prevent soft errors. It had the disadvantage of being weak.

[Purpose of the invention]

The present invention aims to provide a semiconductor memory device that is equipped with trench capacitors having a large capacitor value per unit area, can significantly shorten the distance between the trench capacitors, and has excellent soft error resistance. .

(Summary of the Invention) The present invention provides a semiconductor substrate of a first conductivity type having a higher concentration than the semiconductor layer formed on the surface thereof, and a semiconductor substrate having a semiconductor layer of a first conductivity type formed on the surface of the semiconductor substrate. a second conductivity type impurity diffusion region provided over the semiconductor layer and the semiconductor substrate on the inner surface of the trench, and a capacitor insulating film extending from inside the trench to at least the periphery of the opening. and an electrode provided through the capacitor, the electrode is used as a first capacitor electrode, and the impurity diffusion region is used as a second capacitor electrode.
The present invention is characterized in that it includes a groove-type capacitor having a structure as a capacitor electrode. In such a structure, the high concentration semiconductor substrate of the first conductivity type suppresses the extension of the depletion layer in the deep part of the trench capacitor and prevents the punch-through phenomenon between adjacent trench capacitors, thereby creating a high-density memory hill. and improve soft error resistance due to the similar effect of the highly concentrated semiconductor substrate of the first conductivity type.
Further, it is possible to obtain a semiconductor memory device in which the capacitor value per unit area is increased by J: in the junction capacitance between the semiconductor substrate and semiconductor layer of the first conductivity type and the impurity diffusion region of the second conductivity type.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a plan view showing a portion of the dynamic MOS memory, and FIG. 3 is a sectional view taken along line ll-H in FIG. Reference numeral 21 in the figure indicates a 2 μm thick p-type silicon layer 22 containing, for example, 2×10”70 m3 of acceptor impurity (boron, etc.) on the surface, which is formed by, for example, an epitaxial growth method and contains, for example, 5×101?/cm3 of boron. This is a highly doped p+ type silicon substrate.This silicon layer 22 is provided with a field oxide film 23, and the silicon layer 22 has a plurality of island-shaped active regions (memory Cell regions) 248 to 24C are formed.Trench capacitors 2 are formed at both ends of a portion of these active regions 24a and 24b and an active region 24c, respectively.
5a to 25d are provided, and the groove type capacitor 2
5a and 25b are arranged adjacent to each other. As shown in FIG. 3, the trench capacitor 25a includes a trench 26a having a depth of, for example, 3 μm, extending from the surface of the p-type silicon layer 22 into the silicon substrate 21. this)i
Silicon layer 22 and silicon substrate 2 on the inner surface of the bottom portion 26a
1, an n-type diffusion region 27a is formed as a second conductivity type impurity diffusion region. This r) type diffusion region 27
The depth of a is 0.2 μm, and the degree of m is, for example, 2×10 70
It is from m3. An extending portion 28a is formed on the side surface (surface portion of the p-type silicon layer 22) of the r) type diffusion region 1U27a opposite to the trench capacitor 25b. The electrodes 1 and 2 made of first layer polycrystalline silicon are applied from inside the groove 2Ga to at least around the opening of the groove 26a.
℃) is used as an insulating film for a capacitor.
It is provided through a silicon oxide film 30a.

In such a trench capacitor 25a, the electrode 29
is the first capacitor electrode, and the type 1 diffusion region 27a functions as the second capacitor. - 10,000, the trench type capacitor 25
b is composed of a groove portion 261), an n-type diffusion region 1i127b, two electrodes, a silicon oxide film 30b, etc. Although the trench type capacitor 25C125d is not shown in detail, it has a similar structure to the trench capacitors 25a and 25b.

Here, Fig. 4(a) shows a method for manufacturing a trench type capacitor.
, (b) will be briefly explained. First, a p-type silicon layer 22 is formed on a p+-type silicon substrate 21 by epitaxial growth, and a field oxide film 23 is selectively formed on the silicon layer 22, and island-shaped active regions 24a, 24b (24c is (not shown), the surface of the active region I or 24a, 24b is oxidized to a thickness of about 1000 ml. Form J31. Next, Fu 11-
After applying a resist and forming a resist pattern (not shown) on the portion of the oxide film 31 where the groove is to be formed by photolithography, the oxide film 31 is etched by reactive ion etching using the resist pattern as a mask. Then, the area from the surface of the p-type silicon layer 22 to the inside of the d-type silicon substrate 21 is selectively etched to form grooves 26a and 26b having a depth of, for example, 3 μm (as shown in FIG. 4(a)). After this, the resist pattern was peeled off.

Next, the oxide film 31 corresponding to a part of the source region of the transfer transistor is selectively removed by photolithography, and then a phosphorus-doped silicon oxide film (or an arsenic-doped silicon oxide film, a multilayer film in which phosphorus is also doped with arsenic) is formed on the entire surface. After depositing a crystalline silicon film 32 by the CVD method, phosphorus is thermally diffused from the p-type silicon layer 21 to the p-type silicon substrate 21 using the phosphorus-doped silicon oxide film 32 as a diffusion source to form a mold diffusion regions 27a, 27b and extension portion 28a,
28b (as shown in FIG. 4(b)).

After this, although not shown, the phosphorus-doped silicon oxide film is removed, the oxide film is also removed, and thermal oxidation treatment is performed again to form a silicon oxide film on the exposed silicon layer surface including the inner surface of the groove. A first layer polycrystalline silicon film is deposited on the entire surface, and this is buttered to form an electrode from within the groove to at least around the opening thereof, and the silicon oxide film is selectively etched using this electrode as a mask. Then, a silicon oxide film for a capacitor is formed.

Also, transfer 1 transistors 33a to 33d are formed in each active region 24a and 24c adjacent to the trench capacitors 25a to 25d. n+ type source and drain regions 34a and 35a that are electrically isolated from each other on the surfaces of adjacent active regions 24a, and a portion of the active region 24a that includes at least the space between these source and drain regions 34a and 35a. 1 to a gate electrode 37a installed via an oxide film 36a.

The 11+ type source region 34. a is connected to an extension 28a of an n-type diffusion region 27a constituting the crystal capacitor 25a. On the other hand, the transfer 1 to transistor 33b
is composed of n+ type source and drain regions 34b and 35b, a gate oxide film 36b, and a gate electrode 37b, and the source region 34b is a 1] type diffusion region 27b forming the trench type capacitor 25b. Extending portion 28b of
is connected to each of the transfer transistors 33a, 3
Similar to 3b, the source, drain regions, and Ga-1/oxide film (
(none of which are shown) and gate electrodes tM37c and 37d. Note that the transfer 1 to transistor 33
a', 33b (7) The gate electrodes 37a, 37b cross over the electrodes 29 of the trench capacitors 25c, 25d via an oxide film (not shown), and the gate electrodes 37a, 37b cross the electrodes 29 of the trench type capacitors 25c, 25d via an oxide film (not shown), and +? A 37c
, 37d cross the oxide film 38a138b over the electrode 29 of the trench type capacitor 2.5D125. Furthermore, each of the trench type capacitors 251 to 25
The silicon layer 22 including the transfer transistors 33E+ to 33d and the transfer transistors 33E+ to 33d is covered with an interlayer insulating film 39, and on the interlayer insulating film 39, bit lines 4o and 4o- made of A1, for example, are connected to each of the transfer transistors 33E+ to 33d. Goo 1'-electrode 37a~
37d are provided in a direction perpendicular to each other. One bit line 4o contacts *-/L, 41 to the drain regions 35a and 35b of the transfer 1 to transistors 33a and 33b.
a and 41b, respectively. The other bit line 40' is connected to the transfer transistors 33c, 33
d is connected to a common drain region (not shown) through a contact hole 41c. These bit lines 4
A protective insulating film 42 is formed on the interlayer insulating film 39 containing 0.4O-.
is covered.

According to the semiconductor memory device of the present invention, approximately 5×10′7/cm A high degree p1 with an impurity concentration of
Since the p-type silicon substrate 2°1 is present, the extension of the depletion layer in the deep portions of the trench-type capacitors 25a and 25b can be moderately suppressed by the presence of the p-type silicon substrate 21. In fact, when the storage node has a potential difference of 5V with respect to the p-type silicon substrate 21 and the p-type silicon layer 22, the width of the depletion layer extending from the corresponding one of the n-type diffusion regions 27a and 27b is about 0.13 μm. Ta. Further, the extension of the depletion layer from the n-type diffusion regions 27a and 27b in the p-type silicon layer 22 can be made approximately 0.2 μm even with a potential difference of 5V by implanting and diffusing acceptor impurity ions into the field oxide film 23. was completed. As a result, the trench capacitor 25a,
The distance (A) between the groove type capacitors 25b and 25b can be kept close to 0.6 μm (even with I-type, the pan-de-through phenomenon between the two can be prevented. In addition, in the structure of the groove type capacitor i shown in FIG. A pan death-through phenomenon has already occurred at 2 μm.This is an improvement of more than three times in terms of distance.Furthermore, in the present invention, the junction capacitance of the line 1 to the line does not increase at all.Therefore, the pan death-through phenomenon between the groove-type chitopacitas can be prevented. As a result, high-density memory cells can be realized.

In addition, since the p+ type silicon substrate 21 knee 1 in the deep part where the groove capacitor (for example 25a) is formed is highly concentrated, the lifetime of carriers at that part is shortened, and the carriers generated by the incidence of α rays are 17 rear is the n-type expansion 11 of the groove capacitor 25a! ! It is possible to prevent the particles from gathering in the region 27a due to the funneling phenomenon, and it is possible to realize a semiconductor memory device with excellent soft error resistance.

Furthermore, in the present invention, the pn junction capacitance between the p + type silicon substrate 21 and the p type silicon layer 22 and the n type diffusion region 27a is reduced by the n type diffusion region 27a with the silicon oxide film 30a interposed.
Since the capacitance is superimposed on the capacitance between the capacitance and the electrode 29, it is possible to realize the trench type capacitor 25a with a high capacitance value per unit area, and as a result, the density of the memory cell can be increased. fact,
It was found that the pn junction capacitance reached approximately 30% of the electrostatic capacitance value.

Note that in the above embodiment, a silicon oxide film is used as the capacitor insulating film, but the present invention is not limited to this. for example,
A composite film in which a silicon nitride film is sandwiched between silicon oxide films, a silicon nitride film, or a two-layer film of silicon oxide and tantalum oxide may be used.

In the above embodiments, a p + type silicon substrate was used as the semiconductor substrate and an n type silicon layer was used as the semiconductor layer, but an n + type silicon substrate or an n type silicon layer may be used. In this case, the second conductivity type impurity diffusion region is p-type, and the transfer transistor is a p-channel MOS transistor.

Although the above embodiment has been described using a dynamic N=I OS memory as an example, it can be similarly applied to a static MOS memory. In this case, for example, the trench type capacitor described above may be provided at the bistable node of a flip-flop type cell.

〔Effect of the invention〕

As described in detail above, according to the present invention, a groove type capacitor having a large capacitor value per unit area is provided, and the distance between the groove type capacitors is significantly shortened without causing a bump-through phenomenon. It is possible to increase the density of rerels, improve the resistance to errors, and provide a high-density, highly reliable semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional dynamic MOS memory, FIG. 2 is a plan view of a dynamic MOS memory showing an embodiment of the present invention, and FIG. 4(a) and 4('b) are cross-sectional views taken along the line showing the steps for forming the trench type capacitor of this embodiment. 21...p+ type silicon substrate, 22...n type silicon layer, 23...field oxide film, 24a to 24c.
...Active region (memory cell), 25a-25d...Trench capacitor, 26a, 26b-...Groove portion, 27a12
7b...11 type diffusion region (second conductivity type impurity diffusion region), 28a, 28b...extension portion, 29...electrode made of first layer polycrystalline silicon, 30a, 30b...oxidation Silicon film (insulating film for capacitor), 32...Phosphorus-doped silicon oxide film, 33a-33d...Transfer transistor, 34'a, 34b...n+ type source region, 35a, 35 b/n'' type 'I' L/ Inf
iJ"l IJI, 37a-37d...Goo 1-electrode made of second layer polycrystalline silicon, 40.40'...Bin 1-line. Applicant's representative Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) a semiconductor substrate of a first conductivity type on whose surface a semiconductor layer of a first conductivity type is formed and whose concentration is higher than that of the semiconductor layer; and a groove portion extending from the surface of the semiconductor layer into the semiconductor substrate; A second conductivity type impurity diffusion region provided over the semiconductor layer and the semiconductor substrate on the inner surface of the trench, and an electrode provided from inside the trench to at least the periphery of the opening via a capacitor insulating film. 1. A semiconductor memory device comprising a trench type capacitor having a structure in which the electrode is a first capacitor electrode and the impurity diffusion region is a second capacitor electrode. (2) The semiconductor memory device according to claim 1, wherein the second conductivity type impurity diffusion region of the trench capacitor has a higher V# degree than the first conductivity type semiconductor substrate. (3) Source and drain regions of a second conductivity type provided electrically isolated from each other on the surface of a semiconductor layer of a first conductivity type, and a gate on a portion of the semiconductor layer including at least between and between these source and train regions. A transfer 1-transistor comprising a gate electrode provided through an insulating film, one of the source and drain regions being connected to the second conductivity type impurity diffusion region of the trench capacitor, and the other being connected to the bit line. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected.