JPS6240868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the structure of a groove-type capacitor as a memory portion is improved. [Technical background of the invention and its problems] The storage capacity of semiconductor memory devices such as dynamic memories is increasing at a rate of four times every three years due to advances in microfabrication technology. The memory cell area continues to be rapidly reduced as storage capacity increases, but the storage capacitor value of the memory cell is being adjusted to prevent soft errors and to ensure the S/N ratio for sense amplifier sensing. dozens of
It is necessary to maintain a large value of fF. By the way, conventionally, in order to increase the capacitor value per unit area, the insulating film of the MOS structure constituting the storage capacitor has been made thinner, or the insulating film material has been changed from silicon oxide film to silicon nitride film. However, since these storage capacitors form a MOS structure using the surface of a semiconductor substrate, there is a natural limit to obtaining a large capacitor value as the cell area becomes smaller. For this reason, recently H. Sunami et al.
“A Corrugated Capacitor Cell (CCC) for
Megabit Dynamic MOS Memories”,
International Electric Device Meeting
Technical Digest, lecture number 26.9, pp, 806~
On 808 Dec, 1982, we announced a MOS memory with a groove-type capacitor having the structure shown in Figure 1. That is, 1 in FIG. 1 is, for example, a p-type silicon substrate, and a deep (for example, 3
~5 μm) groove portion 2 is provided. A capacitor electrode 3 made of a first layer of polycrystalline silicon is provided from the inside of the trench 2 to the periphery of the opening with a capacitor insulating film 4 interposed therebetween. This capacitor insulating film 4 consists of a three-layer film of SiO ₂ /Si ₃ N ₄ /SiO ₂ .
The substrate 1, the groove portion 2, the capacitor insulating film 4, and the capacitor electrode 3 constitute a groove-type capacitor 5 . Further, on the surface of the silicon substrate 1 adjacent to the trench capacitor 5 , n ⁺ type source and drain regions 6, which are electrically isolated from each other, are provided.
7 is provided. On a portion of the substrate 1 including at least between these source and drain regions 6 and 7,
A gate electrode 9 made of a second layer of polycrystalline silicon is provided with a gate oxide film 8 interposed therebetween. The source and drain regions 6 and 7, the gate oxide film 8, and the gate electrode 9 constitute a transfer transistor 10 . Furthermore, the source region 6 is in contact with the insulating film 4 of the trench capacitor 5 , and the drain region 7 is connected to a bit line (not shown). Note that 9' in the figure is the gate electrode of an adjacent memory cell. However, as described in some literature, the MOS memory shown in FIG.
The disadvantage was that the distance between the trench capacitors between memory cells could not be shortened, making it impossible to realize high-density memory cells. That is, it is generally required that the junction capacitance of the drain of a transfer transistor constituting a memory cell be reduced in order to reduce the bit line capacitance. For this reason, it is necessary to lower the concentration of the p-type silicon substrate, but this causes a depletion layer to extend in the substrate near the capacitor of the MOS structure, making it easier for punch-through phenomenon to occur. Such punch-through phenomenon can generally be prevented by implanting impurity ions from near the surface of the silicon substrate. However, in the trench capacitor 5 made by forming a deep trench 2 in a silicon substrate 1 as shown in FIG. 1, it is difficult to implant impurity ions deep into the silicon substrate 1. A serious drawback was that a punch-through phenomenon occurred near the bottom of the groove-type capacitor, and this phenomenon could not be prevented. Therefore, in the conventional structure, it was necessary to leave a long distance between the trench capacitors between memory cells, making it extremely difficult to realize a high density memory cell. In addition, in the structure shown in FIG. 1, the depletion layer is extended by the trench capacitor 5 deep in the silicon substrate 1, and α
It has the disadvantage of being vulnerable to soft errors because the charge generated by the incidence of the line is likely to be collected by the funneling phenomenon. [Objective of the Invention] It is an object of the present invention to provide a semiconductor memory device that is equipped with groove-type capacitors having a large capacitance value per unit area, can significantly shorten the distance between the groove-type capacitors, and has excellent soft error resistance. That is. [Summary of the Invention] The present invention provides a semiconductor substrate of a first conductivity type having a higher concentration than the semiconductor layer formed on the surface thereof, and a semiconductor substrate having a semiconductor layer of a first conductivity type formed on the surface of the semiconductor substrate. a second groove provided over the semiconductor layer and the semiconductor substrate on the inner surface of the groove;
It consists of a conductive type impurity diffusion region and an electrode provided from inside the trench to at least around the opening via a capacitor insulating film, the electrode being a first capacitor electrode, and the impurity diffusion region being a first capacitor electrode. This device is characterized by having a groove-type capacitor having a structure of two capacitor electrodes. In such a structure, a semiconductor substrate with a high concentration of the first conductivity type suppresses the extension of the depletion layer in the deep part of the trench capacitor and prevents the punch-through phenomenon between adjacent trench capacitors, resulting in a high-density memory. cell, and the soft error resistance is improved by the same effect of the high-concentration semiconductor substrate of the first conductivity type, and furthermore, the semiconductor substrate and semiconductor layer of the first conductivity type and the impurity diffusion region of the second conductivity type are It is possible to obtain a semiconductor memory device with an increased capacitor value per unit area due to the junction capacitance between the two. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3. FIG. 2 is a plan view showing a part of the dynamic MOS memory, and FIG. 3 is a sectional view taken along the line - in FIG. 21 in the figure is, for example, 2× on the surface.
A 2 μm thick p-type silicon layer 22 containing 10 ¹⁵ /cm ³ of acceptor impurity (such as boron) is formed by, for example, an epitaxial growth method.
It is a highly concentrated p ⁺ type silicon substrate containing 10 ¹⁷ /cm ³ of boron. A field oxide film 23 is provided on this silicon layer 22, and a field oxide film 23 is provided on this silicon layer 22.
A plurality of island-shaped active regions (memory cell regions) 24a to 24 are separated by the field oxide film 23.
c is formed. These active regions 24a, 2
Groove capacitors 25a to 25d are provided in a part of the active region 4b and at both ends of the active region 24c, respectively, and the groove capacitors 25a and 25b are arranged adjacent to each other. Groove capacitor 25a
As shown in FIG. 3, a groove 26a having a depth of, for example, 3 μm is provided extending from the surface of the p-type silicon layer 22 into the silicon substrate 21. An n-type diffusion region 27a serving as a second conductivity type impurity diffusion region is formed in the silicon layer 22 and the silicon substrate 21 on the inner surface of the groove portion 26a. This n-type diffusion region 27a has a depth of 0.2 μm and a concentration of, for example, 2×10 ¹⁸ /cm ³ . An extending portion 28a is formed on the side surface of the n-type diffusion region 27a opposite to the groove capacitor 25b (the surface portion of the p-type silicon layer 22). The groove portion 26a
An electrode 29 made of first layer polycrystalline silicon is provided from the inside to at least around the opening of the groove 26a via a silicon oxide film 30a having a thickness of 200 Å, for example, as a capacitor insulating film. In such a groove-type capacitor 25a , the electrode 2
9 functions as a first capacitor electrode, and the n-type diffusion region 27a functions as a second capacitor electrode. Note that the electrode 29 is connected to each groove-type capacitor 25a to
25d serves as a common electrode. On the other hand, the groove-type capacitor 25b has a groove portion 26b, an n-type diffusion region 2
7b, an electrode 29, and a silicon oxide film 30b. Further, the groove type capacitor 25
Although not shown in detail, capacitors 25c and 25d have the same structure as the groove capacitors 25a and 25b . Here, we will discuss the fourth method for manufacturing groove-type capacitors.
This will be briefly explained with reference to Figures a and b. First, p ⁺
A p-type silicon layer 22 is formed on a silicon substrate 21 by epitaxial growth, and a field oxide film 23 is selectively formed on the silicon layer 22, and island-shaped active regions 24a, 24b (2
4c is not shown), the active region 24 is formed.
An oxide film 31 with a thickness of about 1000 Å is formed on the surfaces of portions a and 24b. Next, apply photoresist,
After forming a resist pattern (not shown) on the portion of the oxide film 31 where the groove is to be formed by photolithography, the oxide film 31 is etched by reactive ion etching using the resist pattern as a mask, and then p-type silicon is etched. Grooves 26a and 26b having a depth of, for example, 3 .mu.m are formed by selectively etching from the surface of the layer 22 into the p.sup. ⁺ type silicon substrate 21 (as shown in FIG. 4a). After this, the resist pattern was peeled off. Next, the oxide film 31 corresponding to a part of the source region of the transfer transistor is selectively removed by photolithography, and then a phosphorus-doped silicon oxide film (or an arsenic-doped silicon oxide film, a multilayer film doped with phosphorus or arsenic) is formed on the entire surface. CVD of crystalline silicon film) 32
After deposition by a method, phosphorus is deposited on the p-type silicon layer 21 using the phosphorus-doped silicon oxide film 32 as a diffusion source.
Thermal diffusion is performed from the to the p-type silicon substrate 21 to form the n-type diffusion regions 27a, 27b and the extension portion 28, respectively.
a, 28b (as shown in FIG. 4b). After this, although not shown, the phosphorus-doped silicon oxide film is removed, the oxide film is also removed, and a thermal oxidation treatment is performed again to form a silicon oxide film on the exposed silicon layer surface including the inner surface of the groove, and then the entire surface is covered. A first layer polycrystalline silicon film is deposited and patterned to form an electrode from inside the trench to at least around the opening, and using this electrode as a mask, the silicon oxide film is selectively etched to form a capacitor. Form a silicon oxide film. Further, transfer transistors 33a to 33d are formed in each active region 24a to 24c adjacent to each of the trench capacitors 25a to 25d. The transfer transistor 33a is connected to the trench capacitor 25.
n ⁺ type source and drain regions 34a and 35a provided electrically isolated from each other on the surface of the active region 24a adjacent to a, and a portion of the active region 24a that includes at least the space between these source and drain regions 34a and 35a. and a gate electrode 37a provided through a gate oxide film 36a. The n ⁺ -type source region 34a is connected to the extension 28a of the n-type diffusion region 27a constituting the trench capacitor 25a . On the other hand, the transfer transistor 33b is composed of an n ⁺ type source, drain regions 34b, 35b, a gate oxide film 36b, and a gate electrode 37b, and the source region 34b is an n-type which constitutes the trench capacitor 25b . It is connected to the extension part 28b of the diffusion region 27b. Further, the transfer transistors 33c ,
33d is each transfer transistor 33a , 33
Similar to b, source, drain regions, gate oxide films (none of which are shown), and gate electrodes 37c, 3
It consists of 7d. Note that the gate electrodes 37a , 37 of the transfer transistors 33a, 33b
b is the electrode 2 of the groove capacitors 25c and 25d ;
The gate electrodes 37c and 37d of the transfer transistors 33c and 33d cross over the trench capacitors 25a and 9 through an oxide film (not shown).
The electrode 25b is crossed over the electrode 29 via the oxide films 38a and 38b. Furthermore, each of the grooved capacitors
25a to 25d and each of the transfer transistors 33
An interlayer insulating film 39 is coated on the silicon layer 22 including a to 33d , and the interlayer insulating film 39
Bit lines 40 and 40' made of Al, for example, are provided above in a direction perpendicular to each of the gate electrodes 37a to 37d. One bit line 40 has contact holes 41a, 41 in the drain regions 35a , 35b of the transfer transistors 33a, 33b.
They are connected to each other via b. The other bit line 40' is connected to the transfer transistors 33c and 33d.
are connected to a common drain region (not shown) through a contact hole 41c. A protective insulating film 42 is coated on the interlayer insulating film 39 including these bit lines 40, 40'. According to the semiconductor memory device of the present invention,
N-type diffusion regions 27a, 2 forming respective storage nodes of groove-type capacitors (for example, 25a , 25b )
Since there is a highly concentrated p ⁺ type silicon substrate 21 with an impurity concentration of about 5×10 ¹⁷ /cm ³ in the deep part of the trench capacitors 25a and 25b , the extension of the depletion layer in the deep part of the trench capacitors 25a and 25b is as follows. p-type silicon substrate 21
can be significantly suppressed by the presence of In fact, when the potential of the storage node was 5 V potential difference with respect to the p-type silicon substrate 21 and the p-type silicon layer 22, the width of the depletion layer extending from the corresponding one of the n-type diffusion regions 27a and 27b was about 0.13 μm. . Furthermore, the extension of the depletion layer from the n-type diffusion regions 27a and 27b in the p-type silicon layer 22 is achieved by implanting and diffusing acceptor impurity ions into the field oxide film 23.
Even with a potential difference of 5V, it was possible to achieve a voltage of about 0.2 μm.
As a result, even if the distance (A) between the grooved capacitors 25a and 25b is made as close as 0.6 μm, punch-through phenomenon between them can be prevented. In the structure of the grooved capacitor 5 shown in FIG. 1, the punch-through phenomenon already occurred when the distance between the grooved capacitors was about 2 μm.
This is an improvement of more than three times in terms of distance. Moreover, in the present invention, the junction capacitance of the bit line does not increase at all. Therefore, by preventing the punch-through phenomenon between the trench capacitors, high-density memory cells can be realized. In addition, since the p ⁺ type silicon substrate 21 in the deep part where the groove capacitor (for example 25a ) is formed has a high concentration, the lifetime of the carrier at that part is shortened, and the carrier generated by the incidence of α rays is N-type diffusion region 27a of groove capacitor 25a
It is possible to prevent the particles from gathering due to the funneling phenomenon, thereby realizing a semiconductor memory device with excellent soft error resistance. Furthermore, in the present invention, the pn junction capacitance between the p ⁺ type silicon substrate 21 and the p type silicon layer 22 and the n type diffusion region 27a is the same as the pn junction capacitance between the n type diffusion region 27a and the electrode 29 with the silicon oxide film 30a interposed. Since it is superimposed on the capacitance, it is possible to realize the groove-type capacitor 25a with a high capacitance value per unit area, and as a result, it is possible to increase the density of memory cells. fact, said
It was found that the pn junction capacitance reached approximately 30% of the above-mentioned capacitance value. In the above embodiment, a silicon oxide film was used as the capacitor insulating film, but the present invention is not limited to this. For example, a composite film in which a silicon nitride film is sandwiched between silicon oxide films in a sandwich pattern, a silicon nitride film, or a two-layer film of silicon oxide and tantalum oxide may be used. In the above embodiment, a p ⁺ type silicon substrate was used as the semiconductor substrate and a p type silicon layer was used as the semiconductor layer, but an n ⁺ type silicon substrate or an n type silicon layer may also be used. In this case, the second conductivity type impurity diffusion region is p-type, and the transfer transistor is a p-channel MOS transistor. Although the above embodiment has been explained using a dynamic MOS memory as an example, the present invention can be similarly applied to a static MOS memory. In this case, for example, the above-mentioned trench type capacitor may be provided at the bistable node of a flip-flop type cell. [Effects of the Invention] As detailed above, according to the present invention, groove-type capacitors having a large capacitance value per unit area are provided, and the distance between the groove-type capacitors can be significantly shortened without causing a punch-through phenomenon. This makes it possible to increase the density of memory cells, improve soft error resistance, and provide a high-density, highly reliable semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional dynamic MOS memory, FIG. 2 is a plan view of a dynamic MOS memory showing an embodiment of the present invention, and FIG.
A sectional view taken along the - line in FIG. 2, and FIGS. 4a and 4b are sectional views showing steps for forming the groove-type capacitor of this embodiment. 21...p ⁺ type silicon substrate, 22... p type silicon layer, 23... field oxide film, 24a~
24c...active region (memory cell), 25a - 2
5d... Groove capacitor, 26a, 26b... Groove portion, 27a, 27b... N type diffusion region (second conductivity type impurity diffusion region), 28a, 28b... Extension portion, 29... First conductivity type Electrodes made of polycrystalline silicon, 30a, 30b...silicon oxide film (insulating film for capacitor), 32...phosphorus-doped silicon oxide film, 33a to 33d ...transfer transistor,
34a, 34b...n ⁺ type source region, 35a,
35b...n ⁺ type drain region, 37a to 37d
...Gate electrode made of second layer polycrystalline silicon,
40, 40'...Bit line.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, on the surface of which a semiconductor layer of a first conductivity type is formed, the concentration of which is higher than that of the semiconductor layer;
a trench provided extending from the surface of the semiconductor layer into the semiconductor substrate; a second conductivity type impurity diffusion region provided across the semiconductor layer and the semiconductor substrate on the inner surface of the trench; and at least an opening extending from within the trench. and an electrode provided around the periphery of the capacitor through a capacitor insulating film, the groove-type capacitor having a structure in which the electrode is a first capacitor electrode and the impurity diffusion region is a second capacitor electrode. A semiconductor memory device characterized by: 2. The semiconductor memory device according to claim 1, wherein the impurity diffusion region of the second conductivity type of the trench type capacitor has a higher concentration than the semiconductor substrate of the first conductivity type. 3. A gate insulating film is provided over the source and drain regions of the second conductivity type provided electrically isolated from each other on the surface of the semiconductor layer of the first conductivity type, and the portion of the semiconductor layer including at least the area between these source and drain regions. and a gate electrode provided through the transfer transistor, and one of the source and drain regions is connected to the second conductivity type impurity diffusion region of the trench capacitor, and the other is connected to the bit line. A semiconductor memory device according to claim 1, characterized in that: