JPS61199657A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To contract the cell space while improving the degree of integration by a method wherein a transfer transistor coming into contact with a conductor layer of capacitor is provided on a one conductive semiconductor layer laminated on the upper part of cylindrical capacitors arranged in through holes formed in an insulating film on a conductive type substrate through the intermediary of an insulating film. CONSTITUTION:Cylindrical capacitors C are formed in through holes 23 made in a thick SiO2 insulating film 22 and then the first interlayer insulating film 27 with the first contact window 28 exposing a part of charge accumulating electrode 26 is arranged on the surface of capacitors C. Besides, a P<-> type single crystal silicon layer 29 is arranged on the first interlayer insulating film 27 above the capacitors C. Finally a transfer transistor composed of a gate oxide film 30 formed on the silicon layer 29, gate electrodes 33 comprising e.g. N<+> type polycrystalline silicon layer PC formed on the gate oxide film 30, and N<+> type region 31 to be an accumulating node coming into contact with the charge accumulating electrode 26 in the capacitors C at the first contact window 28 formed in the P<-> type single crystal silicon layer 29 and an N<+> type drain region 32 may be arranged on the P<-> type single crystal silicon layer 29.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a dynamic random access memory (CD-RAM) cell having a one-transistor, one-cabinet structure with increased capacitance.

As the functions of information processing devices have expanded, the D-RAMs installed in the information processing devices have also become larger in scale. Integration is progressing rapidly.

However, when the D-RAM becomes extremely dense and highly integrated, the amount of information charge stored in the capacitor decreases significantly due to a significant reduction in capacitor capacity due to the reduction in cell area. This causes problems such as a decrease in information readout accuracy and a decrease in resistance to soft errors caused by alpha rays (soft error alpha ray resistance), resulting in a decrease in confidence in the D-RAM. Therefore, there is a demand for a D-RAM cell with a small cell area and a large capacitor capacity.

[Conventional technology]

In the one-transistor/one-capacitor type D-RAM cell, a stacked capacitor type cell, whose side cross section is schematically shown in FIG. 3, was originally proposed as a structure for increasing the capacitor capacity.

In FIG. 3, 1 is a p-type silicon substrate, 2 is a p-type channel cut region, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, and 6 is a word line (for adjacent cells). transfer transistor gate electrode),
7 is a first insulating film, 8 is a drain, the first n+ type region 9 is a storage node, and the second n' type region 1o is a first capacitor electrode, 11 is a dielectric film, and 12 is a The second capacitor electrode, Tr, is a transfer transistor, C
indicates a capacitor.

According to this cell structure, the first capacitor electrode for charge storage is a transfer transistor (Tr) of the self-cell.
Since it extends to the upper part of the word line 6 adjacent to the gate electrode, the capacitor capacitance is 2 to 3 times higher than that of a normal D-RAM cell in which the second n-type region 8 serves as one electrode of the capacitor. It will be increased about twice as much.

However, in a situation where high integration is progressing significantly, increasing the capacitance by a factor of 2 to 3 is insufficient in terms of detection accuracy of stored information and resistance to soft error alpha rays, and it is necessary to further increase the capacitor capacity. A trench capacitor type cell has conventionally been provided as a structure for this purpose.

FIG. 4 schematically shows a side cross section of the trench capacitor type cell, in which 12a and 12b are trenches, 13a and 13b are charge storage regions (depletion layers), and 14
indicates a capacitor electrode, and other symbols indicate the same objects as in FIG.

This trench capacitor type cell has the advantage that by increasing the depth of the trench, the capacitor capacity can be further increased significantly compared to the stacked capacitor type cell having the same cell area.

[Problem that the invention seeks to solve]

However, in the trench capacitor type D-RAM cell, the charge storage regions 13a, 13b, etc. made of depletion layers formed around the trenches 128, 12b, etc. become thicker (widener) due to the voltage applied to the capacitor electrode 14. As shown in the figure, because the back bias is strong (particularly widens in the middle between the functional trench tip and the functional trench base), the trenches of adjacent cells, for example 12a and 12b, are placed close together. In this case, leakage of accumulated charge occurs between the trenches, resulting in a phenomenon in which information is lost.

Therefore, the width of the isolation region between each cell, that is, the field oxide film 3
It is necessary to widen the width of the area in which the IC is disposed, which poses a problem in that it impedes the improvement of the degree of integration.

[Means for solving problems]

The above-mentioned problem is solved by a first insulating film laminated on the conductive substrate exposed inside the through-hole and inside the through-hole in the through-hole provided in the first insulating film on the conductive substrate.
a cylindrical capacitor including a conductor layer, a dielectric film formed on the first conductor layer, and a second conductor layer laminated on the dielectric layer, the capacitor One conductivity type semiconductor layer is stacked on top of the semiconductor layer with a second insulating film interposed therebetween, and one of the opposite conductivity type regions disposed with the gate in between is the second conductivity type semiconductor layer.
This problem is solved by a semiconductor memory device according to the present invention, which includes a transfer transistor that is in contact with the second conductive layer of the capacitor through a contact window provided in the insulating film of the capacitor.

[Effect]

That is, the one-transistor/one-capacitor type D-RA of the present invention
In the M cell, the transfer transistor is arranged above the cylindrical capacitor, so the cell area is reduced, and the insulating film below the transfer transistor is formed thicker to form a through hole where the cylindrical capacitor is formed. By increasing the depth of the capacitor, the charge storage capacity of the capacitor can be greatly increased.

Since the periphery of the capacitor is separated by an insulating film, there is no leakage of information charges between adjacent capacitors (also, the periphery is separated by an insulating film, and the capacitor electrode where information charges are stored is connected to the opposite electrode). Since it is included in the shift error α ray resistance is also greatly improved.

〔Example〕

The present invention will be specifically described below with reference to illustrated embodiments.

FIG. 1 is a schematic plan view (a
) and A-A cross-sectional view (bl, Fig. 2 (al to (f)
) is a process sectional view showing the manufacturing method.

Identical objects are designated by the same reference numerals throughout the design.

In FIG. 1, 21 is a conductive substrate made of, for example, highly doped p-type silicon, 22 is a silicon dioxide (St(h)v7A film) with a thickness of about 2 to 5 μm, and 23 is, for example, 1.
Through hole of about 5 to 2 μm, 24 has a thickness of 1000 mm
A trend capacitor electrode made of a 0p type polycrystalline silicon layer P^, 25 has a thickness of 100, for example, made of 5 iOz.
The dielectric film 26 is a dielectric film with a thickness of 0, for example, an n-type polycrystalline silicon film with a thickness of about 0.5 to 1 μm, which fills the inside of the through hole.
A charge storage capacitor electrode made of iPB, 27 a first layer film made of, for example, Sing and having a thickness of about 5,000 to 8,000 layers, 28 a first contact window, and 29 a P layer having a thickness of about 3,000 to 5,000 layers. 30 is a gate oxide film of normal thickness, 31 is an n-type region 32 which becomes a storage node is an n-drain region, and 33 is a gate electrode made of an n-type polycrystalline silicon layer PC. 34 is a second glabellar insulation film made of phosphosilicate glass, 35 is a second contact window, 36 is a bit wiring made of aluminum, etc., C is a capacitor, and Tr is a transfer transistor. .

As shown in the figure, the D-RAM cell according to the present invention includes a conductive substrate 21 made of, for example, highly doped p-type silicon.
A through hole 23 exposing the surface of the substrate 21 is provided in the thick SiOg insulating film 22 provided above, and the St island insulating film including the inner surface of the through hole 23 and the surface of the substrate 21 exposed in the through hole is formed. 22, a counter capacitor electrode 24 made of a p+ type polycrystalline silicon layer PA which is ohminically connected to the substrate 21 is formed, and a dielectric material II! made of, for example, Sing is formed on the surface of the counter capacitor electrode 24. 25 is formed, and a charge storage electrode 26 made of, for example, an n-type polycrystalline silicon layer PB is provided above the through hole 23 via the dielectric film 25 to fill the inside of the through hole 23. Through hole 23 of the thick Si0g insulating film 22
A cylindrical capacitor C is formed therein, and a first contact window 28 made of, for example, 5iOt and exposing a part of the charge storage electrode 26 of the capacitor C is provided on the surface on which the capacitor C is disposed. The first glabella insulating film 27 corresponding to the upper part of the capacitor C is disposed.
P formed by single crystallization technology of polycrystalline silicon on top
A gate oxide film 30 is formed on the p-type box crystal 9937 layer 29, on the p-type box crystal 9937 layer 29, and on the gate oxide film 30. The gate electrode 33 made of, for example, an n-type polycrystalline silicon layer PC formed in A transfer transistor Tr consisting of an n9 type region 31 serving as a node and an n'' drain region 32 is disposed, and the upper part thereof is made of PSG or the like, and the n'' drain region 32 of the transfer transistor Tr is exposed. Second
A second glabellar insulating film 34 having a contact window 35 is formed, and the second contact window 3 is formed on the second interlayer insulating film 34.
5, a bit wiring 36 connected to the type drain region 32 of the transfer transistor Tr is provided.

The D-RAM is formed, for example, by the method described below with reference to process cross-sectional views shown in FIGS. 2A to 2F.

Refer to Figure 2 (a). First, p is deposited by thermal oxidation or chemical vapor deposition (CVD) method.
2 to 5 μm thick on type 0 polycrystalline silicon conductive substrate 21
A StO□vA film 22 with a thickness of 1.5% is formed using a conventional glue active ion etching (RIE') method.
A through hole 23 with a diameter of about 2 μm is formed.

Referring to FIG. 2(b), a first polycrystalline film having a thickness of approximately 1,000 layers is deposited on the SiOg insulating film 22, including the inner surface of the through hole 23 and the surface of the substrate 21 exposed inside the through hole 23, by CVD. A silicon layer P^ is formed, and the polycrystalline silicon fiPA is made into p° type by ion implantation or the like. This first polycrystalline silicon layer PA becomes the opposing capacitor electrode 24.

Next, by thermal oxidation, a SiO□ dielectric material v! with a thickness of, for example, about 100 mm is formed on the surface of the opposing capacitor electrode 24 made of PA. , 25 is then formed on the dielectric film 25 by CVD to a thickness of, for example, 0.5 to 1.5 mm to fill the through hole. A second polycrystalline silicon layer PB having a thickness of approximately 100 nm is formed, and the second polycrystalline silicon JiPB is made into an n-type by ion implantation or the like.

Referring to FIG. 2(C), the second polycrystalline silicon layer PR is then patterned by the usual RIE method to form a charge storage capacitor electrode 26 made of PB.

Referring to FIG. 2(d), a first lamina film 2 of about 5,000 to 8,000 thickness and made of, for example, Sing is deposited on the substrate by CVD.
A first contact window 28 exposing a part of the charge storage capacitor electrode 26 is formed in the first glabella insulating film 27 by a normal RIE method, and then a CVD method is used to form a first contact window 28 exposing a part of the charge storage capacitor electrode 26. A polycrystalline silicon layer with a thickness of about 3,000 to 5,000 layers is formed on the glabella insulating film 27, and the polycrystalline silicon layer is made into a single crystal by a laser annealing method using a laser beam and scanning, and then is made into a single crystal by an ion implantation method. This single crystal layer is referred to as a p-type single crystal silicon layer 29.

Refer to Fig. 2+8) Next, after patterning the p-type packed crystal 9937 layer 9 into a predetermined shape by RIE method, the p-type single crystal silicon layer 29 is patterned according to a normal MOS transistor manufacturing method. A gate oxide film 30 is formed on the gate oxide film 30, a gate electrode 33 made of a third polycrystalline silicon layer PC is formed on the gate oxide film 30, and a storage node is formed by ion implantation using the gate electrode 33 as a mask. An n° type region 31 and an n° drain region 32 are formed.

FIG. 2 (see fl) Next, a second layer made of PSG or the like is deposited on the substrate by CVD method.
A second contact window 35 exposing the n1 type drain region 32 is formed in the second interlayer insulating film 34 by an RIE method, and a second contact window 35 is formed by a reflow process. 35 is gently shaped, and then a layer of wiring material such as aluminum is formed on the second glabellar insulating film 34 by a normal vapor deposition method and patterned by an RIE method to form the second interlayer insulating film 34. 3
A bit wiring 36 is formed on the second contact window 35 to be connected to the n+ type drain region 32.

Thereafter, a cover insulating film (not shown) and the like are formed to complete the D-RAM cell according to the present invention.

As is clear from the description of the above embodiment, in principle, in the D-RAM cell according to the present invention, the conductive substrate 21
By increasing the thickness of the 5iOz insulating film 22 formed thereon and deepening the through hole 23, it is possible to significantly increase the charge storage capacity of the cylindrical capacitor C.

Further, the cylindrical capacitor C is provided within the insulating film 22,
The cylindrical capacitors of adjacent cells are separated by the insulating film 22, and leakage of information charges is completely prevented.

Furthermore, since a highly conductive substrate is used as the substrate, electrons excited in the substrate by the incidence of α rays quickly recombine and disappear, and since the capacitor is disposed within the insulating film 22, a soft error α is caused. Line resistance is greatly improved.

Note that the capacitor electrode is not limited to the polycrystalline silicon shown in the above embodiment, but may be made of a conductive material such as molybdenum silicide.

[Effects of invention]

As explained above, according to the present invention, one transistor/l
It is possible to significantly increase the capacitor capacity of a dynamic random access memory (D-RAM) cell with a capacitor structure, eliminate information charge leakage between adjacent capacitors, and improve soft error alpha ray resistance. Its credibility will improve.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view (a
1 and A-A cross-sectional view (b), Figures 2 (a) to (f)
3 is a side sectional view of a stacked capacitor type D-RAM cell, and FIG. 4 is a side sectional view of a trench capacitor type D-RAM cell. In the figure, 21 is a conductive substrate, 22 is a silicon dioxide (Sing) insulating film, 23 is a through hole, 24 is a counter capacitor electrode, 25 is a dielectric film, 26 is a charge storage capacitor electrode, and 27 is the first glabella. Insulating film, 28 is a first contact window, -29 is a p-type single crystal silicon layer, 30 is a gate oxide film, 31 is an n-type region 32 which becomes a storage node, is an n-drain region, 33 is a gate electrode (word line), . 34 is a second interlayer insulating film, 35 is a second contact window, 36 is a bit wiring, C is a capacitor, and Tr is a transfer transistor. Figure 1 Figure 2

Claims (1)

[Claims] A first conductor layer laminated on the conductive substrate, which is exposed in the inner surface of the through hole and inside the through hole, in a through hole provided in a first insulating film on the conductive substrate;
A cylindrical capacitor includes a dielectric film formed on the first conductive layer and a second conductive layer laminated on the dielectric film, and a second conductive layer is formed on the top of the capacitor. One conductivity type semiconductor layer stacked with an insulating film interposed therebetween, one of the opposite conductivity type regions disposed with the gate in between is connected to the capacitor through a contact window disposed in the second insulating film. A semiconductor memory device comprising a transfer transistor in contact with a second conductive layer.