JP3511267B2 - Semiconductor DRAM device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a semiconductor DRAM (Dynamic Random Access Memory) device, and more particularly, Ru <br/> relates to a memory cell structure of the stacked DRAM.

[0002]

2. Description of the Related Art In a semiconductor DRAM device, 3-4
The storage capacity is increasing at a rate of four times each year, and it is expected that the storage capacity will increase at the same rate in the future. In order to improve the degree of integration of the semiconductor memory device in order to increase the storage capacity, it is necessary to reduce the memory cell that is a storage unit. However, in order to prevent a soft error due to radiation and to secure a sufficient S / N ratio, it is impossible to reduce the size of the capacitor forming the memory cell at the same reduction ratio as the memory cell. Therefore, it is necessary to increase the surface area of the capacitor storage electrode to increase the capacitance. For this reason, attention has been focused on a trench memory cell in which a capacitor groove is formed on a semiconductor substrate and a stacked memory cell in which a capacitor is formed above a transistor or above the transistor and connected to a bit line, after 4 MBit DRAM.

The groove type memory cell is a method of accumulating charges on the semiconductor substrate side having a capacitor groove formed on the surface thereof. However, since it is difficult to control crystal defects and impurities in the semiconductor substrate, it is very difficult to suppress leakage of accumulated charges in the trench memory cell. In addition, in the stacked memory cell in which the capacitor is formed below the bit line, the capacitor cannot be formed above the bit line contact hole because two memory cells share one bit line contact hole. Therefore, it is difficult to increase the surface area of the capacitor storage electrode to some extent. Therefore, a method of forming a laminated capacitor on the bit line and closely packing the surface of the memory cell portion with the capacitor is considered promising.

By the way, in a memory cell structure in which a multilayer capacitor is formed on a bit line, a capacitor contact hole for connecting a storage electrode of the capacitor and one of source / drain regions of a transistor formed on the surface of a semiconductor substrate is formed. , It must be formed in a place other than the region where the bit line is arranged. Therefore, there is a method of arranging the active regions forming the memory cells obliquely with respect to the bit lines and the word lines.

As described above, as an example of the method of arranging the active regions obliquely with respect to the bit lines and the word lines, there is a method of arranging the active regions as shown in FIG. However, with such an arrangement of active regions, the active regions 1, 1
Since the width of the element isolation region 2 between them is different depending on the position such as the position (A) and the position (B), it is difficult to fill the element isolation trench with the insulating film when forming the trench type element isolation. is there.

Therefore, conventionally, as shown in FIG. 8, element isolation is performed by covering the surface of the semiconductor substrate 3 corresponding to the pattern of the element isolation region 2 with a field oxide film 5. Also, the position in FIG.
In the case of a wide element isolation region as shown in FIG. 9A, as shown in FIG. 9B, the element isolation groove 7 filled with the embedded insulating film 6 is formed.
And the field oxide film 5 are used together to form the element isolation region 2. On the other hand, in the case of a narrow element isolation region such as the position (B) in FIG. 7, the element isolation region 2 is formed only by the element isolation groove 7 filled with the embedded insulating film 6 as shown in FIG. 9A. I am doing it.

[0007]

However, in the conventional method of forming the element isolation region 2 only with the field oxide film 5, the current leakage between the memory cells becomes remarkable as the memory cells are miniaturized. However, there is a problem that it is difficult to miniaturize the memory cell.

Further, in the method of forming the element isolation region 2 using the element isolation groove 7, the field oxide film 5 must be used together in a wide element isolation region, which complicates the memory element manufacturing process. There's a problem. further,
There is also a problem that a current leak remarkably occurs due to electric field concentration at the groove edge portion of the element isolation groove 7 such as the portion (C).

[0009] It is an object of the invention is to easily allow the inter-trench element isolation is to provide a semiconductor DRAM element capable of reducing the current leakage in the groove edge portion.

[0010]

In order to achieve the above object, the first invention is a semiconductor memory cell having one transistor formed on the surface of a semiconductor substrate and one capacitor extending to a bit line. One of the two source / drain regions of the transistor is connected to the bit line through a bit line contact hole, the other is connected to the capacitor through a capacitor contact hole, and a bit line contact hole is formed. In a semiconductor DRAM device in which two semiconductor memory cells are shared by a plurality of semiconductor memory cells, a plurality of bit lines having the capacitor contact holes arranged in parallel to one direction and a plurality of bit lines arranged in a direction perpendicular to the one direction. The bit line contact hole is formed in a region surrounded by a word line and the bit line and the bit line In a region intersecting the gap between the word lines, and along the line segment that connects one bit line contact hole and two capacitor contact holes adjacent to both sides of this bit line contact hole in a straight line. One active region whose minute direction is oblique to the direction of the bit line and the word line is formed, and among the capacitor contact holes included in each active region, the number of adjacent capacitor contact holes is one. Bit lines or one word line are separated from each other, and bit line contact holes included in the active regions adjacent to each other in the word line direction are separated from each other by one word line. form as element isolation region which isolates the upper Kikatsu region, said capacitor contact holes adjacent to each other
Of the part of the element isolation region between the active region parts in the vicinity of
Width and the activity near the bit line contact holes adjacent to each other.
The width of the element isolation region between the active regions is the same.
The above two capacitor contacts
Portion of the active region in a direction orthogonal to the line segment connecting the holes
It is characterized in that it is constituted only by the groove-type element isolation structure in which the width of the component is increased .

A second invention is the semiconductor DRAM device of the first invention, wherein the groove type element isolation structure is
At least an element isolation trench carved in the semiconductor substrate and an insulating film filled in the element isolation trench up to a level of the surface of the semiconductor substrate or more and covering an edge portion of the element isolation trench are configured. that it is characterized by.

[0012]

According to the first invention, the capacitor contact hole for connecting one of the two source / drain regions of the transistor of the semiconductor memory cell to the capacitor is surrounded by the plurality of bit lines and the plurality of word lines. Formed in the area. A bit line contact hole that connects the other of the source / drain regions to a bit line is formed in an intersection region between the plurality of bit lines and the plurality of word lines. The active region of the semiconductor DRAM device including the semiconductor memory cell is a region along a line segment that straightly connects one bit line contact hole and two capacitor contact holes adjacent to both sides of the bit line contact hole. The direction of the formed line segment is oblique to the direction of the bit line and the word line.

At this time, among the capacitor contact holes included in each active region as described above, adjacent capacitor contact holes may be separated from each other by one bit line or one word line. Is made in. Further, the bit line contact holes included in the active regions adjacent to each other in the word line direction are formed so as to separate one word line from each other.

The element isolation regions for isolating the active regions are adjacent to each other by the capacitor contacts.
The part of the element isolation region between the active region parts near the hole
Width and the vicinity of adjacent bit line contact holes
The width of the element isolation region part between the active region parts should be the same.
By making it one, the above two capacitor contacts
Of the active area in the direction orthogonal to the line segment connecting the hole
It is composed only of a groove-type element isolation structure in which the width of the portion is increased . The groove type with the same width described here
The element isolation structure means that they are the same in design.
The same even if the dimension width is slightly different due to manufacturing variations.
It means to consider.

Therefore, when the groove type element isolation structure forming the element isolation region is formed by the element isolation groove and the insulating film filling the element isolation groove, the inside of the element isolation groove is formed by the insulating film. It becomes possible to embed easily.

Further, in the second invention, in the groove type element isolation structure, at least an element isolation groove carved in the semiconductor substrate and the element isolation groove are filled up to a level of the surface of the semiconductor substrate or more. It is formed by an insulating film covering the edge portion of the element isolation groove.

Therefore, the edge portion of the element isolation groove is covered with the insulating film, and the electric field concentration at the edge portion of the groove is relaxed.

[0018]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 shows an active region, an element isolation region, a word line, a DRAM semiconductor memory cell array according to this embodiment.
FIG. 6 is a plan view showing a bit line, a bit line contact hole, and a capacitor contact hole. 2 is a diagram schematically showing a connection relationship between the activation region 15 and the bit lines 11, 11, ... And the sense amplifiers 17, 17 ,. The DRAM semiconductor memory cell array according to this embodiment has a structure in which a multilayer capacitor is formed above a bit line.

Also in this embodiment, a capacitor contact hole for connecting to either one of the storage electrode of the capacitor formed above the bit line and the two source / drain regions of the transistor formed on the surface of the semiconductor substrate is formed.
It is formed in a region other than the region where the bit line is arranged.
That is, in FIG. 1, the gaps 11 ', 11', ... Between the bit lines 11, 11, ... Arranged in parallel at a predetermined interval and the predetermined intervals in the direction orthogonal to the arrangement direction of the bit lines 11, 11 ,. Gap 12 ', 1 between word lines 12,12, ... arranged in parallel
Capacitor contact holes 13, 13, ... Are installed in a region (a) where 2 '... .. and the gaps 12 ', 12', ... Between the word lines 12, 12, ... Intersect the bit line contact holes 14 according to a predetermined arrangement rule. , 14, ... are installed.

Then, a certain bit line contact hole 14
And a capacitor contact hole 13 in a region (a) that is oblique to the bit line 11 and the word line 12 and is adjacent to one side of the bit line contact hole 14.
And the capacitor contact hole 13 'existing in the diagonal direction and adjacent to the other side of the bit line contact hole 14 on the other side (a), a region along a straight line connecting one active region. 15 is formed. That is, the bit line contact hole 14 is shared by two sets of memory cells, so that one active region 15 is formed in the active regions of the two sets of memory cells.

At this time, the capacitor contact holes 13 adjacent to each other included in the active region 15 and the active regions 15 ', 15', ...
Bit lines 11 or one word line 12 are spaced apart from each other, and the bit line contact holes 14 included in the active regions 15 adjacent to each other in the direction of the word line 12 have one word. The above-mentioned arrangement rule of the capacitor contact holes 13 and the bit line contact holes 14 is predetermined so that the lines 12 are separated from each other. As a result, the respective active regions 15, 15, ... Are arranged in the same direction and at equal intervals, so that the respective active regions 15,1.
The widths of the element isolation regions 16, 16, ... Formed between 5 ,.

FIG. 3 is a sectional view taken along the line AA in FIG. In FIG. 3, when a word line is selected during reading, the gate electrode 24 of the corresponding transistor is selected.
When a voltage is applied to the transistor, the transistor turns on. The charges accumulated in the corresponding capacitance accumulated charge region 25 are transferred to the capacitor contact hole 13, the source / drain region 23, the channel layer of the semiconductor substrate 26, and the source.
It is emitted to the corresponding bit line 11 through the / drain region 23 and the bit line contact hole 14, and the potential of the bit line 11 changes. The change in the potential of the bit line 11 is detected by the sense amplifier 17, and the information stored in the capacitive charge region 25 is read. 27 is an oxide film, 28 is a gate oxide film, 29,3
Reference numerals 3 and 35 are interlayer insulating films, and 30 is a channel stopper region. Further, 31 is a capacitor insulating film, 32 is a capacitor plate electrode, 34 is a first aluminum wiring, 36 is a second aluminum wiring, and 37 is a passivation film.

At this time, as shown in FIG. 1, in the DRAM semiconductor memory cell array of this embodiment, an activation region 15 ', 15', ...
Since the intervals of the element isolation regions 16 between and are all the same, as shown in FIG. 3, the element isolation regions 16, 16, ...
Can be easily formed only by the element isolation grooves 21, 21, ....

At this time, the groove edge portion indicated by the portion (c) in the element isolation groove 21 is covered with the T-type element isolation oxide film 22 having a T-shaped cross section. Therefore, the structure is such that the electric field concentration at the groove edge portion is relaxed and the leak current is reduced.

The method of manufacturing the element isolation region 16 of the DRAM semiconductor memory cell array having the above structure will be described in detail below. <First Process Example> FIGS. 4 and 5 are manufacturing process diagrams of the element isolation region 16 of the DRAM semiconductor memory cell array having the above structure. Less than,
A method of manufacturing the element isolation region 16 according to this process example will be sequentially described with reference to FIGS.

As shown in FIG. 4A, after a thermal oxide film 52 having a film thickness of about 10 nm is formed on a semiconductor substrate (p-type semiconductor substrate in this embodiment) 51, a multi-layer having a film thickness of about 300 nm is formed. A crystalline silicon layer 53 and a first chemical vapor deposition (CVD) oxide film 54 having a thickness of about 300 nm are sequentially deposited. That is,
The thermal oxide film 5 constitutes the first insulating film, the polycrystalline silicon layer 53 constitutes the conductor film, and the first CVD oxide film 54 constitutes the second insulating film.

Next, as shown in FIG. 4B, a photo-etching process is performed to remove only the portions where the element isolation regions 16 are formed in the first CVD oxide film 54 and the polycrystalline silicon layer 53. After that, the film thickness 100
A second CVD oxide film 55 of about nm is deposited. At this time, the element isolation region 16 is shaped such that the pattern of the active region satisfies the above-mentioned condition as shown in FIG. That is, the second CVD oxide film 55
Thus, the third insulating film is formed. The width of the element isolation region in this example is 0.3 μm.

Next, as shown in FIG. 4 (c), the second CVD oxide film 5 at the location where the element isolation trench 21 is to be formed.
5 and the thermal oxide film 52 are etched back until the surface of the semiconductor substrate 51 is exposed. After that, the second CVD oxide film 55 is left only on the sidewalls of the polycrystalline silicon layer 53 and the first CVD oxide film 54, and the second CVD oxide film 55 at other portions is removed. And the remaining second C
Silicon etching is performed using the VD oxide film 55 and the first CVD oxide film 54 as a mask, and 1.0 μm to 1.5 μm
Element isolation trenches 21 having a depth of about a certain degree are formed.

Next, as shown in FIG. 5D, a thermal oxide film 56 of about 20 nm is formed on the surface of the element isolation groove 21, and then B (boron) ions are implanted by oblique ion implantation to form a channel. The stopper region 30 is formed. After that, the first CVD oxide film 54 is removed, and a thermal oxide film of about 20 nm is formed on the surface of the polycrystalline silicon layer 53. Then, the third CVD oxide film 57 is deposited and the element isolation groove 21 is formed.
Are embedded to flatten the surface. That is, the third CV
The D oxide film 57 constitutes the fourth insulating film.
At this time, since the element isolation regions 16 are formed to have the same width as described above, the element isolation trenches 21 can be easily filled with the third CVD oxide film 57.

Next, as shown in FIG. 5E, a third CVD oxide film 57 is formed until the polycrystalline silicon layer 53 is exposed.
Is etched back to form a T-type element isolation oxide film 22. In this way, the T-type element isolation oxide film 22 is formed by filling the element isolation groove 21 with the third CVD oxide film 57 up to the level of the surface of the semiconductor substrate 51 or above, thereby forming the trench of the element isolation groove 21. The edge portion is covered with the T-type element isolation oxide film 22. As a result, the electric field concentration at the groove edge portion is relaxed and the leak current is reduced. Finally, as shown in FIG. 5 (f), the polycrystalline silicon layer 53
And after removing the exposed thermal oxide film 52, the film thickness is 10 nm.
A gate oxide film 28 is formed to some extent.

In this way, the element isolation region 16 of the DRAM semiconductor memory cell array is formed. After that, a semiconductor memory cell array having a structure as shown in FIG. 3 is formed by a known method.

<Second Process Example> FIG. 6 is another manufacturing process diagram different from the first process example of the element isolation region 16 of the DRAM semiconductor memory cell array having the above structure. Hereinafter, the method of manufacturing the element isolation region 16 according to this process example will be sequentially described with reference to FIG. After the steps shown in FIGS. 4A to 5D in the above-mentioned first step example, the third CVD oxide film 57 is etched back under the etching condition having no selection ratio with respect to the polycrystalline silicon layer 53. .

Next, as shown in FIG. 6A, a film thickness of 150 n
A tungsten silicide film 61 and a CVD oxide film 62 of about m are sequentially deposited. Then, a photoresist layer 63 is patterned on the CVD oxide film 62 in a word line pattern by a photoresist process.

Next, using the photoresist layer 63 as a mask, the CVD oxide film 62, the tungsten silicide film 61, and the polycrystalline silicon layer 53 are sequentially etched. Thus, as shown in FIG. 6B, the T-type element isolation oxide film 2 is formed.
In the active region 15 surrounded by the element isolation regions 16 formed of the element isolation trenches 21 in which 2 is embedded, the gate electrode 24 formed of the polycrystalline silicon layer 53 and the tungsten silicide film 61 connected to the gate electrode 24 are formed. The word line 12 is formed.

Next, a source / drain region 23 is formed after forming an oxide film 27 around the gate electrode 24 and the word line 12 by a known method. After that, the source / drain regions 23 sandwiched by the oxide film 27 are formed.
A contact plug 64 for a capacitor contact or a bit line contact is formed on the surface of the.

Thereafter, the semiconductor memory cell array having the structure shown in FIG. 3 is formed by a known method. That is, in the second process example, the polycrystalline silicon layer 5 is
3 is used to form the gate electrode 24 of the transistor,
The gate oxide film 28 is formed by using the thermal oxide film 52. By doing so, since the gate electrode 24 and the gate oxide film 28 can be formed when the element isolation region 16 is manufactured, the subsequent formation of the semiconductor memory cell array is facilitated.

As described above, in the DRAM semiconductor memory cell array according to the present embodiment, the capacitor contact holes 13-bit line contact holes 14-which are adjacent to each other and which are linearly connected to the bit line 11 and the word line 12 in a diagonal direction. An active region 15 is formed in a region including the capacitor contact hole 13. And each active region 1
Of the capacitor contact holes 13 included in 5, 15, ...
Bit lines 11 or one word line 12 are separated from each other, and bit line contact holes 14 included in the active regions 15 adjacent to each other in the direction of the word line 12 are separated from each other by one word line 12. The arrangement rule of the capacitor contact holes 13, 13, ... And the arrangement rule of the bit line contact holes 14, 14 ,. As a result, the element isolation regions 16 formed between the active regions 15 have the same width. Therefore, the element isolation oxide film 22 can be easily embedded in the element isolation trench 21 forming the element isolation region 16, and the trench type element isolation can be easily performed.

When manufacturing the DRAM semiconductor memory cell array, the thermal oxide film 52 is formed on the semiconductor substrate 51.
A polycrystalline silicon layer 53 is laminated on the semiconductor substrate 51, and an element isolation groove 21 is formed in the semiconductor substrate 51 by etching. On the other hand, in the polycrystalline silicon layer 53, a groove communicating with the element isolation groove 21 and wider than the element isolation groove 21 is formed. Then, a third CVD oxide film 57 is deposited, and a third CVD oxide film 57 is deposited on the trench of the polycrystalline silicon layer 53 and the element isolation trench 21.
Of the T-type element isolation oxide film 2 by burying the CVD oxide film 57 of
Forming 2. As a result, the groove edge portion of the element isolation groove 21 is covered with the T-type element isolation oxide film 22, and the electric field concentration at the groove edge portion is alleviated. Therefore,
Current leakage at the groove edge is reduced.

The sectional structure of the DRAM semiconductor memory cell array according to the present invention is not limited to the sectional structure shown in FIG. The point is that the cross-sectional shape of the insulating film filling the inside of the element isolation trench 21 should be such that it also covers the groove edge portion of the element isolation trench 21. The shape of the active region of the DRAM semiconductor memory cell array according to the present invention is not limited to the shape shown in FIG.
The point is that the shapes should be such that they are arranged in the same direction and satisfy the above-mentioned conditions and have the same intervals.

[0040]

As is apparent from the above, the semiconductor DRAM device according to the first aspect of the present invention includes a region along a line segment that straightly connects two capacitor contact holes adjacent to both sides of one bit line contact hole. Active regions that are oblique to the directions of the bit lines and the word lines are formed, and capacitor contact holes that are adjacent to each other among the capacitor contact holes that are included in the respective active regions form one bit line or one word line. The bit line contact holes included in the active regions that are separated from each other and are adjacent to each other in the direction of the word lines are separated from each other by one word line, and the active regions are separated from each other. Since the element isolation region is constituted only by the groove type element isolation structure having the same width, when the element isolation region is formed by the groove type element isolation, The isolation trench may be filled easily by the insulating film. That is, according to the present invention, it is possible to easily separate the groove type elements from each other. still,
The groove-type element isolation structure having the same width described here is
It means that the accounting is the same, and due to manufacturing variations.
In the sense that it is considered the same even if the dimension width is slightly different
is there.

According to a second aspect of the semiconductor DRAM device of the present invention, the groove-type element isolation structure is formed by at least an element isolation groove carved in the semiconductor substrate and a level of the surface of the semiconductor substrate in the element isolation groove. Since the insulating film is filled up with the insulating film, the edge portion of the element isolation groove is covered with the insulating film. Therefore, to alleviate the current concentration at the edge portion, Ru can reduce the occurrence of current leakage.

[Brief description of drawings]

FIG. 1 is a plan view showing an arrangement example of active regions in a semiconductor DRAM device of the present invention.

FIG. 2 is a schematic diagram showing a connection relationship between a sense amplifier and the active region and bit line shown in FIG.

3 is a cross-sectional view taken along the line AA in FIG.

FIG. 4 is a manufacturing process diagram of an element isolation region of a DRAM semiconductor memory cell array according to the present invention.

FIG. 5 is a manufacturing process diagram following FIG. 4;

FIG. 6 is another manufacturing process diagram of the element isolation region of the DRAM semiconductor memory cell array according to the present invention.

FIG. 7 is a diagram showing an arrangement example of active regions in a conventional DRAM semiconductor memory cell array.

FIG. 8 is a sectional view showing a structure of an element isolation region in a conventional DRAM semiconductor memory cell array.

9 is a cross-sectional view showing the structure of another element isolation region different from that in FIG.

[Explanation of symbols]

11 ... Bit line, 12 ... Word line, 13 ... Capacitor contact hole, 14 ... Bit line contact hole, 15 ... Active region,
16 ... Element isolation region, 17 ... Sense amplifier,
21 ... Element isolation trench, 22 ... T type element isolation oxide film, 23 ... Source / drain region, 24 ... Gate electrode, 25 ... Capacitance accumulated charge region, 28 ... Gate oxide film, 51 ... Semiconductor substrate, 52 ... Thermal oxide film , 53 ...
Polycrystalline silicon layer, 57 ... Third CVD oxide film,
61 ... Tungsten silicide film, 64 ... Contact plug.

Claims (2)

(57) [Claims] 1. In a semiconductor memory cell having one transistor formed on the surface of a semiconductor substrate and one capacitor extending onto a bit line, one of two source / drain regions of the transistor is a bit line contact hole. A semiconductor DRAM device in which one bit line contact hole is shared by two semiconductor memory cells, and the other is connected to the bit line via the Forming a capacitor contact hole in a region surrounded by a plurality of bit lines arranged in parallel to one direction and a plurality of word lines arranged in parallel to a direction perpendicular to the one direction; A hole is formed in an intersection region between the plurality of bit lines and the plurality of word lines, and one via is formed. Of the bit line contact hole and two capacitor contact holes adjacent to both sides of the bit line contact hole along a straight line segment, and the direction of the line segment is relative to the direction of the bit line and the word line. One active region is formed in a diagonal direction, and among the capacitor contact holes included in each active region, adjacent capacitor contact holes are separated by one bit line or one word line. together, form as present at a bit line contact hole between each other one word line included in the active region adjacent to each other in the direction of the word line, element separation between upper Kikatsu region Separation areas are adjacent to each other
Active area near the capacitor contact hole
The width of the above-mentioned element isolation region between
Between the active region near the bit line contact hole
By making the width of the element isolation region the same,
Directly connect to the line segment connecting the two capacitor contact holes.
A semiconductor DRAM device characterized in that it is constituted only by a groove-type device isolation structure in which the width of the active region portion in the intersecting direction is increased . 2. The semiconductor DRAM device according to claim 1, wherein the groove type element isolation structure has at least an element isolation groove carved in the semiconductor substrate and a level of a surface of the semiconductor substrate in the element isolation groove. A semiconductor DRAM device comprising an insulating film filled up to the above and covering an edge portion of the device isolation trench.