JPH0435913B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dynamic MIS semiconductor memory element and a method for manufacturing the same.

(Prior art) In recent years, there has been a growing trend towards higher integration and higher density of semiconductor memory elements, and along with this, the miniaturization of elements has progressed. As a result, we are facing various technical difficulties on many fronts. In particular, dynamic random access memory (hereinafter abbreviated as DRAM)
In a one-transistor memory cell consisting of one transistor and one storage capacitor, which is a typical structure of the techniques are being considered. "A
CORRUGATED CAPACITANCE CELL
(CCC) FOR MEGABIT DYNAMICMOS
H.SUNAMI titled “MEMORIES”
In a paper published by et. The element area is smaller than that of a memory element.

(Problem to be Solved by the Invention) However, the element area is approximately 21 square microns including the surrounding isolation area, and if a 4 megabit memory circuit is created using this structure, the memory element area The area alone is about 88 square millimeters, which is quite large.

The purpose of the present invention is to eliminate such conventional drawbacks, reduce the device area overwhelmingly compared to the conventional device with the same design standard, and furthermore, the channel part of the control transistor is electrically connected to the substrate, and It is an object of the present invention to provide a semiconductor memory element compatible with a folded bit line configuration and a method for manufacturing the same.

(Means for Solving the Problems) According to the present invention, the first impurity doped layer of the second conductivity type is provided on a part of the side surface on the first conductivity type silicon single crystal substrate, and the first impurity doped layer of the second conductivity type is provided on the upper surface. It has a columnar structure composed of a first conductivity type single crystal silicon layer having a second conductivity type second impurity doped layer that is not continuous with the second conductivity type impurity doped layer, and The first impurity doped layer is partially buried with first conductivity type silicon whose periphery is electrically connected to the substrate single crystal silicon, and an insulating film is formed on the top surface of this buried layer, and the first impurity doped layer is covered with the buried layer. A gate insulating film is formed on the side surface of the columnar structure, and a conductor layer that is in contact with the gate insulating film and straddles the first and second impurity doped layers of the second conductivity type serves as a gate electrode. There is obtained a semiconductor memory element characterized in that two bonitos are arranged in parallel between columns of columnar structures in a mutually insulated manner, and each bonito is in contact with every other columnar structure via a gate insulating film.

Furthermore, according to the present invention, a single crystal silicon layer of a second conductivity type is formed on a single crystal silicon substrate of a first conductivity type, and a desired region is formed into a columnar shape deeper than the silicon layer by etching. Then, the exposed silicon surface is covered with an insulating film, and only the insulating film deposited on the etched and dug bottom surface is selectively etched away, and the substrate is etched more deeply to remove the insulating film formed in the process. Using the film as a mask, the exposed silicon surface is doped with impurities of the second conductivity type, and the surface is covered with a thin insulating film. The second conductivity type impurity doped layer is selectively etched away, and the first conductivity type silicon is buried in the groove until the upper end of the second conductivity type impurity doped layer provided at the lower side of the columnar structure remains. , an insulating film is formed on the surface of the buried layer, and an insulating film is formed on the first side surface for odd rows of the matrix of the columnar structure, and on the side surface opposite to the first side surface for the even rows. The silicon surface is exposed by etching away from the surface to the upper end of the impurity doped layer of the second conductivity type, and a gate insulating film is formed thereon. There is obtained a method for manufacturing a semiconductor memory element characterized in that two conductor layers serving as gate electrodes are formed between rows of the columnar structure so as to straddle the side surface of the second conductivity type impurity doped layer provided on the top of the columnar structure.

Furthermore, according to the present invention, a single crystal silicon substrate of the first conductivity type is etched leaving a desired region in the form of a columnar structure, an impurity of the second conductivity type is doped on the side surface of the columnar structure silicon, and the surface is covered with a thin insulating film. The thin insulating film and the impurity doped layer of the second conductivity type, which are also formed on the bottom surface of the silicon substrate dug around the columnar structure, are selectively etched away, and silicon of the first conductivity type is deposited in the trench. burying the impurity doped layer of the second conductivity type provided on the side surface of the columnar structure until the upper end thereof remains, forming an insulating film on the surface of the buried layer, and forming a single crystal silicon layer of the first conductivity type on the top surface of the columnar structure. further selectively forming a second conductivity type single crystal silicon layer on the upper surface thereof, forming an insulating film on the buried layer to at least the same height as the second conductivity type single crystal silicon layer, and forming a columnar shape. For the odd rows of the structure matrix, the insulating film on the first side surface, and for the even rows, the insulating film on the side surface opposite to the first side surface from the top of the impurity doped layer of the second conductivity type. A gate insulating film is formed thereon by etching to expose the silicon surface, and a second conductive type impurity doped layer is provided on the upper end of the second conductive type impurity doped layer and on the top of the columnar structure in contact with the gate insulating film. A method for manufacturing a semiconductor memory element is obtained, which is characterized in that two conductor layers serving as gate electrodes are formed between each row of a columnar structure so as to span the side surfaces of the layers.

(Example) Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a partially cutaway perspective view showing an embodiment of the first invention of the present application, showing a memory element for 4 bits. 101 is a single-crystal p-type silicon substrate, 102 is a p-type silicon single crystal with a columnar structure perpendicular to the substrate 101, and 103 is a p-type silicon substrate provided on the lower part of the side wall of this columnar structure.
Alternatively, an n-type impurity doped layer 104 forms a junction capacitance with the p-type silicon 102 provided in a form that is electrically connected to the n-type impurity doped layer 104, which is SiO ₂ or SiO ₂ that covers at least a part of the surface of the impurity doped layer 103.
It is an insulating thin film having a laminated structure of Si ₃ N 4 and Si 3 N ₄ , and forms an MIS capacitor between it and the p-type silicon 105 .

Reference numeral 106 denotes an n-type impurity doped layer formed at the top of the columnar structure, and this doped layer and 103 constitute the source/drain electrodes of the control MIS transistor. The p-type silicon 102 between these two doped layers constitutes a channel portion. In this way, a control MIS transistor is formed on the upper side of one pillar, and a storage capacitor is formed on the lower side, and the channel portion of the transistor is electrically connected to the substrate. Reference numeral 107 indicates an insulating film such as SiO ₂ that fills the remaining portion of the trench, 109 indicates a gate insulating film, and 108 indicates two n-type impurity doped layers 103 and 1 in contact with the gate insulating film.
06 and constitutes the gate electrode of the control MIS transistor and serves as the ^word line. Reference numeral 110 is a metal and is connected to the n-type doped layer to form a bit line. In this way, a dynamic memory cell is constructed.

The insulating thin film 104 forming the MIS capacitor completely covers the pn junction with the p-type silicon substrate 104a.
A case like this and a case like 104b where the pn junction is not completely covered may occur during the process of partially removing the insulating thin film. The storage capacity is a composite capacity of MIS type capacitance and junction type capacitance, and in the case of the former, MIS
The area of the mold and the area of the joint mold are approximately equal, and in the latter case, most of the mold is the joint mold. These 2
The two capacitances are the area represented by the product of the peripheral length of the columnar structure, the overlap height of the n-type impurity doped layer 103 and the p-type buried layer 105, and the area where the n-type impurity doped layer 103 is in contact with the p-type layer 102. increases according to the sum of Therefore, even if the cross-sectional area of the columnar structure portion is made small, there is an advantage that a sufficiently large storage capacity can be obtained by increasing the dimension in the depth direction, that is, the height direction of the substrate.

The conductor films 108, which serve as gate electrodes of this structure, are arranged in two parallel rows 108a and 108b between columns of columnar structures, and are in contact with every other columnar structure via a gate insulating film to form a control MIS transistor. Therefore, the bit line 11 extending in the row direction
0 can adopt a folded type. Therefore, compared to the open type, the arrangement pitch of the sense up is doubled, and there are advantages such as relaxing design standards for peripheral circuits and improving noise resistance.

If this structure is used, when the design standard is F,
The minimum occupied area can be reduced to 6F ² (2F x 3F), making it possible to achieve high density. etc., the channel part of the control transistor is connected to the p-type substrate via the p-type part at the center of the columnar structure, and problems that occur when the channel part is floating from the substrate (charge increase in the channel, threshold This has the advantage of avoiding problems such as voltage instability.

Hereinafter, a more specific example of this embodiment will be described with reference to FIG. 2 together with the second invention (manufacturing method) of the present application.

First, a substrate in which an n-type impurity doped layer 206 with a thickness of about 0.5 μm is formed on a p-type single crystal silicon substrate 201 with a concentration of about 5×10 ¹⁶ cm ^-3 is used, and a thin SiO ² membranes, thickness 1000 on top
Using a mask pattern consisting of a Si ₃ N ₄ film with a thickness of about 1.5 Å thick and a thick SiO ₂ film laminated on top of it, the area where the memory cell is to be formed on the substrate is etched by 2 μm by anisotropic etching such as reactive ion etching (RIE). A prismatic pattern of 1.5 μm x 1.5 μm arranged at a pitch of 3 μm in the horizontal direction and a pitch of 4.5 μm in the vertical direction was formed by digging to a certain extent. Thereafter, the exposed silicon surface was covered with an insulating film 211 such as a silicon oxide film, and only the insulating film on the bottom of the dug silicon trench was selectively removed. (Fig. 2a) Next, the silicon groove is further dug by about 6 μm using RIE, and an n-type impurity doped layer 203 is formed shallowly on a part of the side surface of the columnar structure by a thermal diffusion method of arsenic, etc. (Figure 2b).

Next, the n-type impurity doped layer that is also formed on the bottom of the silicon trench dug by the thermal diffusion is selectively removed by anisotropic etching, and then a thin insulating film, such as a thermal oxide film or a thermal oxide film, which will become the MIS capacitor is etched. and
A stack 204 with CVD nitride is formed on the exposed silicon surface. Thereafter, the insulating film deposited also on the bottom of the silicon trench was selectively removed by anisotropic etching (FIG. 2c). If the anisotropy of the etching is slightly poor or the columnar structure is slightly slanted, a portion of the insulating thin film at the bottom of the sidewall will be removed as shown in FIG. 104b. However, the remaining area of the insulating thin film after etching is 10% between adjacent cells.
Unlike 4a and 104b, there is no extreme variation, and the variation is the same within at least one chip.

FIG. 2d shows a state in which the dug silicon trench is filled with a p-type silicon layer 205 of about 5 μm by selective epitaxial growth. As a filling method, a p-type polycrystalline silicon film may be grown in vapor phase and then etched, or this method may be combined with selective epitaxy.

Figure 2e shows that after filling the remaining groove with a silicon oxide film 207 using CVD, RF bias sputtering, or silica glass coating, two n-type impurity doped layers 203 and 206 are separated. A groove 212 with a depth of about 2.5 μm and a width of about 1.5 μm is in contact with the surface of a part of the p-type columnar silicon 202 that is continuous with the substrate.
This shows the state in which it has been formed.

FIG. 2 f shows that after a gate insulating film is formed on the exposed silicon surfaces of the silicon layers 202, 203, and 206 by a thermal oxidation method, etc., a gate insulating film is formed by a chemical vapor deposition (CVD) method at least in contact with the side walls of the trench. It shows a state in which n ⁺ polycrystalline silicon 208, which is formed into a wire, is deposited over the entire surface to a thickness of about 0.5 μm.

In Figure 2g, the grooves are etched by an anisotropic etching method such as reactive ion etching (RIE).
After removing the polycrystalline silicon deposited on the bottom of the polycrystalline silicon deposited in the shape of a letter, the top of the columnar structure, and the buried insulating film 207, word lines 208a and 208b, 208c and 208 are separated as word lines.
d shows a state in which an insulating film 207' is buried by a combination of CVD and RIE etching.

Next, as shown in FIG. 1, an interlayer insulating film is formed on the entire surface, and a metal wiring 110 that becomes a bit line is formed.
By applying this to the n-type impurity doped layer 106,
A dynamic memory cell with a new structure can be obtained.

If there is a risk of leakage occurring in the n-channel MOS transistor, fill in boron glass (BSG) instead of the silicon oxide film 207 and fill the trench 2.
After forming the gate electrode 108, heat treatment is performed to form the gate electrode 108.
What is necessary is to dope boron into the silicon in the region that is not in contact with the silicon.

Next, an embodiment of the third invention (manufacturing method) of the present application will be described with reference to FIG.

First, a p-type single crystal silicon substrate 301 with an impurity concentration of about 5×10 ¹⁶ cm ^-3 is used, and a thickness of
Anisotropic etching such as reactive ion etching (RIE) using a mask pattern consisting of a thin SiO ₂ film of about 200 Å, a Si ₃ N ₄ film of about 1000 Å thick, and a thick SiO ₂ film on top of that. A region of the substrate where a memory cell is to be formed is dug to a depth of about 6 μm to form a prismatic pattern having the same dimension in the plane direction as in the above embodiment. After this, an n-type impurity doped layer 303 is formed on the side surface of the columnar structure by a thermal diffusion method of arsenic, etc.
A thin insulating film 304 serving as a MIS capacitor, such as a thermal oxide film or a laminated film of a thermal oxide film and a CVD nitride film, is formed on its surface. (FIG. 3a) Next, the insulating film deposited also on the bottom surface of the silicon trench and the n-type impurity doped layer covered therewith are selectively removed by anisotropic etching, and then the trench is etched as described above. Similar to the embodiment, a p-type silicon layer 305 is buried to a depth of about 5 μm by selective epitaxial growth using SiH ₂ Cl ₂ and HCl as source gases, and the surface of the buried layer is further thermally oxidized to form a silicon oxide film 3.
Cover with 07. (Figure 3b) Next, the top surface of the columnar structure is exposed, and a p-type silicon stack 322 with a thickness of 1 μm and an n ⁺ type silicon stack 306 with a thickness of 0.5 μm are successively formed by selective epitaxial growth. (Figure 3c). At this time, it is of course possible to form a p-type silicon stack with a thickness of 1.5 μm and form an n ⁺ layer on the top surface by implanting arsenic ions or the like. The state in Figure 3c is the second
In terms of the figure, this corresponds to an intermediate state between figure d and figure e.
Therefore, the latter part of the embodiment of the second invention of the present application can be used for the following steps. In this embodiment, as shown in FIG. 3c, a p-type silicon stack 322,
An n ⁺ type silicon laminated layer 306 was formed on the entire upper surface of the columnar structure. However, these two laminated layers may be formed only on a portion of the upper surface of the columnar structure. However, the p-type silicon stack 322 must be electrically connected to at least a portion of the p-type portion on the upper surface of the columnar structure. Even in this embodiment, if there is a risk of leakage occurring in the transistor, boron can be doped as in the previous embodiment.

Although the present invention has been described above based on one embodiment, the same effect can be obtained even if the p-type and n-type of the embodiment are replaced.

Furthermore, instead of crystalline silicon, the gate electrode 108 can be made of a high melting point metal such as tungsten, molybdenum, or titanium, or a silicide thereof, or a multilayer structure thereof. Since it is normally desirable that the work function φ _M of the gate electrode be constant over the channel, it is preferable to form multiple layers so that the portion of the gate electrode that spans the channel and the other portions are made of a constant material.

Furthermore, in this embodiment, the columnar structure matrix is arranged in a straight line in both the row and column directions, so the two hood lines arranged between the columns have a meandering shape, as shown in FIG. Word line pair 108a, 1
It is also possible to arrange the pillars 08b in a straight line and to shift the positions of the pillars between odd and even rows. FIG. 4 shows a memory element for 5 bits.

The rows of a matrix with a columnar structure are arranged in a straight line, but the columns are arranged in a meandering manner (the intersection with the even-numbered row and the intersection with the odd-numbered row are on two adjacent but different lines). Therefore, two conductor films 10 serving as gate electrodes are arranged in parallel between adjacent columns.
Each of 8a and 108b can be made straight, which has the advantage of being shorter than a meandering word line, resulting in lower resistance and higher speed.

FIGS. 5a and 5b are schematic plan views showing still another embodiment. In both figures a and b, the columnar structures 501 are arranged in a straight line in the row direction, and meander in the column direction so as to overlap each other by half the diameter of the columnar structures. In figure a, one gate electrode 108a is straight, and the other gate electrode 108b is meandering. In figure b, the three rows of both gate electrodes are straight lines, but when viewed as a whole, they meander significantly.

(Effect of the invention) As a result, in the embodiment shown in FIG.
In the example shown in Fig. 4, a dynamic MIS semiconductor memory element can be fabricated in a small area of 3 μm x 3.75 μm with a design rule of 1.5 μm, and the storage capacitor area alone is sufficient at 30 ^μm2 . You can make it bigger. If the pn junction capacitance is also added, it becomes even larger. Therefore, it was found that it can sufficiently withstand soft errors such as α-ray errors. Furthermore, the effective channel length of the control transistor can be made sufficiently large, approximately 1 μm or more, and the short channel effect can be suppressed. Furthermore, the channel section of the control transistor is electrically connected to the substrate through the center of the columnar structure, and the channel section potential oscillates due to the charge pumping phenomenon that occurs when the channel section is floating from the substrate. There are no concerns about bipolar operation.

If the present invention is applied to the 1.5 μm design rule and a 1 megabit memory circuit is manufactured, the area of only the memory element portion in the embodiment shown in FIG. 1 is 14.1 mm ² (3.07 mm x 4.61
mm), 11.6mm ² (3.04×3.80mm) in the example shown in Figure 4.
In the case of 4 megabits using the 1 μm design rule, the area is 25.2 mm ² (4.10 mm x 6.14 mm) in the example shown in Figure 1, and 20.6 mm ² (4.06 x 5.07 mm) in the example shown in Figure 4, including peripheral circuits. It was also found that the 64K DRAM package can be accommodated in a cage about the same size as the current 64K DRAM package.

[Brief explanation of drawings]

1 and 4 are partially cutaway perspective views showing embodiments of the structure of the memory element of the present invention, and FIGS. 2a-g,
FIGS. 3a to 3c are partially cutaway perspective views showing embodiments of the method for manufacturing a memory element of the present invention, respectively.
FIGS. 5a and 5b are schematic plan views showing an embodiment of the structure of a memory element according to the present invention. In the figure, 101, 201, 301... p-type silicon substrate, 102, 202... p-type silicon columnar structure, 103, 203, 303... n-type impurity doped layer, 102, 202... p-type silicon columnar structure, 103,203...N-type impurity doped layer, 104,204...Insulating thin film, 105,20
5...P-type silicon buried layer, 106...N-type impurity doped layer, 107...Insulating film, 108...
Conductor film such as polycrystalline silicon, refractory metal or refractory metal silicide, 109... Insulating thin film, 1
10... Metal, 211... Insulating film, 212... Groove dug in insulating film, 104, 204, 304
...Insulating thin film, 105, 205, 305...p-type silicon layer, 106...n-type impurity doped layer, 3
06...N-type silicon stack, 107,307...
Insulating film, 108... Conductor film, such as polycrystalline silicon, refractory metal, or refractory metal silicide, 10
9... Insulating thin film, 110... Metal, 211... Insulating film, 212... Groove dug into insulating film, 32
2...P-type silicon stack.

Claims (1)

[Claims] 1. A silicon single crystal substrate of a first conductivity type, having a first impurity doped layer of a second conductivity type on a part of a side surface, and a layer doped with an impurity of a second conductivity type on an upper surface. It has a columnar structure composed of a first conductivity type single crystal silicon layer having a second conductivity type second impurity doped layer that is not continuous, and the periphery of the columnar structure is electrically connected to the substrate single crystal silicon. The first impurity doped layer is buried halfway with silicon of the first conductivity type connected to the silicon, an insulating film is formed on the top surface of this buried layer, and a gate insulating film is formed on the side surface of the columnar structure that is not covered with the buried layer. is formed, and first and second conductive layers of the second conductivity type are in contact with the gate insulating film.
It has a conductor layer that serves as a gate electrode spanning the impurity-doped layer, and two of the conductor layers are arranged in parallel between the columns of the columnar structure in a mutually insulated manner, and each bonito is placed in the columnar structure every other column. A semiconductor memory element characterized by being in contact with each other through a gate insulating film. 2 A monocrystalline silicon layer of a second conductivity type is formed on a single-crystal silicon substrate of a first conductivity type, and is etched to leave a desired region deeper than the silicon layer in the form of a column and exposed. Covering the silicon surface with an insulating film, selectively etching away only the insulating film deposited on the etched and dug bottom surface, etching the substrate even more deeply, and using the insulating film formed in the process as a mask. The exposed silicon surface is doped with impurities of the second conductivity type, and the surface is covered with a thin insulating film. selectively etching and removing the impurity doped layer, burying silicon of the first conductivity type in the groove portion until the upper end of the impurity dope layer of the second conductivity type provided at the lower side surface of the columnar structure remains; and the buried layer. An insulating film is formed on the surface, and the insulating film on the first side surface for odd rows of the matrix of the columnar structure, and on the side surface opposite to the first side surface for the even rows, is coated from the surface to the first side surface. Etching and removing the second conductivity type impurity doped layer to the upper end of the second conductivity type impurity doped layer to expose the silicon surface and forming a gate insulating film there; A method for manufacturing a semiconductor memory element, comprising: forming two conductor layers to serve as gate electrodes between rows of a columnar structure so as to straddle side surfaces of a second conductivity type impurity doped layer. 3. Etching the single crystal silicon substrate of the first conductivity type while leaving a desired region in the form of a column, doping the side surface of the silicon columnar structure with an impurity of the second conductivity type, covering the surface with a thin insulating film, and etching the area around the columnar structure. The thin insulating film and the impurity doped layer of the second conductivity type, which are also formed on the bottom surface of the trenched silicon substrate, are selectively etched away, and the silicon of the first conductivity type is deposited in the groove on the side surface of the columnar structure. burying the impurity doped layer of the second conductivity type provided on the columnar structure until the upper end thereof is left, forming an insulating film on the surface of the buried layer, forming a single crystal silicon layer of the first conductivity type on the upper surface of the columnar structure, and further forming a single crystal silicon layer on the upper surface of the columnar structure. selectively forming a single crystal silicon layer of a second conductivity type, forming an insulating film on the buried layer to at least the same height as the single crystal silicon layer of the second conductivity type; For odd-numbered rows, the insulating film on the first side surface, and for even-numbered rows, the insulating film on the side surface opposite to the first side surface is etched away from the surface to the top of the second conductivity type impurity doped layer. exposing the silicon surface and forming a gate insulating film thereon, the gate insulating film being in contact with the gate insulating film and extending over the upper end of the second conductive type impurity doped layer and the side surface of the second conductive type impurity doped layer provided on the top of the columnar structure; A method for manufacturing a semiconductor memory element, comprising: forming two conductor layers to serve as gate electrodes between rows of a columnar structure.