JPS6190395A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To improve the resistance against a software error due to an alpha ray, etc., by bringing a conductive type of a semiconductor area into contact with an impurity added area of a reverse conductive type at the groove of the semiconductor area, where a capacitor is embedded, and biasing these area in a prescribed manner. CONSTITUTION:The groove equipped with an insulation film 40 at the inner surface of a substrate 10 of P type Si, etc., and the capacitor for forming a memory element is embedded in the groove. The conductive-type substrate 10 and the P type impurity area 11 of the reverse conductive type are embedded in contact with this groove, and this area 11 is biased in a manner that a potential with respect to a minor carrier of the substrate 10 will be always lower than the connection node of an accumulation electrode provided for the capacitor. Accordingly, even if an electron-hole pair 62 is produced by the alpha ray, the electron or hole flow to the area 11 having a low potential, an the occurrence of the software error is prevented, thereby improving the resistance against the software error due to the alpha ray, etc.

Description

[Detailed description of the invention] [Industrial application field] Present invention 1'; td-RAM (dynamic random RAM)
This invention relates to a method for enhancing alpha ray resistance of access/memory cells.

The mainstream of d-RAM cells has been the double polysilicon type, but as integration becomes higher, more advanced types of cells with larger storage capacities are required. Also, one of the problems with d-RAM cells is that when α rays hit, electron-hole pairs (Electron-Hole Pa) are formed in the substrate.
1r) occurs, which poses a problem of causing a lift error.

[Conventional technology]

FIG. 5 shows one of the conventional cell structures for achieving high integration of d-RAM. This is a trench capacitor (commonly known as a trench capacitor), in which a pore 51 is formed from the main surface of a semiconductor substrate toward the inside of the substrate, and an insulating film 53 and a capacitive electrode ( polysilicon, etc.). In addition, in Fig. 5, 55 + 56 is the FE of the transfer gate.
North of T. In the n10 region of the drain, 57 is a word line, 57 is a word line of an adjacent cell, and 59 is a bit line. In the trench type capacitor, an inversion (electronic) layer 50 serving as a charge storage electrode is formed adjacent to the pore 51 . Now, if α rays 63 hit this trench capacitor, electron-hole pairs 62 are generated in the semiconductor substrate, which are attracted by the electric field between the depletion layers and enter the n-layer 55, causing an offset error. be. In particular, in the case of a trench type capacitor, the depletion layer ω has a very large spread, so the trapping cross section is large, and a structure that is resistant to offset errors cannot be achieved. Another drawback is that punch-through tends to occur between cells, which prevents the desired degree of integration from being achieved.

On the other hand, in order to suppress punch-through, the inventor of the present invention developed a DIET-C cell (Dielectric
e! LpSulated Trench-Capacity
tor cell). This is shown in FIG. 4, where the trench capacitor is formed exactly within the capsule of the insulating film 40. The capacitor is formed of two polysilicon layers 4] and 43 on an insulating film 40, and an insulating film 42 between them. The insulating film 42 is formed by thinly oxidizing the surface of the lower polysilicon 4 or by depositing an oxide film. For other parts,
Since the same numbers are given to the corresponding parts as in the previous 5th to 5th figures, the explanation will be omitted. In the structure shown in Figure 5, the inversion layer blade is one electrode, and it is just exposed in the Si substrate, and when the depletion layers (A) of the cells come together, it punches through. occurs. On the other hand, in the structure shown in FIG. 4, the capacitor is housed in the recess of the insulator, so that it is electrically isolated. Therefore, the depletion layer 44 may extend through the insulating film 40, but in this case, even if the depletion layers of the cells are pinched, punch-through will not occur. Therefore, the structure of FIG. 4 can have a higher degree of integration than that of FIG. However, with regard to the strength against alpha rays, the structure in which the trench capacitor is housed in the capsule of the insulating film 40 shown in FIG. 4 alone is not necessarily satisfactory. Even with the insulating film 40, if a positive voltage is accumulated in the storage electrode, a depletion layer inevitably extends into the substrate because the substrate is of P type. This becomes a depletion layer of the so-called MO8 structure, but the extension of the depletion layer is smaller than the known one shown in Fig. 5 due to the insulating film inserted between them, and is strong against alpha rays. If α rays run through the depletion layer and electron-hole pairs are generated, the electrons will be attracted by the electric field within the depletion layer and move to the side with a higher potential. When the potential of the n0 region 55 of the transfer gate is high, the generated electrons are attracted to the tan0 region group,
As a result, there is a possibility that a lift error will occur.

[Problem that the invention seeks to solve]

The present invention solves the problem that the improved trench type capacitor as shown in FIG. 4 described above still has insufficient resistance to alpha rays and may cause a phantom error.

[Means for solving problems]

In the present invention, a storage electrode is attached via an insulating film to the inner surface of a groove dug into the semiconductor from the surface of a semiconductor of one conductivity type, a dielectric film on the storage electrode, and a dielectric film. In the semiconductor memory device, at least a portion of the groove is in contact with a region of a conductivity type that is the same as the conductivity type of the connection portion of the storage electrode, that is, a conductivity type different from the conductivity type of the semiconductor, and A voltage is applied to the cough region so that the potential for the minority carriers of the -4 type semiconductor is always lower than that of the storage electrode.

That is, according to the present invention, in at least one of the dug grooves (pores) of a trench capacitor surrounded by an insulating film as shown in FIG. The impurity doped regions are formed so as to be in contact with each other. The impurity doped region of the opposite conductivity type to the substrate is biased so that the substrate's potential for minority carriers is always lower than the connection node of the storage electrode of the trench capacitor.

[Function] Now, if the power supply voltage is 5V, for example, 5V is connected to the above-mentioned reverse conductivity type impurity doped region, while the connection node of the storage electrode, for example, the n0 region, is connected to a lower voltage of 4V.
A voltage of about V is applied.

Then, a depletion layer extends from the insulating film around the trench capacitor to the substrate, and even if α rays hit this depletion layer and generate electron-hole pairs, the electrons are transferred to the higher potential side, that is, the lower potential for electrons. It moves to the impurity doped region of the opposite conductivity type, and is eventually absorbed by the power supply and has no effect. If there is a possibility that a power error may occur, it is thought that α rays are directly hit on the n-middle region of the connection node, but since the area ratio of the n-middle region is small,
Overall, the ft error rate when exposed to alpha rays can be significantly reduced.

〔Example〕

(First Embodiment) In FIG. 1, among the numbers of each part, the same parts as those in FIG. An insulating film 40 is laminated on the surface of the pore 51, and the insulating film 40 serves as a capsule for storing the trench capacitor inside. A silicon layer and an insulating film 42 formed by oxidizing its surface. A counter electrode (cell plate) 54 and a portion 43 buried in the trench thereof are made of polysilicon.

55 and 56 are the sources of transformer 7 agate FETs,
n middle region of the drain, 57 is a word line, 59 is a word line of the next cell, 59 is a bit line, 61 is a field oxide film,
62 is an electron-hole pair generated by the α ray 63.

The above structure is the same as that of the improved trench capacitor shown in FIG. and the n
The ten-shaped buried layer 11 is in contact with a groove 51 dug in the substrate at least at one point. Then, the n-type buried layer 1
1 is biased so that the potential is always higher than the n0 layer relationship at the connection portion of the storage electrode 41 (this potential relationship is reversed in the P channel type).

Specifically, the power supply voltage is set to 5V, and 5V is supplied to the nx-shaped buried layer 11, while the maximum voltage written to the storage electrode 41 is set to about 4.8V in the circuit configuration. From this K, the potential of electrons in the buried layer 11 is always lower than the n-layer function at the storage electrode connection part, so even if minority carriers (electrons) enter the depletion layer 12 due to α-ray irradiation, This flows into the n+ type buried layer 11 having a low potential, and no error occurs.

This principle can be easily understood by considering the FET shown in FIG.

The surface of the drilled pore 51 enclosed in an insulating capsule is 1
It can be thought of as two MOS FETs. n-shaped buried layer 11
Since the potential is high, the drain D and the storage electrode 41 are connected to the gate G.
and is connected to the source S corresponding to the n raw electrode 55 of the storage electrode. In this state (gate voltage) Vc=V
The MOSFET does not turn on because of s (source voltage). When electrons enter the channel portion of the MOS FET by α-ray irradiation, the electrons flow toward the drain D and never enter the source S. This is the principle of the invention.

To give a more specific example of the configuration shown in FIG. 1, B-doped St with a specific resistance of 100 cm is used as the P-type substrate 10, and the n+-type buried layer 11 is made of Sb with a center concentration of 100 cm.
Form to about m. Storage electrode 41 of trench capacitor
is formed of 1500'A polysilicon, its surface is oxidized at about 150A to form 5iOs+42, and a counter electrode polysilicon 43 is formed thereon. The trench capacitor is formed in a capsule in which the periphery of a pore 51 with a diameter of 2 μm and a depth of 4.5 μm is covered with a 1000× film of StO+ (4). The field oxide film 61 has a thickness of 5000×. .

The interlayer insulating film on the cell plate 54 is 4000 A, and the word line 58 of the adjacent cell is formed on it, and the word line 57 is
All of the edges are made of polysilicon or MoSi2. Note that all the polysilicon layers used above are n
The layer is doped in shape. The n10 layers 55 and 56 of the transfer gate are ion-implanted layers of As+, and the dose is 201 scm-ffi. The depth L of the upper end of the n-shaped buried layer 11 is 4 pm, so the pore 51
The tip of 0.5 μm is in contact with the n-shaped buried layer 11.

(Second Embodiment) In FIG. 3, a P-shaped bitaxial layer 32 is formed on an n-type substrate 31, and a pore 51 is formed in the P-type epitaxial layer 32.
At the same time, the pores 51 are made to partially extend to the n-type substrate 31, so that the n-type substrate 31 becomes the n-type buried layer 11 in FIG.
It is designed to function in the same way.

If the potential of the n-type substrate 31 is always biased to be higher than the potential of the n layer 55 at the connection part of the storage electrode 4, the electrons of the electron-hole pair 62 generated by the α ray will always be directed downward. It will not come off to the board side and cause a lift error. Note that in this embodiment, a P-type ion implantation layer may be used in addition to the P-type epitaxial layer 32. As a specific example, an sb-doped (0.01Ωam) 8 is used as the n-type substrate 31.
1, and the P-type epitaxial layer 32 is boron-doped (
10Qcm ) Si layer with a film thickness of 4 pm. The bias is 5V for the substrate 31 and OV or VBB=-av for the P type epitaxial layer 32.

〔Effect of the invention〕

According to the present invention, an impurity doped region of the conductivity type opposite to the conductivity type of the semiconductor region in which the ridge groove is formed is in contact with at least one part of the trench dug in the trench capacitor whose periphery is covered with an insulating film. In addition, since the impurity doped region is biased so that the potential for substrate minority carriers is always lower than the connection node of the storage electrode of the trench capacitor, α
Even if electron-hole pairs are generated by the beam, the electrons (or holes) flow toward the impurity doped region of the opposite conductivity type, which has a lower potential, and it is possible to prevent the occurrence of a lift error.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram thereof, and FIG. 3 is a sectional view of a second embodiment of the present invention.
FIG. 4 is a sectional view of an improved trench type capacitor, and FIG. 5 is a sectional view of a conventional trench type capacitor. 10...P-type St substrate, 11...n-type buried layer,
12... Depletion layer, 40... Insulating film, 41... Storage electrode (polysilicon), 42... Insulating film, 43...
(Counter electrode) Groove embedded part (polysilicon), 51.
... Pore, C... Counter electrode (cell play), 55.
56... (source, drain) n middle layer, 57... word line, gate line... word line of adjacent cell, 59... bit line, 61... field oxide film, 62... electron −
Hole pair, 63...α ray.

Claims (1)

[Claims] A storage electrode attached via an insulating film to the inner surface of a groove dug into the semiconductor from the surface of a semiconductor of one conductivity type, a dielectric film on the storage electrode, and a counter electrode via the dielectric film. In the semiconductor memory device, the groove is at least partially in contact with a region of the same conductivity type as the connection portion of the storage electrode, and the region is always in contact with a semiconductor of the one conductivity type than the storage electrode. A semiconductor memory device characterized in that a voltage is applied such that the potential for minority carriers in the semiconductor memory device is lowered.