JP2671903B2 - Dynamic random access memory device - Google Patents

Description

The present invention relates to a DRAM device, and more particularly, to a structure of a capacitor cell used in the device, for the purpose of preventing the occurrence of soft errors and improving operation reliability. A substrate; a capacitor formed inside a trench formed in the semiconductor substrate; and a MIS transistor formed in the semiconductor substrate for switching charge / discharge of electric charge for the capacitor, the capacitor comprising: A first dielectric layer formed so as to cover a peripheral portion of a bottom portion of the trench and a side wall portion; and a source region or a drain region of the MIS transistor formed to be embedded in the trench so as to cover the first dielectric layer. A first conductive layer ohmic-connected to either one of the regions, a second dielectric layer formed to cover the first conductive layer, and a trace to cover the second dielectric layer. A second conductive layer having a conductivity type opposite to that of the semiconductor substrate, the second conductive layer being embedded in the semiconductor substrate and extending over the semiconductor substrate, the second conductive layer being a bottom portion of the trench. Is formed so as to penetrate the central part of the semiconductor substrate so as to be conductive with the semiconductor substrate.

[Industrial applications]

The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM) device, and more particularly to the structure of a capacitor cell used in the device.

DRAM cells have been miniaturized year by year due to the demand for high integration. Along with this, the charge storage capacity is decreasing, and there are problems such as soft error and decrease in output voltage. For this reason, there is a need for a DRAM device that can realize a larger storage capacity with a smaller cell area while preventing a malfunction due to a soft error or the like.

[Conventional technology]

FIG. 4 is a sectional view showing the structure of a memory cell in a conventional DRAM device. The example shown in FIG. 4 is a buried and stacked capacitor cell.
Capacitor Cell; BSCC, 46th Annual Proposal Proceedings P.423, 1985
The case of DRAM with October) is shown.

In the figure, 1 is a p-type semiconductor substrate, 2 is a field insulating layer for defining a cell region, 3 is a gate insulating layer, 4 is a word line (gate electrode), 5 and 6 are high-concentration (n ⁺ -type). ) Source and drain regions, 7 is a high-concentration (p ⁺ -type) region for blocking the operation of a parasitic transistor formed in the substrate, 8 is a trench formed in the substrate, and 9a is a trench side surface. The formed capacitor dielectric layer, 10a is a storage electrode of the capacitor, 11a is a dielectric layer of the capacitor, 12a is a counter electrode (cell plate) of the capacitor, 13 is an interlayer insulating layer, and 14 is in contact with the source region 5. The bit line thus formed on the interlayer insulating layer 13 is shown.

In the structure shown in FIG. 4, the semiconductor substrate 1, the gate insulating layer 3, the word line (gate electrode) 4, the source region 5 and the drain region 6 form a metal / oxide / semiconductor (MOS) transistor of a memory cell, More broadly, metal-insulator-semiconductor (MIS) transistors are formed. Further, the semiconductor substrate 1 functioning as a counter electrode, and the dielectric layer
9a and the storage electrode 10a form a first capacitor of the memory cell, while the storage electrode 10a and the dielectric layer 11a are formed.
And the counter electrode (cell plate) 12a form a second capacitor of the memory cell. By thus forming the two capacitors by utilizing both the buried structure and the laminated structure, the capacitance of the capacitors is increased without increasing the area of the memory cell unit.

[Problems to be solved by the invention]

In the above-mentioned conventional structure, it is assumed that α rays are incident on the substrate as indicated by the arrow in the figure. Such α rays (α particles) are often emitted from radioactive elements such as uranium and thorium contained in package materials and IC memory materials, but when the α particles enter the substrate,
Electron-hole pairs (carriers) are generated as shown in FIG.

In the illustrated example, since the storage electrode 10a is covered with the dielectric layer 9a, carriers (electrons in this case) generated in the substrate are not collected by the storage electrode 10a. Therefore, the excess carriers, that is, the electrons generated in the substrate due to the incidence of α particles are as shown by the arrows in the figure.
Collected in the n ⁺ type drain region 6 and the source region 5.

In particular, since the drain region 6 is a portion connected to the storage electrode 10a of the capacitor, if carriers are excessively collected in this region, the potential of the region is lowered, which may cause loss of stored information. Occurs. That is,
A soft error occurs, which causes an inconvenience that the DRAM malfunctions.

The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide a DRAM device capable of preventing the occurrence of a soft error and improving operation reliability.

[Means for solving the problem]

The above-mentioned problems in the conventional technique can be solved by devising the structure of the cell so that excessive carriers generated in the substrate due to incidence of α particles and the like are not excessively collected in the source / drain regions of the transistor.

Therefore, according to the present invention, a semiconductor substrate of one conductivity type,
A capacitor formed inside a trench formed in the semiconductor substrate; and a MIS transistor formed in the semiconductor substrate for performing charge / discharge switching for the capacitor. A first dielectric layer formed so as to cover a peripheral portion of the bottom portion and a side wall portion, and one of a source region and a drain region of the MIS transistor formed to be embedded in a trench so as to cover the first dielectric layer. A first conductive layer ohmic-connected to the region of the second conductive layer, and a second conductive layer formed to cover the first conductive layer.
Dielectric layer and a second conductive layer that is embedded in the trench to cover the second dielectric layer and extends over the semiconductor substrate and has a conductivity type opposite to that of the semiconductor substrate. And a second conductive layer penetrating a central portion of a bottom portion of the trench so as to be conductive with the semiconductor substrate.

(Operation)

According to the above-mentioned structure, the excess carriers generated in the semiconductor substrate due to the incidence of the α particles penetrate the central portion of the bottom of the trench and are conducted to the substrate.
Positively flows into the conductive layer of. Therefore, the amount of carriers collected in the source or drain region of the transistor is relatively reduced and the potential variation in the region is suppressed, so that the possibility of loss of stored information can be avoided. In other words, prevent the occurrence of soft error and DR
The operational reliability of AM can be improved.

The details of other structural features and operations of the present invention will be described with reference to the accompanying drawings and embodiments described below.

〔Example〕

FIG. 1 shows the structure of a memory cell used in a DRAM device as an embodiment of the present invention.
Shows a cross section of the memory cell, and (b) shows an equivalent circuit thereof.

In FIG. 1, 1 is a semiconductor substrate made of p-type silicon (Si), 2 is a field insulating layer made of silicon dioxide (SiO ₂ ) for defining a cell region, 3 is a gate insulating layer made of SiO ₂ , 4 Represents a word line (gate electrode) made of titanium silicide (TiSi ₂ ) or the like, and 5 and 6 represent a high concentration (n ⁺ type) source region and drain region, respectively.
Further, 7 is a high-concentration (p ⁺ -type) region, which indicates a region that prevents a parasitic MOS transistor formed in the substrate from operating, that is, functions as a channel stopper.

8 is a trench formed in the substrate including the field region, 9 is an insulating layer made of SiO ₂ formed on the side surface of the trench, and is a region functioning as a capacitor dielectric,
10 is a storage electrode of a capacitor made of poly-Si, 11 is an insulating layer made of SiO _2, and functions as a dielectric of the capacitor, 12 is a counter electrode of the capacitor made of high-concentration (n ⁺ -type) poly-Si (Cell plate) 13 is an interlayer insulating layer made of SiO ₂ , and 14 is in contact with the source region 5 through a contact hole, and a word line (gate electrode) 4 is provided on the interlayer insulating layer 13.
A bit line of aluminum (A1) or the like extending in a direction orthogonal to is shown. Reference numeral 15 denotes an n ⁺ type region formed between the counter electrode (cell plate) 12 and the substrate 1, in which n type impurities are diffused from poly-Si in the counter electrode (cell plate). Formed by.

As shown in the equivalent circuit of FIG. 1B, the semiconductor substrate 1, the gate insulating layer 3, and the word line (gate electrode) 4
And the source region 5 and the drain region 6 form a MOS transistor (n-channel type) Q of a memory cell, and also functions as a counter electrode (cell plate), the semiconductor substrate 1, the dielectric layer 9, and the storage electrode. 10 forms the first capacitor C1 of the memory cell, while the storage electrode 10, the dielectric layer 11 and the counter electrode (cell plate) 12 form the second capacitor C2 of the memory cell.

In this embodiment, a bias voltage of -3V is applied to the semiconductor substrate 1, a voltage of 2.5V is applied to the counter electrode (cell plate) 12, and the potential of the storage electrode 10 is set to 5V. .

Next, a method of manufacturing a main part of the cell shown in FIG. 1, that is, a method of manufacturing a capacitor cell will be described with reference to the process diagrams of FIGS. 2 (a) to 2 (h).

First, in step (a), a SiO ₂ insulating layer for a pad is formed on the p-type Si substrate 1 by thermal oxidation, and then a p-type impurity is formed on a region where a field insulating layer is to be formed by photolithography. For example, boron (B) is ion-implanted,
The channel stopper region 7 is formed. Then, the area 7
The surface of the is oxidized to form the field insulating layer 2, then the SiO ₂ insulating layer for the pad is removed, the SiO ₂ insulating layer (corresponding to the gate insulating layer 3) is formed, and the gate electrode is further formed on the SiO ₂ insulating layer. After forming (not shown in FIG. 2), n-type impurities are ion-implanted at a high concentration to form a source region (not shown in FIG. 2) and a drain region 6.

In the next step (b), the trench 8 is formed in the Si substrate 1 at a predetermined region of the field insulating layer 2 to a depth of about 4 μm by using ordinary lithography and reactive ion etching (RIE). .

In the next step (c), approximately 200 Å (20 nm) is applied to the inner surface of the trench 8 and the surface of the field insulating layer 2 by thermal oxidation.
The SiO ₂ insulating layer 9 is formed to a thickness of. This corresponds to the dielectric of the first capacitor C1.

In the next step (d), a chemical vapor deposition (CVD) method is used to cover the entire surface of the substrate including the inner surface of the trench 8 by about 0.2 to 0.3 μm.
Form a poly-Si layer with a thickness of m. Then, using photolithography, the regions of the other poly-Si layer are removed so that the region around the trench of the poly-Si layer remains and the region that is ohmic-connected to the drain region 6 of the transistor remains. To do. This forms the storage electrode 10 of the capacitor.

In the next step (e), the portion of the poly-Si layer 10 and the portion of the SiO ₂ layer 9 are removed by the RIE method in the central portion of the bottom of the trench. As a result, the bottom of the trench once contacts the semiconductor substrate (p-type conductive region).

In the next step (f), similar to step (c), about 20 is formed on the bottom of the trench and the surface of the storage electrode 10 by thermal oxidation.
The SiO ₂ insulating layer 11 is formed with a thickness of 0Å (20 nm). This corresponds to the dielectric of the second capacitor C2.

In the next step (g), RIE is performed in the same manner as in step (e).
The SiO ₂ layer 11 is removed in the central portion of the bottom of the trench by the method. As a result, the bottom of the trench contacts the semiconductor substrate (p-type conductive region).

In the final step (h), n ⁺ -type poly-Si that is highly doped with arsenic (As) or phosphorus (P) on the surface of the dielectric layer 11 by CVD, for example, to the extent that the trench is sufficiently filled is used.
Growing layer, counter electrode of capacitor (cell plate)
Form 12. Then, when heat of about 1000 ° C. is applied, the n-type impurity contained in the poly-Si layer diffuses into the substrate, thereby forming the n ⁺ -type region 15 near the bottom of the trench. As a result, the counter electrode (cell plate) 12 and the substrate 1
Becomes conductive via the n ⁺ type region 15.

After that, according to a normal process, an interlayer insulating layer 13 is formed on the entire surface of the substrate, and a contact window for wiring is opened on the source region 5.
A bit line 14 made of Al is formed.

Next, the effect of the cell structure of FIG. 1 will be described with reference to FIG.

As described above, in this embodiment, the storage electrode, that is, the poly
Since the electric potential of the Si layer 10 is set high, a channel is formed around the dielectric layer 9 of the capacitor as shown in FIG.
16 and a depletion layer 17 are formed.

In this state, when α-rays, that is, α-particles enter the substrate as indicated by arrows in the figure, electron-hole pairs (carriers) are generated. Of the carriers generated by the incidence of α particles, excess carriers (electrons in this case) will of course partially flow into the drain region 6 or the source region 5 of the transistor, but most of them will be affected by the electric field of the depletion layer 17. Flows into channel 16 (illustrated by arrow). The electrons flow in the channel and into the n ⁺ type region 15 at the bottom of the trench (illustrated by the arrow). Also, from the substrate to the n ⁺ type region 15
There is also a route that directly flows into (illustrated by the arrow).

As described above, the excess carriers generated in the semiconductor substrate 1 due to the incidence of α particles are n ⁺
It positively flows into the mold region 15, that is, into the counter electrode (cell plate) 12 of the capacitor. Therefore, the amount of carriers collected in the drain region 6 or the source region 5 of the transistor is relatively reduced, and as a result, fluctuations in the potential of the region are suppressed. Therefore, it is possible to prevent the occurrence of a soft error, which in turn can improve the operational reliability of the DRAM.

Although the n-channel type cell has been described in the above-described embodiments, it is obvious that the present invention is not limited to this and can be similarly applied to an opposite p-channel type cell.

〔The invention's effect〕

As described above, according to the present invention, by devising the cell structure so that excessive carriers generated in the substrate due to incidence of α particles or the like are not excessively collected in the source / drain regions of the transistor, soft error Occurrence can be prevented, and thereby operational reliability can be improved.

[Brief description of the drawings]

1 (a) and 1 (b) show an embodiment of the present invention.
3A and 3B are diagrams showing the structure of a memory cell used in a DRAM device, in which FIG. 2A is a sectional view, FIG. 2B is an equivalent circuit diagram, and FIGS. 2A to 2H are main parts of the cell of FIG. FIG. 3 is a cross-sectional view for explaining the effect of the cell structure of FIG. 1, and FIG. 4 is a cross-sectional view showing the structure of a memory cell in a DRAM device as an example of a conventional type. (Explanation of symbols) 1 ... Semiconductor substrate (p-type), 2 ... Field insulating layer,
3 ... Gate insulating layer, 4 ... Word line (gate electrode),
5 ... Source region (n ⁺ type), 6 ... Drain region (n
⁺ Type), 7 ... Channel stopper region (p ⁺ type), 8 ...
Trench, 9 ... Insulating layer (capacitor dielectric layer), 10
...... Capacitor storage electrode, 11 …… Insulation layer (capacitor dielectric layer), 12 …… Capacitor counter electrode (cell plate), 13 …… Interlayer insulation layer, 14 …… Bit line, 15 …… n ⁺
Mold area, Q ... Transistor, C1, C2 ... Capacitor.

Claims (1)

(57) [Claims] 1. A MIS semiconductor substrate of one conductivity type, a capacitor formed inside a trench formed in the semiconductor substrate, and a MIS formed in the semiconductor substrate for switching charge / discharge of charges. A first dielectric layer formed to cover a peripheral portion of a bottom portion of the trench and a sidewall portion, and a capacitor formed to be embedded in the trench to cover the first dielectric layer. A first conductive layer ohmic-connected to either one of a source region and a drain region of the MIS transistor, a second dielectric layer formed to cover the first conductive layer, A second conductive layer having a conductivity type opposite to that of the semiconductor substrate, the second conductive layer covering the second dielectric layer and being embedded in the trench, and extending over the semiconductor substrate. The conductive layer of the train A dynamic random access memory device, which is formed so as to be able to conduct to the semiconductor substrate by penetrating a central portion of a bottom portion of the switch.