JPH05190801A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device, wherein the cell area is small and the element-isolating structure having the small leaking current in a diffusing region is provided. CONSTITUTION:The figure is the plan view indicating one cell of a DRAM, which is formed of one transistor and one capacitor. Element isolation is provided with a field effect transistor in at least one part. A dummy word line 13, which is formed in parallel with a word line 3, is used as the gate electrode of the element-isolating field effect transistor. The element isolation in the direction of a bit line 12 is provided with an ordinary insulating oxide film. Since the corners of the insulating oxide films are omitted, the leaking current is further decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (Dynamic Random Access Memor) having fine memory cells.
y, hereinafter referred to as DRAM).

[0002]

2. Description of the Related Art A DRAM uses a one-transistor cell having a small number of constituent elements per memory cell for high bit integration. It is characterized in that it is composed of only a capacitor for storing charges and a transistor for transferring the charges, and n-channel MOS technology has been used so far. As for the structure of this one-transistor / one-capacitor cell, many structures such as a planar type, a stacked type and a trench type have been devised in order to obtain a large storage capacity in a small area. FIG. 12 shows a sectional view of a conventional stacked cell. The manufacturing process typically utilizes three-layer polysilicon technology. As the semiconductor substrate, for example, the P-type silicon semiconductor substrate 1 is used. First, the surface of the semiconductor substrate 1 is oxidized to form an element isolation oxide film 2 made of a thick silicon oxide film around the elements in one cell. An N ⁺ impurity diffusion region 4 is formed in this element region to serve as a source / drain region.
A first silicon oxide film is formed on the semiconductor substrate 1 via a thin silicon oxide film.
A polysilicon film as a layer is formed and selectively removed by etching to form a word line 3 to be a gate electrode. War
The drain line 3 is formed in the element region, but is also formed on the element isolation region 2. In order to reduce the resistance, the word line 3 may use polysilicon silicide instead of polysilicon. The word line 3 in the element area is
It is arranged on the region between the impurity diffusion regions 4 of the semiconductor substrate with a gate oxide film interposed therebetween.

On the semiconductor substrate 1 including the word line,
For example, an interlayer insulating film 5 such as BPSG is applied, and a second-layer polysilicon film is deposited thereon. At that time, a contact hole 7 is formed in the interlayer insulating film 5 on either one of the impurity diffusion regions 4 to bring the impurity diffusion region 4 into contact with the polysilicon film. This polysilicon film is removed by etching leaving the inside of the contact hole 7 and its periphery to form the storage node electrode 6. The surface of the electrode 6 is oxidized to form a silicon oxide film having a thickness of about 100 Å, which becomes the capacitor insulating film 8. A third-layer polysilicon film is deposited on the interlayer insulating film 5 including the capacitor insulating film 8 to form a plate electrode 9. This insulating film, the storage node electrode 6 and the plate
A capacitor is formed by the gate electrode 9, and a portion where this one capacitor is formed is defined as one cell region. Since the capacitor is also formed in the element isolation region, the region of one cell does not necessarily match the element region formed on the semiconductor substrate. An interlayer insulating film 10 made of, for example, BPSG is formed on this capacitor. Further, a contact hole 11 is formed in this insulating film to expose the impurity diffusion region 4 where the storage node electrode 6 is not formed. Then, a bit line (data line) 12 made of, for example, aluminum is formed on the insulating film 10, and the contact hole 1 is formed.
1 to connect to the impurity diffusion region 4. A plurality of cells having such a structure are assembled and peripheral circuits are connected to form a semiconductor memory device. As can be seen from the figure, since the capacitor can be arranged on the switching transistor or the word line, a large storage capacity can be obtained with a small cell area. Further, the soft error rate can be improved because the diffusion area is not required in the charge storage section.

FIG. 1 is a partial plan view in which two cells are connected.
Shown in 1. 12 is a partial sectional view of one cell of FIG. 11,
FIG. 13 is a circuit configuration diagram thereof. FIG. 11 shows the word line 3, the storage node contact hole 7, and the bit line contact hole 11, but the bit line formed so as to intersect the word line is shown as follows. Omit it. As shown in the figure, a memory cell composed of an insulating gate type field effect transistor (hereinafter referred to as a MOS transistor) for switching and a capacitor for storing information (charge) is used as a word line and a bit line (data line). To choose by. This figure shows an example of the folded bit line system. The circuit configuration diagram of this folded bit line system is
It is shown in FIG. In FIG. 11, two word lines and one bit line are arranged in the area shown by the thick line for giving one cell. Here, if the width or space of each wiring is simply F, the plane area of one cell is 8F.
Given in ² . From this, in order to further reduce the area of one cell, it is necessary to reduce the value of F.

[0005]

As described above, for example, in a DRAM formed by one transistor and one capacitor by the conventional folded bit line system,
Two word lines and one bit line are arranged in the area of the cell. Therefore, assuming that the width of the wiring is F as described above, the cell area can be expressed by 8F ² , and from this fact, it is understood that the width of the wiring can be reduced to reduce the area. However, simply reducing the F-number requires a new lithography technique, and is not simple and requires a new technique.

Further, the element isolation region on the outer periphery of the element region forming the cell is usually a LOCOS (Local Oxidation Of S
The leakage current in the diffusion region is prevented by using a thick selective oxide film formed by the isolation method. The leak current in the diffusion region is divided into an area-dependent term and a peripheral length-dependent term. The absolute value of the leak current depending on the peripheral length depends on the structure of the element isolation, and the leakage current of the element isolation method using a transistor is about two digits as compared with the element isolation method using the LOCOS isolation method. Few. Therefore, CCD
For devices such as (Charge Coupled Device) which have a stricter leak current allowable value than DRAM, a device isolation method is used for element isolation. In the future, DRA
In M as well, the demand for reducing the leak current is expected to increase, so there is a big problem how to perform element isolation. The present invention has been made under the above circumstances, and an object thereof is to provide a semiconductor memory device having a small cell area and a small leak current in a diffusion region.

[0007]

The present invention is characterized in that a field effect transistor is used for element isolation in a DRAM constituted by one transistor and one capacitor, and cells are connected by an open bit line system. That is, the semiconductor memory device of the present invention includes a semiconductor substrate and a plurality of switching insulating gates formed on the semiconductor substrate.
A field effect transistor and a charge storage capacitor, and a device isolation region surrounding the device region in which the memory cell is formed. At least a part of the device isolation region is formed on the semiconductor substrate. Saw
It is characterized in that it is composed of a gate / drain region, an element isolation transistor formed of a gate electrode formed on these regions and between these regions via a gate oxide film. The gate electrode of the element isolation transistor has means for supplying a voltage of 0 V or less. When the semiconductor substrate is P-type silicon, the gate electrode of the element isolation transistor may be made of P-type polysilicon. The source / drain regions of the switching insulating gate type field effect transistor and the element isolation transistor may each have an LDD structure. Also, a semiconductor substrate, a word line formed on the semiconductor substrate, a bit line formed on the semiconductor substrate so as to intersect with the word line, and formed on the semiconductor substrate. A memory cell which is composed of an insulating gate type field effect transistor and a charge storage capacitor and is connected to the bit line and the word line, and an element in the bit line direction which is formed on the semiconductor substrate and is composed of an insulating oxide film. A transistor including an isolation region, a pair of impurity diffusion regions formed in the semiconductor substrate, and a gate electrode formed on the impurity diffusion regions and between the regions through a gate oxide film. The second feature is that the device isolation region in the word line direction is provided. The memory cell is always arranged near the intersection of the word line and the bit line, and a sense amplifier having a pair of the bit lines connected so as to lead out in opposite directions on two opposing surfaces thereof. Can also be provided.

[0008]

Since at least a part of the device isolation uses the transistor isolation method, the leak current in the impurity diffusion region in the cell can be remarkably reduced. Further, in this separation method, it is advantageous to use the open bit line method instead of the conventional folded bit line method, and by using this method, the cell area can be reduced without changing the width of the wiring. Will be able to. In the cell arrangement of the folded bit line system, two word lines arranged in one cell are turned off.
In the Pumbit line type cell, one word line and 0.5 dummy word lines for element isolation are formed in total of 1.5. Further, since one bit line is required as before, the cell area of the present invention is 6F ² when the minimum line and space are simply F, which is 25% smaller than the cell area of 8F ² of the folded bit line system. Become.

[0009]

Embodiments of the present invention will be described with reference to the drawings.
A first embodiment will be described with reference to FIGS. Figure 1
FIG. 1A is a schematic plan view of a semiconductor memory device according to a first embodiment of the present invention. 2 is a sectional view taken along the line BB ′ in FIG. 1, FIG. 3 is a sectional view taken along the line CC ′ in FIG. 1, and FIG.
5 is a characteristic diagram showing the gate potential dependency of the leak current in the diffusion region and a cross-sectional view of the semiconductor substrate including the gate electrode and the impurity diffusion region. FIG. 5 shows the open bit line system of the present invention. It is a circuit block diagram which shows arrangement | positioning of a cell. As shown in FIGS. 1 and 2, in this embodiment, the bit line 12 is formed between the capacitor region and the dummy word line and the word line, and the capacitor for storing the electric charge is formed. It is formed above the bit lines and word lines, and its shape is characterized in that a parallelogram portion is added to a square or rectangular portion. Since the capacitor is at the top, its area, that is, the capacitance, can be made as large as possible, and since the parallelogram is joined to the square or rectangular part, each cell's The long axis of the bit line can be deviated from the line where the storage node contact holes of the capacitor are aligned.
Therefore, the bit line can be formed linearly between the contact hole in which the storage node electrode is formed and the contact hole in which the storage node electrode of the capacitor of the adjacent cell is formed.

The characteristic of this semiconductor memory device is that the word line 3 is used.
The dummy word line 13 is formed between the rows of the lines, and the portion in which the dummy word line is formed is used as an element isolation region.
A MOS transistor is formed in this region to separate transistors. The semiconductor substrate 1 has, for example, P
Type silicon is used. First, impurities are diffused in the semiconductor substrate 1 to form a plurality of N-type impurity diffusion regions (hereinafter referred to as diffusion regions) 4 in the surface region thereof. These diffusion regions are used as source / drain regions for element isolation transistors and switching transistors. Then, an oxide film is formed on the semiconductor substrate 1 by, for example, heat treatment to form a gate oxide film or the like. On this oxide film, for example,
A polysilicon film or a polysilicon silicide film is deposited and selectively etched, and the word line 3 and dummy wire are formed.
Forming a wire 13. The word lines and the dameword lines are alternately arranged in parallel. Then, the semiconductor substrate 1 is covered with an interlayer insulating film 5 such as BPSG or PSG in order to insulate the word line and the like.

Then, a bit line contact hole 11 for connecting the bit line to the diffusion region 4 of the semiconductor substrate 1 is formed in the interlayer insulating film 5 or the like by using anisotropic etching or the like,
A conductive film such as silicide is formed thereon. afterwards,
The bit line 12 is formed by selectively removing the conductive film by etching or the like. Bit line 12 has contact hole 1
1 is also formed in the switching transistor source.
Contact the drain / steam region 4. After the bit line 12 is formed on the semiconductor substrate 1, the interlayer insulating film 10 such as BPSG or PSG is further formed thereon. Then, the interlayer insulating film 10 is selectively etched to form a storage layer.
The contact hole 7 is formed. Then, the interlayer insulating film 10
A polysilicon film is formed on top of the polysilicon film and selectively etched to form a polysilicon storage node electrode 6.
To form. The storage node electrode 6 is also formed in the contact hole 7 and contacts the source / drain region 4 of the switching transistor. The surface of the storage node electrode 6 is oxidized by, for example, heat treatment,
A silicon oxide film 8 having a thickness of about 100 Å serving as a capacitor insulating film is formed. A polysilicon film is further formed so as to cover the capacitor insulating film 8 and serve as a plate electrode 9.

A capacitor for accumulating charges is formed by these electrodes and the capacitor insulating film 8 sandwiched between them. The plate electrode and the like are covered with a protective insulating film (not shown). The dummy word line 13 and the word line 3 formed on the semiconductor substrate act as a gate electrode in each element region surrounded by the element isolation region. The dummy word line 13 is used as the gate electrode of the element isolation transistor, and the word line 3 is used as the gate electrode of the switching transistor. Figure 2
2 shows a cross section of the cell region of the BB ′ portion of the DRAM shown in FIG. 1. The N-type diffusion region 4 in the figure and the dummy word line 13 formed on the region between them form a MOS transistor, and this transistor performs element isolation. The element isolations on the surface shown in this figure are all transistor isolations, and other element isolations are arranged on the further right side of the bit line 12 formed on the right side of the figure, although not shown.
The above is the isolation method in the word line direction, while the isolation in the bit line direction is performed by the thick silicon oxide film 2 which is a field oxide film formed on the surface of the semiconductor substrate as shown in FIG. Done. The bit line 12 is formed on the oxide film 2. The storage node contact hole 7 is arranged between the bit lines 12. P-type polysilicon is used for the gate electrode, that is, the word line in order to ensure the element isolation by the transistor.

In a DRAM having one transistor and one capacitor as one memory cell, a plurality of word lines and bit lines are arranged vertically and horizontally, and one memory cell is attached at each intersection. At this intersection, the word line is connected to the gate of the switching transistor, the bit line is connected to one of the source / drain regions of this transistor, and the other region is of the capacitor storing the charge. Storage
Connected to the electrode. In the above-mentioned conventional example, memory cells are formed at every intersection of the word line and the bit line in every other vertical and horizontal columns. Then, set two adjacent bit line ends to 1
The cell arrangement by the folded bit line system connected to one sense amplifier is used, but in this embodiment, the cell arrangement by the open bit line system in which one sense amplifier is attached to the center of each bit line as shown in FIG. 5 is adopted. It is used, and one memory cell is always attached at the intersection of the word line and the bit line. Therefore, in the conventional example,
Since two word lines are arranged in one cell region, its area is 8F, where F is the width and space of the wiring.
^{Is 2} . On the other hand, in the method of the embodiment, since 1.5 wire lines including the dummy word line are arranged in one cell area, the area becomes 6F ² , The area is significantly reduced. Of course, the folded bit line system can also be used in the present invention. By performing the element isolation by the transistor as in this embodiment, the leak current in the diffusion region is significantly reduced.

FIG. 4 is a sectional view of a semiconductor substrate for explaining the leak current characteristic diagram of the diffusion region of the transistor and the measurement conditions. P-type silicon semiconductor substrate to form N-type diffusion region to 4V voltage addition, gate - Li when the value of G Voltage (V _G) while varying - taking the leakage current on the vertical axis of the characteristic diagram. The leak current is large in the vicinity of zero volt where the depletion layer is formed under the gate electrode. About -1V
The leak current is increasing in the range of + 1V. That is,
In the accumulation state where majority carriers gather on the substrate side or the inversion state where minority carriers gather, the leak current is small. Therefore,
When using a transistor for element isolation, the accumulator
It is advisable to set the gate voltage so that it will be in the operation state.
For example, when a P-type semiconductor is used for the semiconductor substrate, using P-type polysilicon for the gate electrode results in an accumulation state due to the difference in work function even when the gate voltage is the same as when using N-type. Cheap. LOCOS as before
When the cell arrangement by the isolation method and the folded bit line method is used, if one side of the element isolation region is represented by L, the leak current is proportional to 3L, but the transistor isolation is incorporated in one part. Then, it becomes proportional to 2L, and the leak current can be reduced by about 30%. Furthermore, since a large stress is applied to the silicon substrate during the selective oxidation, the corner of the LOCOS oxide film is leaked.
The current is larger than the straight line part. In the present invention, since this corner is eliminated, further reduction of the leak current can be expected.

The word wire 3 and the dummy word wire 13 are
It is used as a gate of a MOS transistor, and in this embodiment, a P ⁺ polysilicon film is used. On the other hand, a P-type silicon semiconductor substrate 1 in which this memory cell is formed
In, for example, a peripheral circuit for refreshing the storage data of the memory cell is formed at regular intervals,
It has a CMOS structure. FIG. 6 shows a sectional view of a peripheral circuit portion of the same substrate as the semiconductor substrate shown in FIG. Since they are formed on the same semiconductor substrate, the MOS transistor of this peripheral circuit is formed at the same time as the memory cell. In a CMOS DRAM, a P-type semiconductor substrate is usually used,
An N well-P well structure is used. The impurity concentration of the semiconductor substrate 1 is about 2 to 3 × 10 ¹⁵ / cm ³ , but the well region is about 1 × 10 ¹⁷ / cm ³ . In the N well region, the source / drain region 4 of the P type diffusion layer is formed to form a PMOS, and in the P well region, the source / drain region 4 of the N type diffusion layer is formed to form the NMOS. Constitute. Since the memory cell portion is an N channel and is formed on the semiconductor substrate, it has the same structure as the NMOS formed in the P well region of the peripheral circuit. However, in this embodiment, the transistor of the memory cell uses the gate of P ⁺ polysilicon, whereas the NMOS of the peripheral circuit uses the gate of N ⁺ polysilicon as in the conventional case. There is.
Therefore, when the impurity is doped into the polysilicon, in the case of P ⁺ polysilicon, the N well region is masked with a photoresist (not shown) or the like, and then the impurity is injected to implant the P ⁺ polysilicon gate. 3, 13, 301 are formed. In the case of N ⁺ polysilicon, the N well region of the cell portion and the peripheral circuit portion is masked and then impurities are implanted to form N
^{+ A} polysilicon gate 300 is formed.

Next, a second embodiment will be described with reference to FIG. The figure shows a cross-sectional view of a cell portion and a peripheral circuit portion of a CMOS structure DRAM formed on one semiconductor substrate. In MOS transistors, polysilicon gate
Besides the gate, a gate having a laminated structure in which a refractory metal or a silicide film is formed on polysilicon is also known. This is advantageous in that the gate resistance can be lowered although the characteristics of the transistor can be determined by polysilicon. In this embodiment, silicide such as W is used.
The low resistance film formed on the polysilicon film is the WSi film.
Other than _2, there are MoSi ₂ , TiSi ₂ , and TaSi ₂ , and Mo and W are used as the refractory metal. Further, a silicide film may be interposed between the polysilicon film and the refractory metal film thereabove. In the device shown in FIG. 7, as in FIGS. 1 and 6, a polysilicon film is formed on each gate oxide film, and impurities are implanted into the polysilicon film to form the P ⁺ polysilicon film 3
1, 131, 311 and N ⁺ polysilicon film 310 are formed. After that, the tungsten silicide films 32, 13 are formed on the polysilicon film by CVD, sputtering, or the like.
2, 320, 321 are deposited. As a method of forming the silicide film, it is also possible to form a tungsten film and then heat-treat it to form a silicide. Further, this heat treatment can be adjusted to form a structure in which a tungsten silicide film is formed between the tungsten film and the polysilicon film.

Next, a third embodiment will be described with reference to FIG. The figure is a schematic plan view showing a part of a DRAM. In the cell arrangement of the DRAM of FIG. 1, since the bit line is formed between the capacitor and the word line, it is necessary to shift the bit line axis with respect to the storage node contact hole. In this embodiment, the bit line is formed on the capacitor as in the conventional example described above. Therefore, the bit line can be easily formed, and the cell can be designed in a simple quadrangle, which facilitates the design. However, it is better to put the capacitor on the top layer.
Since it is possible to increase the area of the cord, in that respect,
The first embodiment is advantageous.

Next, a fourth embodiment will be described with reference to FIG. The figure is a cross-sectional view showing a part of the DRAM. In this embodiment, the bit line is arranged in the middle of the capacitor and word line as in the embodiment of FIG. As shown in the figure, the selective oxide film as shown in FIG. 3 is not formed in the element isolation region formed by the oxide film, but the trench 21 is formed, and the insulating oxide film 22 is embedded therein. The source / drain region 4 is provided between the insulating oxide films 22. Since the LOCOS oxidation method is not used, no bird's beak is generated and the element isolation region can be reduced. Therefore, it is remarkably useful for high integration of the semiconductor memory device.

Next, a fifth embodiment will be described with reference to FIG. Although the stack type capacitors are used in the above-described embodiments, the present invention is not limited to this, and can be applied to those using planar type or trench type capacitors. The figure shows an example of a DRAM using a trench type capacitor, in which the flatness of the substrate surface can be maintained and at the same time a high density of devices can be expected. This is different from the first embodiment shown in FIG. 1 in that the capacitor portion is buried in the trench formed in the semiconductor substrate 1. This drawing is a cross-sectional view and corresponds to the BB ′ cross-sectional view of the semiconductor memory device of FIG.
Since the capacitor is embedded in the semiconductor substrate 1, the height of the cell can be reduced and the area thereof can be reduced. A part of the bit line 12 is buried in the source / drain region 4 to form a contact hole 11 which is in contact with this region, and the other region is formed with a sidewall and a bottom of a trench in which a capacitor is formed. Is formed in. Then, the word line 3 and the dummy word line 13
Are arranged one by one in one cell. An interlayer insulating film 5 and a protective insulating film 14 are provided on the semiconductor substrate 1 so as to cover the bit lines 12 and the word lines 3.

In the conventional cell arrangement, two word lines are arranged in one cell, whereas in the cell of the present invention, one word line and 0.5 dummy word line are used. Since 1.5 bit lines are used in total, considering that one bit line is required as in the conventional case, the cell area is 6F ² where F is the minimum line and space. As a result, the present invention makes it possible to provide a smaller cell area even if the F value is constant, and the effect is very large. In the embodiment of the present invention, the example in which the bit line is formed first is shown, but this method enables the area of the storage node to be increased, and its effect is very large. In the present invention, the dummy word line and the word line are described as being made of the same material, but they may be made of different materials. Further, the semiconductor substrate is not limited to silicon, and any existing semiconductor substrate such as Ge or GaAs can be used. Furthermore, the conductivity type of the semiconductor substrate is not limited to P type, but N type may be used.

[0021]

The present invention remarkably reduces the leak current in the diffusion region by utilizing the transistor isolation,
Further, since the open bit line system can be adopted, the cell area can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view taken along the line BB ′ of FIG.

FIG. 3 is a partial cross-sectional view taken along the line CC ′ of FIG.

FIG. 4 is a characteristic diagram showing a gate potential dependency of a leak current in a diffusion region and a sectional view of a semiconductor substrate including a gate electrode and an impurity diffusion region.

FIG. 5 is a circuit configuration diagram showing an arrangement of cells according to an open bit line system.

FIG. 6 is a cross-sectional view showing a peripheral circuit portion of the same semiconductor substrate as in FIG.

FIG. 7 is a sectional view of a cell portion and a peripheral circuit portion of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a schematic plan view of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 11 is a schematic plan view of a conventional semiconductor memory device.

FIG. 12 is a sectional view of a conventional semiconductor memory device.

FIG. 13 is a circuit configuration diagram showing an arrangement of cells according to a folded bit line system.

[Explanation of symbols]

 1 semiconductor substrate 2 field oxide film 3 word line 31 polysilicon film 32 silicide film 4 source / drain region 5 interlayer insulating film 6 storage node electrode 7 contact hole 8 capacitor insulating film 9 plate Electrode 10 Interlayer insulation film 11 Contact hole 12 Bit line 13 Dummy word line 131 Polysilicon film 132 Silicide film 14 Protective insulation film 21 Trench 22 Insulation oxide film 300 Gate electrode of P well region 301 N well region gate -Pt electrode 310 Polysilicon film in P well region 311 Polysilicon film in N well region 320 Silicide film in P well region 321 Silicide film in N well region

Claims (6)

[Claims] 1. A semiconductor substrate, a memory cell comprising a plurality of switching insulating gate type field effect transistors and a charge storage capacitor formed on the semiconductor substrate, and an element region in which the memory cell is formed. And a source / drain region formed on the semiconductor substrate, above and between these regions with a gate oxide film interposed therebetween. A semiconductor memory device comprising an element isolation transistor including a gate electrode formed as described above. 2. The semiconductor memory device according to claim 1, wherein the gate electrode of the element isolation transistor has means for supplying a voltage of 0 V or less. 3. A P-type silicon semiconductor is used for the semiconductor substrate, and P-type polysilicon or P-type polysilicon and a refractory metal formed thereon are used for the gate electrode of the element isolation transistor. 3. The semiconductor memory device according to claim 1, wherein a film, a silicide film, or a composite film including both of them is used. 4. The semiconductor memory device according to claim 1, wherein the source / drain regions of the switching insulating gate type field effect transistor and the element isolation transistor each have an LDD structure. .. 5. A semiconductor substrate, a word line formed on the semiconductor substrate, a bit line formed on the semiconductor substrate so as to intersect with the word line, and a semiconductor substrate on the semiconductor substrate. A memory cell formed of an insulating gate type field effect transistor and a charge storage capacitor, connected to the bit line and the word line, and a bit line formed on the semiconductor substrate and made of an insulating oxide film. Direction element isolation region, a pair of impurity diffusion regions formed on the semiconductor substrate, and a gate electrode formed on the impurity diffusion regions and between the regions through a gate oxide film. And a device isolation region in the word line direction which is formed by a transistor. 6. The memory cell is always disposed near the intersection of the word line and the bit line, and a pair of the bits are connected to two opposing surfaces of the memory cell so as to lead out in opposite directions. The semiconductor memory device according to claim 5, further comprising a sense amplifier having a line.