JP2004335553A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a measure is devised against the junction leakage of the memory cell in a mixedly pelletized DRAM or FBC memory cell, and to provide a method of manufacturing the device. <P>SOLUTION: The semiconductor device is provided with a memory cell array having a cell array in which a plurality of memory transistors is arranged and a peripheral transistor having a plurality of peripheral transistors. Each memory transistor in the memory cell array is provided with a pair of source-drain diffusion layers formed in a semiconductor substrate, gate electrodes formed on the semiconductor substrate through a gate insulating film as word lines, and an insulating film covering the surface of the semiconductor substrate. The memory transistor is also provided with a contact which is in contact with the source and drain-diffusion layers through the insulating film. The surface of the semiconductor substrate is covered with the insulating film except the contact. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor device, and more particularly, to a cell structure of a DRAM embedded element and an FBC (Floating-Body Cell) memory element and a manufacturing method for realizing the cell structure.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in the field of semiconductor memory, a structure having a charge accumulation region arranged in a cell has been studied in order to achieve high integration.
[0003]
An FBC memory is known as such a semiconductor device. The FBC is an abbreviation of Floating-Body Cell, and was introduced in, for example, a lecture at ISSCC2002 (International Solid-State Circuit Conference 2002: Held in San Francisco from February 3 to 7, 2002). The details are disclosed by the lecture number 9.1 “FBC Cell” (see Non-Patent Document 1).
[0004]
This FBC memory has a cell structure composed of MOS transistors formed in SOI (silicon-on-insulator), and has a charge storage region for storing charges below the transistors.
[0005]
In such an FBC memory, particularly in a structure in which a PN junction is formed at the boundary of a charge storage region, a polysilicon plug or the like should be used as a plug and a wiring on the PN junction in order to reduce junction leakage. And finally a metal plug is formed thereon. However, in the case of miniaturization, a margin in area is small and a margin for contact misalignment cannot be sufficiently secured. For this reason, when misalignment occurs, an irregular shape may occur due to over-etching.
[0006]
FIGS. 18A and 18B show a configuration of an FBC memory exemplified as a semiconductor device known by the present inventor. FIG. 18A is a plan view, and FIG. 18B is a view AA of FIG. It is a line sectional view.
[0007]
In each of FIGS. 18A and 18B, UC indicates a unit cell constituting a MOS transistor. As shown in FIG. 18B, a buried oxide film (insulating layer) 2 is disposed on a supporting substrate (substrate) 1 and a silicon layer 3 is formed thereon to form an SOI structure. Here, the substrate 1 is configured such that an n-type well (1A) is arranged on a P-type silicon support substrate main body 1b. In the silicon layer 3, source / drain regions (diffusion layer regions) 4, 4 and a channel region 5 interposed therebetween are formed. Above the diffusion layer region 4, one of the source line SL and the bit line BL is formed. A gate electrode 6 (word line WL) is formed on the channel region 5 with a gate insulating film 7 interposed therebetween. Diffusion layer 4 (D) (drain) and bit line BL are mutually connected by contact plug CP. The contact plug CP and the source line SL are made of polysilicon. The source line SL is connected to the ground. In the figure, reference numeral 8 denotes an interlayer insulating film (BPSG).
[0008]
A perspective view of the FBC memory is shown in FIG. 19C (for example, see Non-Patent Document 2).
[0009]
For example, as shown in FIG. 19, the FBC memory does not have a charge storage capacity in a cell, and is configured to perform a memory function by storing charges in a charge storage region called a floating body portion.
[0010]
When data is called from this memory, a plurality of cells connected to the memory are selected by a word line WL. The electric charge stored in each cell is read out as Vout from the corresponding bit line BL through the sense amplifier 31 connected thereto. Note that a load capacitance 32 exists on the input side of each sense amplifier 31. Therefore, prior to the reading, the charge of the load capacitance 32 is discharged by the reset transistor 33 that is operated by the read reset signal read reset.
[0011]
At the time of data writing, a write reset signal write reset is given through the Vg2 terminal of the substrate to reset the charge of the floating body portion, and thereafter, data writing is performed through the bit line BL.
[0012]
In the FBC memory having the above-described structure, for example, referring to FIG. 18B, a current flows from the diffusion layer region 4 (drain D) to the diffusion layer region (source S) via the channel region 5. When flowing, hot holes are generated in the channel region 5. The hot holes are accumulated in the channel region 5. That is, a memory operation is performed by setting the channel region 5 as a capacitor for storing data (holes), that is, a charge storage region. That is, the charge storage region is arranged below the gate (word line WL) in the unit cell UC which is a MOS transistor. The FBC memory has the advantage that the circuit area can be significantly reduced and high integration can be achieved.
[0013]
However, the data storage time of the FBC is shorter than that of a capacitor in a conventional DRAM. In order to extend the accumulation time, it is conceivable to reduce the junction leak in the diffusion layer region 4. At the same time, since it is necessary to generate hot holes in the charge storage region, it is conceivable to lower the resistance of the source line SL and the bit line BL connected to the ground.
[0014]
For this reason, although the source line SL and the bit line BL contact plug CP, each made of polysilicon, are connected to the supporting substrate via salicide, respectively, the wiring resistance is reduced, but an example known by the present inventors is provided. Are shown in FIGS. 20A and 20B. These two figures are cross-sectional views of different portions of one semiconductor device. In particular, FIG. 20A shows an FBC cell portion, and FIG. 20B shows an FBC peripheral circuit portion. As shown in these figures, a salicide process is applied to an electrode made of polysilicon to form a salicide portion 11, thereby realizing a reduction in wiring resistance. In the figure, 12, 13 and 14 are gate side walls.
[0015]
However, according to such a configuration, as is clear from FIG. 20A, the surface of the silicon layer 3 is directly salicidized. For this reason, an interface reaction or a crystal defect portion occurs at the joint portion, resulting in a structure having a large amount of junction leak. As a result, a problem arises in the ability to accumulate charges that are important for the memory operation.
[0016]
Also, consider a semiconductor device using bulk silicon. For example, Japanese Patent Application Laid-Open No. 3-171768 discloses a memory cell using bulk silicon. Also in this case, it can be seen that similar problems are involved in reducing the junction leak.
[0017]
[Non-patent document 1]
ISSCC 2002 / SESSION 9 / DRAM AND FERROELECTRIC MEMORIES / 9.1 Memory Design Using One Transistor Gain Cell on SOI / TAKASHIO Ohsawa et al.
[Non-patent document 2]
IEEE TRANSACTION ON ELECTRON DEVICES, VOL. 37, MAY, 1990, p1373-1382
[Patent Document 1]
JP-A-3-171768
[Problems to be solved by the invention]
As described above, conventionally, there has been no memory structure using a PN junction in a charge storage region, such as FBC, having an appropriate structure and process.
[0019]
SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same in which, for example, in an embedded DRAM or FBC cell, a junction leak in a contact portion in a memory cell is prevented. is there.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, an embodiment of the present invention includes: a memory cell array unit having a cell array in which a plurality of memory transistors are arranged; and a peripheral transistor unit having a plurality of peripheral transistors. Each of the memory transistors includes a pair of source / drain diffusion layers formed in a semiconductor substrate, a gate electrode as a word line formed on the semiconductor substrate via a gate insulating film, and a surface of the semiconductor substrate. An insulating film to cover, and a contact penetrating through the insulating film and contacting each of the source / drain diffusion layers, and a surface of the surface of the semiconductor substrate other than the contact is covered with the insulating film. A semiconductor device is provided.
[0021]
In order to achieve the above object, according to an embodiment of the present invention, a polysilicon gate electrode is formed via a gate insulating film on each of a memory cell array portion forming region and a peripheral transistor portion forming region on a semiconductor substrate. A first step of forming a pair of source / drain regions on both sides of the gate electrode, and forming at least an insulating film and a nitride film on an upper surface and side walls of each of the gate electrodes and on the semiconductor substrate. A second step of depositing, and burying an interlayer insulating film material entirely, polishing this until the nitride film on the top of each of the gate electrodes is exposed, and subsequently polishing the interlayer insulating film material in the peripheral transistor portion forming region A third step of removing only the nitride film using the interlayer insulating film material as a mask until the insulating film is exposed; and Forming a hole through the insulating film and the nitride film above the pair of source / drain regions and reaching the surface of the semiconductor substrate, and forming a polysilicon plug in the hole. A sixth step of removing the insulating film at the top of the gate in the memory cell array part forming region, the top of the gate in the peripheral transistor part forming region, and the insulating film in the source / drain region; And a seventh step of saliciding the top of the gate electrode and the top of the polysilicon plug in the portion forming region, the top of the gate electrode and the source / drain region in the peripheral transistor portion forming region. To provide a method for manufacturing a semiconductor device.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
Embodiment 1 FIG.
1A and 1B show a configuration of an FBC memory exemplified as a semiconductor device according to a first embodiment of the present invention. FIG. 1A shows a memory portion (memory cell array portion), and FIG. 1B shows a peripheral circuit portion ( (Peripheral transistor section). Although shown in FIGS. 1A and 1B, the same elements as those shown in FIGS. 20A and 20B are denoted by the same reference numerals, and detailed description is omitted. This is the same in other drawings described below.
[0024]
In the memory section, as shown in FIG. 1A, the gate side walls 12 and 13 are covered on the silicon substrate and are not salicidized. On the other hand, the source / drain regions 4 (S) and 4 (D) are in contact with the polysilicon plug 21. The upper portions of these polysilicon plugs are salicided. However, since the polycrystalline portion (polysilicon plug 21) is salicided here, there is no direct influence on the silicon substrate to increase the junction leak.
[0025]
Therefore, according to the configurations shown in FIGS. 1A and 1B, it is possible to simultaneously realize the structure of the logic transistor in the peripheral circuit portion, the countermeasure against the leak in the cell in the memory portion, and the salicide on the gate. .
[0026]
Embodiment 2. FIG.
FIG. 2 shows a configuration of a memory using bulk silicon exemplified as a semiconductor device according to a second embodiment of the present invention. FIG. 2A shows a memory portion, and FIG. 2B shows a peripheral circuit portion. It is shown.
[0027]
FIG. 2 differs from FIG. 1 in that the configuration of FIG. 1 has a three-layer SOI structure of a support substrate 1, a buried oxide film layer 2, and a silicon single crystal layer 3 as a substrate, whereas the configuration of FIG. Is a one-layer structure of the bulk silicon layer 3, and the other structures are the same.
[0028]
Also in the case of the second embodiment, as in the first embodiment, it is possible to simultaneously realize the structure of the logic transistor in the peripheral circuit portion, the countermeasure for leak in the cell of the memory portion, and the salicide on the gate.
[0029]
Embodiment 3 FIG.
3A and 3B show a configuration of a trench DRAM exemplified as a semiconductor device according to a third embodiment of the present invention. FIG. 3A shows a memory portion, and FIG. 3B shows a peripheral circuit portion. .
[0030]
FIG. 3 differs from FIG. 1 in that the source line SL is connected to the X'fer contact 25 and the trench capacitor 26, and the other configuration is the same.
[0031]
That is, also in the configuration of FIG. 3A, it is possible to simultaneously realize the structure of the logic transistor in the peripheral circuit portion, the countermeasure for leak in the cell in the memory portion, and the salicide on the gate.
[0032]
Embodiment 4 FIG.
4 to 17 are process cross-sectional views for explaining a process of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. In these drawings, (1A) to (14A) denote manufacturing processes of a memory unit. , (1B) to (14B) respectively show the manufacturing process of the peripheral circuit portion.
[0033]
As can be seen from FIGS. 4A and 4B, after performing STI (Shallow Trench Isolation) on the SOI substrate including the support substrate 1, the buried oxide film layer 2, and the silicon layer 3 by the element isolation film 25. Then, a gate electrode 6 (word line WL) is formed of polysilicon. Thereafter, ion implantation is performed using the gate electrode 6 as a mask, and then, diffusion is performed to form source / drain regions (diffusion layer regions) 4.
[0034]
Subsequently, as can be seen from FIGS. 5 (2A) and (2B), in order to further form the gate electrodes 13 and 14 outside the gate side wall 12, TEOS which is a planarization insulating material is set to 200 °, and the SiN film is set to 700 °. Are respectively deposited. Thus, gate sidewalls 13 and 14 are formed via gate sidewall (oxide film) 12. Simultaneously, ions are implanted into a deep region into the source and drain regions of the memory portion using the gate 6 and the gate side walls 12, 13, and 14 as a mask.
[0035]
Thereafter, as can be seen from FIGS. 6 (3A) and (3B), the gate step is filled with the interlayer insulating film (BPSG) 8. Subsequently, the BPSG 8 is shaved by CMP (chemical mechanical polishing) using the gate side wall (SiN film) 14 as a stopper until the SiN film 14 comes out of the face. In this case, it is needless to say that the SiN film 14 needs to be set to a sufficient thickness as a CMP stopper.
[0036]
Subsequently, as can be seen from FIGS. 7 (4A) and 7 (4B), only the memory portion of (4A) is protected with a resist, and the BPSG of the peripheral circuit portion of (4B) is removed by wet etching. Also in this case, the thickness of the SiN film 14 of (4B) is set to such a degree as to sufficiently function as an etching stopper, and it is required that there is no defect such as a pinhole.
[0037]
Next, as can be seen from FIGS. 8 (5A) and (5B), the SiN film 14 of the memory section of (5A) and the SiN film 14 of the peripheral circuit section of (5B) are subjected to the RIE (reactive ion etching) method. Etching. At this time, the etching condition of the SiN film is set to a condition that does not remove SiO ₂ . As a result, as shown in FIGS. 8 (5A) and (5B), the etching is stopped at the portion where the surface of the TEOS 13 is exposed. As a result, as shown in FIG. 8 (5B), in the peripheral circuit portion, the SiN film 14 is removed both on the gate 6 and on the silicon layer 3. On the other hand, in the memory section, as shown in FIG. 8 (5A), only the portion above the gate 6 has the form in which the SiN film 14 is removed.
[0038]
Subsequently, as can be seen from FIGS. 9 (6A) and (6B), high concentration source / drain regions 4 (D) and 4 (S) are formed by implantation and diffusion of impurities.
[0039]
Next, as can be seen from FIGS. 10 (7A) and (7B), a contact hole 26 for a source line contact is opened in the memory section of (7A).
[0040]
Next, as can be seen from FIGS. 11 (8A) and (8B), contact holes 27 for bit line contacts are formed.
[0041]
Subsequently, as can be seen from FIGS. 12 (9A) and (9B), polysilicons 21 (S) and 21 (D) are buried in the respective contact holes 26 and 27.
[0042]
Subsequently, as can be seen from FIGS. 13A and 13B, the gate sidewalls 12 and 13 are formed on the gate 6 of (10A), on the gate 6 of (10B), and on the silicon layer 3 (substrate). Is removed by RIE and wet etching. Thereafter, a salicide portion 11 of Co is formed by a salicide method. In this case, the salicide 11 is formed on the upper portion of the gate 6 and the upper portions of the polysilicons 21 (S) and 21 (D) in the memory portion of (10A), and in the peripheral circuit portion of (10B). And on the silicon layer (substrate) 3. That is, in the memory section of (10A), salicide is not formed on the silicon substrate.
[0043]
Next, as can be seen from FIGS. 14 (11A) and (11B), BPSG 8 is deposited on the entire device and flattened by the CMP method.
[0044]
Subsequently, as can be seen from FIGS. 15 (12A) and (12B), in the memory section of (12A), a hole (8A) opening in the salicide 11 (D) is opened by RIE.
[0045]
Next, as can be seen from FIGS. 16 (13A) and (13B), a hole (8B) opening in the salicide 11 of the peripheral circuit portion of (13B) is formed.
[0046]
Next, as shown in FIGS. 17 (14A) and (14B), W (tungsten) is buried in the holes (8A) and (8B) formed as described above, and the contact plugs CP and CP are formed by CMP. A CP is formed.
[0047]
Through the processes described above, in the logic transistor structure of the peripheral circuit portion, salicide 11 is formed on the gate and on the contact portion of the substrate, while, in the memory portion, salicide 11 is formed on the gate and on the substrate. The salicide 11 is formed on the standing polysilicon, and a structure that is not salicidized on the silicon substrate can be realized. As a result, in the memory section, low-resistance gate wiring and junction leakage reduction can be achieved at the same time, and in the peripheral circuit section, a logic circuit having a normal salicide structure can be formed.
[0048]
In the fourth embodiment shown in FIG. 4, the manufacturing method for the structure shown in the first embodiment has been exemplified. However, this step can be similarly applied to the manufacturing of the second and third embodiments. Yes, the same effect can be obtained.
[0049]
【The invention's effect】
As described above, according to the present invention, for example, in an embedded DRAM or FBC cell, the resistance of the word line of the memory cell is simultaneously reduced while reducing the junction leak in the memory cell and improving the charge storage performance. On the other hand, a transistor having a normal salicide structure can be arranged in a mixed logic circuit, so that there is an effect that a high-performance semiconductor device can be realized.
[Brief description of the drawings]
FIG. 1 is a sectional view of a memory cell portion (memory cell array portion) (A) and a peripheral circuit portion (peripheral transistor portion) (B) of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a memory cell portion (A) and a peripheral circuit portion (B) of a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a sectional view of a memory cell portion (A) and a peripheral circuit portion (B) of a semiconductor device according to a third embodiment of the present invention.
FIG. 4 is a part of a process cross-sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 5 is a part of a process sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 6 is a part of a process sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 7 is a part of a process sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 8 is a part of a process sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 9 is a part of a process sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 10 is a part of a process cross-sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 11 is a part of a process cross-sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 12 is a part of a process sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 13 is a part of a process cross-sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 14 is a part of a process cross-sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 15 is a part of a process sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 16 is a part of a process cross-sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
FIG. 17 is a part of a process cross-sectional view for illustrating the method for manufacturing the semiconductor device shown as the fourth embodiment of the present invention.
18A and 18B are a plan view and a cross-sectional view of a conventional semiconductor device.
FIG. 19 is a perspective view of a conventional semiconductor device.
FIG. 20 is a cross-sectional view of a memory cell portion (A) and a peripheral circuit portion (B) of a conventional semiconductor device.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 support substrate 2 buried oxide film 3 silicon layer 4 source / drain diffusion layer 6 gate electrode 11 salicide 21 polysilicon plug 13, 14 gate side wall 25 X'fer contact 26 trench capacitor UC unit cell WL word line SL source line BL bit line

Claims (6)

A memory cell array portion having a cell array in which a plurality of memory transistors are arranged, and a peripheral transistor portion having a plurality of peripheral transistors,
Each of the memory transistors in the memory cell array section has a pair of source / drain diffusion layers formed in a semiconductor substrate, a gate electrode as a word line formed on the semiconductor substrate via a gate insulating film, and An insulating film covering the surface of the semiconductor substrate; and a contact penetrating the insulating film and contacting each of the source / drain diffusion layers. A surface of the semiconductor substrate other than the contact is an insulating film. A semiconductor device characterized by being covered with: 2. The semiconductor device according to claim 1, wherein an upper surface of the gate electrode serving as the word line is salicide. Each of the peripheral transistors in the peripheral transistor portion includes a pair of source / drain diffusion layers formed in the semiconductor substrate, and a gate electrode formed on the semiconductor substrate via a gate insulating film, 3. The semiconductor device according to claim 1, wherein a surface of the pair of source / drain diffusion layers on a surface of the semiconductor substrate and an upper surface of the gate electrode are salicide. 4. The semiconductor device according to claim 1, wherein an SOI substrate is used as said semiconductor substrate. The trench capacitor formed in the semiconductor substrate is connected to the contact that contacts one of the pair of source / drain diffusion layers in each of the memory transistors in the memory cell array section. 4. The semiconductor device according to any one of 1 to 3. A polysilicon gate electrode is formed in each of the memory cell array portion forming region and the peripheral transistor portion forming region of the semiconductor substrate with a gate insulating film interposed therebetween, and a pair of source / drain is formed on both sides of the gate electrode. A first step of forming a region;
A second step of depositing at least an insulating film and a nitride film on the upper surface and side walls of each of the gate electrodes and on the semiconductor substrate;
A third step of burying an interlayer insulating film material entirely and polishing it until the nitride film at the top of each gate electrode is exposed, and subsequently removing only the interlayer insulating film material in the peripheral transistor portion forming region When,
A fourth step of removing the nitride film using the interlayer insulating film material as a mask until the insulating film is exposed;
An opening is formed in the insulating film and the nitride film above the pair of source / drain regions in the memory cell array portion forming region to penetrate them and reach the surface of the semiconductor substrate, and a polysilicon plug is formed in the opening. A fifth step of forming
A sixth step of removing the insulating film at the top of the gate in the memory cell array portion forming region, the top of the gate in the peripheral transistor portion forming region, and the insulating film in the source / drain region;
A seventh step of saliciding the top of the gate electrode and the top of the polysilicon plug in the memory cell array formation region, the top of the gate electrode and the source / drain region in the peripheral transistor formation region,
A method for manufacturing a semiconductor device, comprising:

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