JPS62200758A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce an area occupied by a memory cell while keeping the capacity of an MOS capacitor large sufficiently and thereby to enable the attainment of a memory device of high density, by utilizing the lateral side of an insular region as the MOS capacitor of the memory cell, and by forming a gate electrode from the upper side of a substrate down to the lateral side. CONSTITUTION:A capacitor having a capacitor electrode 16 buried in a groove of an element-isolating region is provided except for the upper side of the groove, a gate electrode 18 of MOS-type FET is provided from the upper side of a substrate in an element region down to the lateral side of the groove, and a reverse conductivity type layer 20 connecting to a bit wire 21 is provided adjacently to the gate electrode 18 on the upper side of the substrate. For instance, grid-shaped grooves are formed in a P-type silicon substrate 11 to form a plurality of insular regions 13, and P-type layers 14 for preventing inversion are formed. Next, first gate oxide films 15 are formed, and phosphorus-doped polycrystalline silicon is deposited to form capacitor electrodes 16. Then after second-layer polycrystalline silicon doped with phosphorus through second gate oxide films 17 is deposited to form gate electrodes 18, the whole surface is covered with an oxide film 19, contact holes are opened, and n<+> layers 20 to operate as drains of MOS transistors and an Al wiring 21 are formed.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and relates to a memory device having a one-transistor/one-capacitor memory cell structure in which information is retained by charges accumulated in a MOS capacitor. 6 [Technical background of the invention and its problems] Conventional dynamic RAM (hereinafter referred to as d-RAM).

) memory cell is composed of a MOS capacitor that holds information by multiplying charges by V8, and a switch 1-transistor that exchanges the charges with an external circuit. For example, as shown in FIG. 2, the structure includes a gate insulating film on a semiconductor substrate 21.

1F silicon gate W installed via 22! very,
23 and a second F silicon gate electrode 2 installed through a gate insulating film 24.
5, and a MOS transistor constituted by a high concentration impurity region 26 of a conductivity type opposite to that of the substrate. 27 is a thick insulating film for element isolation.

The amount of charge is determined by the thickness and area of the gate insulating film 22 in the MOS capacitor section. When reading information,
The magnitude of a signal is determined by the amount of accumulated charge, so in order to increase the amount of accumulated charge, gate insulation 1[12
By the way, the thickness of the gate insulating film 22 cannot be affected too much in terms of reliability, so it is necessary to increase the area. This has been a major obstacle in reducing the area and increasing density.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to obtain a semiconductor memory device that enables high density by reducing the area occupied by memory cells while maintaining a sufficiently large capacity of a MOS capacitor. It is said that

[Summary of the invention]

In the present invention, a plurality of island regions are formed in an array by carving grooves in the surface of a semiconductor substrate, and memory cells are integrated in these island regions. in this case.

A switching transistor is present on the top and side surfaces of the memory cell, and a MOS capacitor is formed except on the top of the trench.

(Effects of the Invention) According to the present invention, since the side surface of the island region is utilized as a MOS capacitor of a memory cell, a large storage capacity can be obtained while keeping the area occupied by the memory cell to a minimum. , a high-density storage device can be realized.

Further, since the gate electrode is formed from the top surface to the side surface of the substrate, a sufficient channel length can be obtained, and short channel effects can be prevented.

[Embodiments of the invention]

The present invention will be explained in detail below. FIG. 1(a) is a plan view showing a MOS dynamic RAM of one embodiment, and (
b) (C) is a cross-sectional view showing the manufacturing process of the AA' cross section.

First, a mask 1 such as S:0□ is placed on a P-type silicon substrate 11.
2, and a plurality of rectangular island regions 13 (13□, 13
．． ), a layer 1 of P-type impurity for preventing inversion for element isolation is applied to the bottom of the groove between each zero-order island region 13 forming an array.
4 is formed by ion implantation or the like. and.

A first gate oxide film 15 of a predetermined thickness is formed on the upper surface and side surfaces of each island region by high-temperature thermal oxidation, and after depositing the first M phosphorus-doped polycrystalline silicon, a planarization process is used.
By leaving polycrystalline silicon in the groove, MO
An S capacitor electrode 16 is formed. (FIG. 1b), and then the second gate oxide film doped with phosphorus via the second gate oxide film 17.
Depositing F polycrystalline silicon and patterning it,
Gate electrode 18 (181, 18,
...) is formed.

After that, the entire surface is covered with a CVD oxide film 19, and a contact hole is made, which will become the drain of the MOS transistor.
Ten layers 20 (20,, 20, . . . ) are formed by ion implantation. Then, Affi wiring 21 is formed.

In this way, each island region 12 has an IMOS transistor.

The gate electrode 13 of the 0M0S transistor, in which a memory cell each consisting of one MOS capacitor is formed, is arranged continuously in the vertical direction, and serves as a word line. On the other hand, the drains of the MOS transistors are commonly connected in the horizontal direction by an l wiring 21, which becomes a bit line.

According to this embodiment, by processing the semiconductor substrate surface and effectively utilizing all the side surfaces of the obtained island region, MO
The S capacitor can be fabricated virtually without occupying one surface area, and therefore high-density non-stacking of the MOS dynamic RAH can be achieved with high reliability.

Note that the present invention is not limited to the above embodiments. For example, the gate oxide film is not limited to a thermal oxide film, but other oxide films or nitride films may be used, and 1MO , other metals or metal silicides may also be used.

Alternatively, an n-type semiconductor substrate can also be used. In addition, various modifications can be made without departing from the spirit of the present invention.

[Brief explanation of drawings]

FIG. 1 shows a MOS dynamic RAM according to an embodiment of the present invention.
FIG. 2 is a diagram showing the memory cell structure of a conventional MOS dynamic RAM. In the figure, 11...P-type silicon substrate, 13 (131, 132,
...)...Island area. 14... Element isolation oxide film, 16... MOS capacitor electrode. 17...Second gate oxide film. 18 (181,1g, ・) ・MOS transistor gate f! ! very. 19...CVDM film. 20(201,20,,-)--Drain n ten layers,
2l-AQ wiring. Agent Patent Attorney Noriyuki Ken Yudo Takehana Kikuo TGL (Gen 2 Figure 1 CC) Figure 1 Figure 2

Claims (1)

[Claims] A semiconductor memory device in which a capacitor electrode is buried in a trench in an element isolation region, the capacitor is provided except for the upper part of the trench, and a MOS type FE is provided from the top surface of the substrate in the element region to the side surface of the trench.
1. A semiconductor memory device comprising: a T gate electrode; and an opposite conductivity type layer adjacent to the gate electrode and connecting a bit line on the upper surface of the substrate.