JP2503689B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a highly integrated structure of a semiconductor memory device capable of random input / output of stored information.

[Conventional technology]

In recent years, the demand for semiconductor memory devices has rapidly expanded due to the remarkable spread of information devices such as computers. Also, functionally, it has a large storage capacity,
What is required is a device that can operate at high speed. Along with this, technological developments relating to high integration, high-speed response or high reliability of semiconductor memory devices are being advanced.

Among semiconductor memory devices, DRAM (Dynamic Random Access Memory) is used for those that can input and output memory information at random.
There is.

Generally, a DRAM is composed of a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits necessary for input / output with the outside. FIG. 5 is a block system diagram showing the configuration of a general DRAM. In FIG. 5, DRAM
Reference numeral 50 denotes a memory cell array 51 for accumulating a data signal of storage information, a row-and-column address buffer 52 for externally receiving an address signal for selecting a memory cell forming a unit storage circuit, and decoding the address signal. Row decoder 53 and column decoder 54 for designating a memory cell, a sense refresh amplifier 55 for amplifying and reading a signal accumulated in the designated memory cell, and a data-in buffer 56 for data input / output. And a data out buffer 57 and a clock generator 58 for generating a clock signal. Also,
In FIG. 5, A0 to A9 are address input terminals.

A memory cell array 51 occupying a large area on a semiconductor chip is formed by arranging a plurality of memory cells for accumulating unit storage information in a matrix. FIG. 6 is a circuit diagram showing an equivalent circuit for 4 bits of the memory cells that form the memory cell array 51. The illustrated memory cell is a so-called one-transistor / one-capacitor type memory cell including one MOS (Metal Oxide Semiconductor) transistor and one capacitive element connected thereto. Since this type of memory cell has a simple structure, it is easy to improve the degree of integration of the memory cell array, and is widely used for large capacity DRAM.

When the memory size is reduced due to higher integration of DRAM, the area for capacitors is also reduced accordingly. However, from the viewpoints of stable operation and reliability of DRAM as a memory device, the amount of electric charge stored in a 1-bit memory cell must be maintained at a substantially constant level even if it is highly integrated. The area needs to be increased in some way. Therefore, it has been attempted to increase the effective area of the capacitor by making the structure of the capacitor three-dimensional. For example, FIGS. 3 and 4 are sectional views of a memory cell having a capacitor having a three-dimensional structure. Since both sides of the portion of the lower electrode of the capacitor perpendicular to the substrate can be utilized as the capacitor area, the effective capacitor area can be increased.

In FIGS. 3, 4, and 6, 1 is a semiconductor substrate,
2 is an element isolation region, 3 is a gate oxide film, 4a and 4b are gate electrodes, 5 is a missing number, 5a and 6b are n ^- diffusion layers, 7 is a missing number, 8 is an oxide film, 9a and 9b are n ⁺ diffusion layers, 10 is a nitride layer, 11-14 are missing numbers, 1
5, 17 is a conductive film, 16 is a dielectric film, 18 is an insulating film, 19 is a conductive layer,
20 is a conductive film which is a bit line, 21 is a MOS transistor, 22
Is a capacitor, and 23 is a corner.

As shown in FIGS. 3, 4, and 6, the memory cell includes one access transistor 21 and one capacitor 22.
It consists of and. The memory cell is surrounded by the element isolation region 2 formed on the surface of the semiconductor substrate 1 and is insulated and isolated from the adjacent memory cell. The access transistor 21 includes impurity regions 6a, 9a and 6b, 9b formed on the surface of the semiconductor substrate 1 and the impurity regions 6a, 9a.
It is located between a and 6b, 9b, and is composed of a gate electrode 4a formed via a thin gate oxide film 3. The capacitor 22 forms a laminated film of a nitride film and an oxide film between a lower electrode 15 and an upper electrode 17 made of a conductive material such as polycrystalline silicon, or a dielectric layer made of a dielectric material such as a tantalum oxide film. 16 are laminated and the lower electrode 15 is connected to the source or drain regions 6b and 9b of the access transistor 21. The bit line 20 is on the interlayer film made of the insulating film 18, and is connected to the source or drain regions 6a and 9a of the access transistor 21 directly or via the conductive layer 19.

[Problems to be Solved by the Invention]

In the conventional memory cell, the cross-sectional shape of the lower electrode 15 with respect to the upper electrode 17 in FIGS.
Has 23. Since the angles of the corners 23 are not defined, the angles of the corners 23 remain the same as the shape processed in the previous step. For example, as shown in FIG.
The angle is in degrees, or as shown in FIG. When both surfaces of a conductive film are used as capacitors as in this memory cell example, the corners of the conductive film are 90 degrees and 90 degrees or obtuse angles and acute angles. In such a conventional corner portion, for example, the capacitor having the three-dimensional structure as described above has at least one acute angle. Therefore, the electric field is concentrated on the acute angle portion, and the dielectric film formed on that portion is thinly formed on that portion, so that there is a problem that reliability such as breakdown voltage is deteriorated on that portion.

The present invention has been made in view of such a point,
The purpose is to obtain a semiconductor memory device having a corner portion in which reliability such as breakdown voltage does not deteriorate.

[Means for solving the problem]

In order to achieve such an object, the present invention provides a semiconductor substrate (1) and a first insulating film (3, 2) on the surface of the semiconductor substrate.
A gate electrode (4a) and a wiring layer (4b) connected to the gate electrode, and a source region (6b, 9b) and a drain region (6a, 6a, formed on both sides of the gate electrode of the semiconductor substrate. 9a), a second insulating film (8) respectively formed on the gate electrode and the wiring layer connected to the gate electrode, and connected to one of the source region and the drain region and extending on the second insulating film. Formed on the surface of the lower electrode (15), which is composed of the lower conductive layer that is formed there, and the upper conductive layer that extends from near the outside of the lower conductive layer in the direction perpendicular to the semiconductor substrate, and on the surface of the lower electrode. Dielectric film (1
6) and the upper electrode (17) formed on the surface of the dielectric film, and the tip of the upper conductive layer of the lower electrode is formed on a smooth surface.

[Action]

In the semiconductor memory device according to the present invention, the electric field strength at the corner where the lower electrode and the upper electrode are in contact with each other via the dielectric film is reduced, and the reliability of the capacitor is improved.

〔Example〕

1 and 2 are sectional views showing an embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device shown in FIGS. 1 and 2 has the same structure as the semiconductor memory device shown in FIGS. 3 and 4 except for the shape of the corner portion 23. The same or corresponding parts as those in FIG. 4 are designated by the same reference numerals.

In the semiconductor memory device of FIG. 1, the corners of the capacitor lower electrode 15 are dropped to form a taper shape.
Only the corners 23 above the degree are used. Further, in FIG. 2, the corner 23 is rounded. By doing so, the electric field is not concentrated in the corner portion 23, and the reliability such as breakdown voltage can be improved.

In this embodiment, two typical examples are shown, but it goes without saying that the corners may be more polygonal or elliptical.

〔The invention's effect〕

As described above, according to the present invention, since the tip end portion of the upper conductive layer of the lower electrode is formed on the smooth surface, it is possible to eliminate the concentration of the electric field at the corner portion, so that the reliability of the breakdown voltage is high. There is an effect that a capacitor, and by extension, a highly reliable semiconductor memory device can be obtained.

[Brief description of drawings]

1 and 2 are sectional views showing a memory cell in an embodiment of a semiconductor memory device according to the present invention, and FIGS. 3 and 4 are sectional views showing a memory cell in a conventional semiconductor memory device, and FIG. Is a block system diagram showing a general semiconductor memory device (DRAM), and FIG. 6 is a circuit diagram showing an equivalent circuit for 4 bits of memory cells. 1 ... Semiconductor substrate, 2 ... Element isolation region, 3 ... Gate oxide film, 4a, 4b ... Gate electrode, 6a, 6b ... n ^- diffusion layer, 8
...... Oxide film, 9a, 9b …… n ⁺ diffusion layer, 1 …… Nitride film, 15,1
7,20 ... Conductive film, 16 ... Dielectric film, 18 ... Insulating film, 19 ...
Conductive layer, 21 …… MOS transistor, 22 …… Capacitor, 2
3 ... Corner.

Claims (1)

(57) [Claims] 1. A semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate via a first insulating film, and a wiring layer connected to the gate electrode, and on both sides of the gate electrode of the semiconductor substrate. A source region and a drain region formed, a second insulating film respectively formed on the gate electrode and a wiring layer connected to the gate electrode, and connected to one of the source region and the drain region,
A lower conductive layer formed to extend on the second insulating film, and a lower electrode formed of an upper conductive layer extending in the direction perpendicular to the semiconductor substrate from outside the lower conductive layer. A dielectric film formed on the surface of the lower electrode and an upper electrode formed on the surface of the dielectric film, and the tip of the upper conductive layer of the lower electrode is formed on a smooth surface. A semiconductor memory device characterized by: