JPS59191374A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a leakage phenomenon by forming a charge storage section into a small hole electrically isolated from a semiconductor substrate and removing an unnecessary depletion region from a capacitance section in the capacitance section of a memory cell. CONSTITUTION:Small holes 3 are formed on a p type semiconductor substrate 1, and the capacitance sections C1, C2 of memory cells are constituted. An insulating film 6 electrically isolates the semiconductor substrate 1 and a first capacitance plate 9. A capacitance insulating film 8 is positioned at the intermediate section of the first capacitance plate 9 and a second capacitance plate 12, and stores information charges. An insulating film 10 isolates both the first capacitance plate 9 and the substrate 1 and the second capacitance plate 12. A connecting hole 11 connects the plate 12 and a semiconductor region. An insulating film 14 isolates the capacitance sections of adjacent memory cells and the plate 12 and word lines 15. n<+> semiconductor regions 16 constitute a MISFETQ1. Insulating films 17 isolate the word lines 15 and a bit line 19. A connecting hole 18 connects the semiconductor region 16 and the bit line 19.

Description

Detailed Description of the Invention [Technical Field 5] The present invention relates to a dynamic random access memory [hereinafter referred to as DRAM (Dynamic Random Access Memory)].
The present invention relates to a semiconductor integrated/circuit device equipped with an "Access Memory".

[Background technology]

Semiconductor integrated circuit devices equipped with DRAMs are becoming highly integrated in order to increase the amount of information they must store and to improve their operating time. In order to achieve higher integration, it is necessary to reduce the size of peripheral circuits that make up DRAMs, such as semiconductor elements such as address selection circuits, readout circuits, @write circuits, etc., as well as the storage elements that hold information. be. This storage element is required to have a certain predetermined capacitance value in order to ensure a signal amount and perform read and write operations correctly. For example, if the capacitance value is small, malfunctions or shaft errors may occur due to the influence of unnecessary minority gears generated by alpha rays (hereinafter referred to as α rays).

Therefore, a semiconductor integrated circuit device equipped with a DRAM using pore technology that utilizes not only the entire surface of the semiconductor substrate that forms memory elements, etc., but also the internal direction has been proposed (Japanese Patent Application No. 50-53883). .

A memory element based on this pore technology consists of a pore (also called a U-groove) provided extending from the entire surface of a semiconductor substrate inward, and an insulating film provided along the pore. An insulated gate field effect transistor (hereinafter referred to as MI) is provided between a capacitive part formed by a capacitive electrode provided to cover the upper part of an insulating film, and a bit line for transmitting information and the capacitive part. ing.

However, as a result of the inventor's experiments and studies, such D
The following problems have been identified regarding semiconductor integrated circuit devices equipped with RAM.

The first problem is that the part where the capacitive part accumulates the charge that becomes information is inside the semiconductor substrate in the vicinity of the pore, and as the distance between adjacent memory elements approaches due to high integration, the pore As a result, the respective depletion regions extending into the semiconductor substrate from the junction with the semiconductor substrate are combined, and when they are combined, if there is a potential difference between the respective capacitance parts at °C, a high potential σ) is applied to the capacitance part to a low potential. Transfer of potential to the capacitive part of, Tokoura,
A leak phenomenon occurs. This tends to cause malfunctions in the information read operation and reduces the reliability of the DRAM, making it impossible to increase the degree of integration of a semiconductor integrated circuit device including the DRAM.

The second problem is that three-dimensional capacitors created using pore technology concentrate charges within the semiconductor substrate to a greater degree than conventional planar capacitors, so they may be generated within the semiconductor substrate. The influence of unnecessary minority carriers generated by α rays also increases. That is, as the depth of the pores extending from the surface of the semiconductor substrate to the inside thereof increases, the influence of the minority carriers increases. It is known that unnecessary minority carriers generated by α rays reverse the charge accumulated in the capacitive part of the storage element. That is, the first
Similar to the problem described above, malfunctions are likely to occur in the information read operation, reducing the reliability of the DRAM.

The third problem is that the size of the pores on the entire surface of the semiconductor substrate (hereinafter simply referred to as pore size) is about 1 [μm] or more at the technological level for commercialization, which is not the case for ordinary capacitive electrodes. Since the pores cannot be completely filled with the thickness of the material and the insulating film material, undulations occur on the upper surface of the pores. This tends to cause irregularities in the wiring width, wiring length, etc. of word lines and bit lines that will be formed on top of the word lines and bit lines, and they also tend to cause disconnections. Unfavorable due to the electrical characteristics of semiconductor integrated circuit devices.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the first problem and prevent leakage between adjacent memory elements of a semiconductor integrated circuit device equipped with a DRAM using pore technology.

Another object of the present invention is to eliminate the second problem and reduce the influence of unnecessary minority carriers caused by α rays in a memory element of a semiconductor integrated circuit device equipped with a DRAM using pore technology. There is a particular thing.

Another object of the present invention is to eliminate the third problem, and provide a storage element of a semiconductor integrated circuit device equipped with a DRAM using pore technology, in which the capacitance portion is a memory element of a semiconductor integrated circuit device equipped with a DRAM. The purpose is to improve the degree of integration of the device.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in conjunction with this application is as follows.

In other words, in the capacitive part of the memory cell provided by the pore, by providing the charge storage part inside the pore that is electrically classified as the semiconductor substrate, the charge storage part can be connected to the inside of the semiconductor substrate from each capacitive part of the adjacent memory cell. The purpose is to eliminate unnecessary depletion regions that cause malfunctions and prevent leakage phenomena, which is the first problem.

〔Example〕

Hereinafter, the present invention will be described in detail along with one embodiment.

In this embodiment, the structure and manufacturing method of a memory element (hereinafter referred to as a memory cell) of a semiconductor integrated circuit device including a DRAM will be explained.

FIG. 1 shows a DRAM for explaining one embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram showing a main part of a memory array of a semiconductor integrated circuit device equipped with a semiconductor integrated circuit device.

In FIG. 1, SAl, SA2. . . . is a sense amplifier, which is used to amplify a minute potential difference between a predetermined memory cell and a predetermined dummy cell, which will be described later. BL
,,, BL, is the sense amplifier SA.

A bit line extends in the row direction from the negative end of the bit line.

BL2. , BL22 are bit lines extending in the row direction from one end of the sense amplifier SA2. These bits iB
L is for transmitting electric charges that serve as information. W
L, , WL are word lines extending in the column direction, and are connected to predetermined gate electrodes constituting a dummy cell M I S FET to be described later, and are used to control the ON and OF of the M I S FET. This is for performing fi' operation.W
ll, , WL4 is a word line extending in the column direction, and is connected to a predetermined gate electrode constituting a MISFET of a memory cell, which will be described later, and controls the ON/OFF operation of the MISFET. It is for the purpose of M...
, M, 2. M2. , M22. . . . are memory cells that hold charges that serve as information. Memory cells M, , M, 2. M2. ,
M22 is a MIS F whose one end is connected to a predetermined bit line BL and whose gate electrode is connected to a predetermined word line WL.
E 'I'Q, II r Q+21 Q2+ +
Qz2t...and the MIS, F"E'l
' One end is connected to the other end of Q, n -Q10, Q21, Q, 22..., and the other end is at a fixed potential vS
s terminal V-connected capacitor parts 011, 012,
There is a high C composed of OH, 022, and so on. D
,,, D,2. D.

D22. . . . are dummy cells that hold such charge that the information of the memory cell M, y1//, 110” can be determined.Dummy cells D, .

D.2. D2. , D22 has one end connected to a predetermined bit line BL and a gate electrode connected to a predetermined word line WL.
1QD211QD22°°° and the M I S F B
T Qnll・QD12・QD21・QD2□・・・
One end is connected to the other end, and the other end is at a fixed potential v
A capacitor C91 is connected to the 88 terminal.

OD1□, OD2□1CD2□, and the capacitance part OD1□1
It is composed of a clearing MISFET0Q for clearing the charge accumulated in CD121C2110D2□. φゎ is a terminal connected to the gate electrode of the clearing MISFET0Q.

Next, the structure of one embodiment of the present invention will be explained.

FIG. 2 (5) is a plan view showing a main part of a memory cell for explaining a semiconductor integrated circuit device equipped with a DRAM according to an embodiment of the present invention. X-
It is a cross-sectional view in an X-ray.

In addition, in the plan views shown in Figure 2 (5) and thereafter, in order to clarify the plan views if necessary, part or all of the insulating film to be provided on each layer may be removed. do.

Furthermore, in all the figures, parts having the same function are given the same reference numerals, and repeated explanations will be omitted.

In the 21st cell and FIG. 2(B), 1 is a p-type semiconductor substrate for configuring a semiconductor integrated circuit device. 3
is a pore provided in the semiconductor substrate 1, which constitutes the capacitance WIC of the memory cell and is used to increase the amount of charge storage which becomes information.

Reference numeral 6 denotes an insulating film provided on the inner surface of the pore 3 and on a part of the surface of the semiconductor substrate 1, and is used to electrically isolate the semiconductor substrate 1 from a first capacitor plate to be described later. Reference numeral 9 denotes a first capacitor plate according to an embodiment of the present invention, which is provided on the pore 3 and a part of the surface of the semiconductor substrate 1 so as to cover the upper part of the insulating film 6, and is used to constitute the capacitor part O of the memory cell. It is something. This first capacity plate 9 is
It has conductivity, and has a fixed potential, preferably V6s.
It is now connected to the terminal. Reference numeral 8 denotes a capacitive insulating film according to an embodiment of the present invention provided so as to cover the first valley plate 9.
It is located at the intervening part between the capacitor plate and stores electric charges that serve as information. 10 is the first capacity plate 9
and an insulating film for electrically isolating the semiconductor substrate 1 and a second capacitor plate, which will be described later. 11 is an insulating film 10
This connection hole is provided by removing a portion of the contact hole, and is for connecting a second capacitor plate and a semiconductor region, which will be described later. 12 is a capacitive insulating film 8 on top of the first capacitive grating 9.
MISF, part of which will be described later
This is a second capacitor plate according to an embodiment of the present invention provided connected to one end of a semiconductor region constituting an ET, and is for constituting a capacitor portion C of a memory cell. 14 is the upper part of the second capacitor plate 12 and a MISFET which will be described later.
It is an insulating film provided on the upper part of the semiconductor substrate 1 that constitutes the capacitive part 0. of the adjacent memory cell. , O, and to electrically isolate the second capacitor plate 12 from a word line, which will be described later, extending over the second capacitor plate 12, and to form a gate insulating film of a MISFET, which will be described later. 15 is a gate electrode and a word line, and MI
This is used to configure the gate electrode of 5FETQ+ and to configure a word line that applies a voltage to the gate electrode. Reference numeral 16 denotes a semiconductor region of n"ffi provided near the surface of the semiconductor substrate 1 to constitute the MISFE'I'Q+. The -16 is connected to the second capacitor plate 12, and the other is a bit which will be described later. In this embodiment, the other semiconductor region 16 is in common with the other memory cell (not shown).

j7 is an insulating film for electrically isolating the word line 15 and a bit line, which will be described later, extending above the word line 15. 18 is an insulating film 14 above the other semiconductor region 16.
This is a connection hole provided by removing 17, and is for connecting the semiconductor region 16 to a bit line to be described later. A bit line 19 is provided to be connected to the semiconductor region I6 via the connection hole 18.

Next, the operation of this embodiment will be explained using the 21st case and FIG. 2(B).

First, a description will be given of a case in which a seeding operation is performed in a memory cell constituted by a MISFETQ and a capacitor C7. MISFETQ.

A voltage is applied to the gate electrode 15 of MISFETQ, and MISFETQ is turned on. After this, a voltage representing information is applied to the bit line 19. The voltage serving as this information is applied to the second capacitor plate 12 via the semiconductor region 16 of MISFETQ. If there is a potential difference between the voltage serving as this information and the fixed potential Vss applied to the first capacitor plate 9, the first
Charges serving as information are accumulated, so-called, written in the capacitive insulating film 8 at the intervening portion between the capacitive plate 9 and the second capacitive plate 12 .

When performing a read operation, the operation described above may be performed in reverse.

In other words, in this embodiment, the information is stored in the capacitor portion of the memory cell! Since a semiconductor substrate is not used for the load storage section, it is possible to prevent leakage between capacitance sections of adjacent memory cells.

In addition, in the capacitor part, by preventing the influence of unnecessary minority carriers generated by α rays that may exist in the semiconductor substrate on the information charge, and by using pore technology, A predetermined charge storage amount can be provided that can suppress the influence of minority carriers.

Furthermore, even if the pore size is about 1 [μm] or more, the pore can be sufficiently filled with the first capacitor plate, the second capacitor plate, the capacitor insulating film, and the other insulating films.

Next, a specific manufacturing method according to an embodiment of the present invention will be explained.

FIGS. 3, 4, 5 (8), and 6 to 9.

Figure 10 Prisoner, Figure 11, Figure 12 (5), Figure 13 are:
FIG. 5 [F]) is a cross-sectional view showing a main part of a memory cell in each manufacturing process for explaining a method of manufacturing a semiconductor integrated circuit device equipped with a DRAM according to an embodiment of the present invention.
The plan view of the 5th inversion, Figure 10 CB+ is shown in Figure 10 (8)
The plan view of FIG. 12 (G3) is the plan view of FIG. 12 (5). In addition, each country of return corresponds to it (B
) is a sectional view taken along line XX in the figure.

First, a p-type semiconductor substrate l made of single crystal silicon (Si) is prepared. Thereafter, a heat treatment is performed to form an insulating film 2 for forming an etching-resistant mask, as shown in FIG. This insulating film 2 is made of silicon dioxide (SiO
It consists of t).

After the step shown in FIG. 3, as shown in FIG. 4, the insulating film 2 is patterned to form a capacitance section using pores, and a mask for etching resistance is formed. Using this mask, the semiconductor substrate 1 is subjected to anisotropic etching to form the pores 3.

The dimensions of the pores 3 should be about 1 to 1.5 [μm], and the depth should be about 2 to 5 [μm]. After this, the mask is removed, resulting in the fifth position and as shown in FIG. 5 (Bl).

After the steps shown in FIG. 5(A) and FIG. 5(B), as shown in FIG. An insulating film 4 and an insulating film 5 are formed to form an electrically isolated field insulating film. This insulating film 4 may be made of, for example, silicon dioxide, and the insulating film 5 may be made of, for example, nitride (Sj3N4), which serves as a heat-resistant treatment mask. The insulating film 5 is patterned to form a heat-resistant treatment mask (not shown) for forming a field insulating film. Heat treatment is performed using this mask,
A field insulating film (not shown) is formed on a predetermined portion of the semiconductor substrate 1 of the peripheral circuit. After that, the mask is removed and a predetermined portion, for example, the insulating film 4 on the memory cell portion is removed.
When is removed, the result is as shown in FIG.

After the step shown in FIG. 7, the semiconductor substrate 1 is subjected to heat treatment to form an insulating film 6 made of silicon dioxide, for example, on the upper surface of the semiconductor substrate 1 and along the pores 3. This insulating film 6 is
This is to electrically isolate the first capacitor plate and the semiconductor substrate 1, which will be formed in a later manufacturing process, and its film thickness only needs to be about 500 (A).After this, the capacitor part of the memory cell is A first layer of conductive material 7 is formed for forming a first capacitor plate constituting the first capacitor plate.This conductive material 7 is made of, for example, polycrystalline silicon (Si), and after its formation, conductive material 7 is formed. In the case of the polycrystalline silicon, the film thickness is 3o.
It is sufficient if it is about oo(i). After this, as shown in FIG. 8, a capacitive insulating film 8 constituting the capacitive part of the memory cell is formed. This capacitive insulating film 8 is made of, for example, silicon dioxide and nitride having a high dielectric constant, and each film has a thickness of 8.
It is sufficient if it is about 0 to 150 [A].

After the process shown in FIG. 8, as shown in FIG. 9, the capacitive insulating film 8. Conductive material7. Insulating film 6 is removed and first capacitor plate 9 is formed.

After the step shown in FIG. 9, a second capacitor plate and a semiconductor substrate 1 are formed to improve the insulation performance of the capacitor insulating film 8 and to cover the exposed end surface portion of the first capacitor plate 9 (not shown).
An insulating film 10 made of silicon dioxide, for example, is formed on the entire surface for electrical isolation from the semiconductor device. After this, Figure 10 (
As shown in FIG. 10(B), the second capacitor plate and M I S F
For connection with the semiconductor region constituting ET, a predetermined portion of the insulating film 10 is removed to form a contact hole 11.

After the steps shown in FIG. 10(A)s- and FIG. 10), a second layer of conductive material is formed to form a second capacitor plate constituting the capacitor portion of the memory cell. This conductive material may be made of polycrystalline silicon, for example, and may be treated with phosphorus to obtain conductivity after its formation. In the case of polycrystalline silicon, the film thickness is 3000 [A
/] is sufficient. After this, the conductive material in the portion other than the portion that will become the capacitor portion is removed to form the second capacitor plate 12.

Further, when the insulating film 10 except for the second capacitor plate 12 is removed, the result is as shown in FIG. 11.

Reference numeral 13 denotes an n-type semiconductor region formed by diffusing n-type impurities introduced into the vicinity of the surface of the semiconductor substrate 1 through the conductive material in the connection hole 11 by the phosphorus treatment.

After the process shown in FIG.
An insulating film 14 is formed over the entire surface in order to electrically isolate the gate insulating film constituting the ET and the respective capacitance portions of adjacent memory cells. This insulating film 14 is made of silicon dioxide, for example, and has a thickness of 2000 to 300 [A]
It is enough. Further, the insulating film 14 is formed to be thicker than the film formed on the semiconductor substrate 1, which is equal to the film thickness formed on the second capacitor plate 12. This is because the growth rate of the insulating film 14 formed on the second capacitor plate 12 is faster than that of the semiconductor substrate 1.

After this, a third layer of conductive material is formed to form a gate pole and a word line constituting the MISFET. This conductive material uses polycrystalline silicon, for example,
After its formation, phosphorus treatment may be performed to obtain conductivity. In the case of polycrystalline silicon, the film thickness is 30
00 [A] degree is fine. Further, the conductive material may be a high melting point metal material such as molybdenum (Mo) or tungsten (W), or a compound (silicide) of these and silicon. patterning the conductive material;
A gate electrode and word line (WL) 15 are formed.

After this, as shown in the 12th rotation and FIG. An n+ type semiconductor region 16 is formed in the vicinity of the surface of the semiconductor substrate 1 through
An ion implantation technique using an energy of about 80 [KeV'l] may be used to implant arsenic (As) ion impurities of about X101' [atoms/C].

After the steps shown in FIG. 12(5)2 and FIG. 12(B), a step is performed to electrically isolate the word line (WL) 15 and the bit line (BL) formed in a later manufacturing process. An insulating film 17 is formed over the entire surface. This insulating film 17 is made of, for example, phosphosilicate glass (PSG), and its thickness may be about 6000 [A'3]. After this, the insulating film 14.17 on the top of the semiconductor region 16 on the opposite side to the semiconductor region 16 connected to the second surface plate 12 constituting the M I S F E T Q of the memory cell is removed. A connection hole 18 for connection to a bit line (BL) formed in the manufacturing process is formed. A bit line (BL) is connected to the semiconductor region 16 through this connection hole 18.
Form 19 - [ru. This bit line (131,) 19 is
For example, using aluminum (Al), the film thickness is 800 mm.
It is sufficient if it is about 0 [A'll.

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Note that, after this, a treatment such as a protective film may be applied.

FIG. 14 is a plan view showing a main part of a memory array constructed of memory cells of this example.

As is clear from FIG. 14, the electrical isolation between adjacent memory cells is LOOO3 (LOOaIQxida
No field insulating film is required using the ion of silicon technology. Therefore, the degree of integration in the memory array can be further improved.

〔Effect of the invention〕

According to the present invention, in the capacitance portion of a memory cell provided by a pore, by providing the charge storage portion inside the pore electrically isolated from the semiconductor substrate, the capacitance portion of each adjacent memory cell Unnecessary depletion regions that extend into the inside of the semiconductor substrate and cause malfunctions can be removed. Therefore, it is possible to prevent a leakage phenomenon occurring in the respective capacitance portions of adjacent memory cells, which would otherwise occur due to high integration.

In addition, in the capacitive part of the memory cell provided by the pore, by providing the charge storage part inside the pore which is electrically isolated from the semiconductor substrate, alpha rays that may exist in the semiconductor substrate can be removed. By using pore technology, it is possible to provide a predetermined amount of charge accumulation that can suppress the influence of unnecessary minority carriers generated by α rays by preventing the influence of the generated unnecessary minority carriers on the electric charges that serve as information. can.

Moreover, even if the pore size is about 1 [μm] or more, the first
The pores can be sufficiently filled by the capacitor plate, the second capacitor grating, the capacitor P3 edge film and other insulating films. Therefore, the upper surface portion of the pore portion is flattened, and it is possible to reduce the force zero variation of the word line and bit line that may be formed thereon.

Furthermore, it is possible to prevent leakage phenomena in each capacitive part of adjacent memory cells, prevent the influence of minority carriers caused by alpha rays in the capacitive part, and prevent unnecessary minority carriers caused by alpha rays. A predetermined amount of charge accumulation that can suppress the influence can be provided,
And LOOO is used for electrical isolation between adjacent memory cells.
In order to avoid using field insulating film using 8 technology, DR
The degree of integration of a semiconductor integrated circuit device including AM can be improved.

Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples (and can be modified in various ways without departing from the gist of the invention). Needless to say, it is.

[Brief explanation of the drawing]

FIG. 1 shows a DRAM for explaining one embodiment of the present invention.
FIG. 2 (4) is an equivalent circuit diagram showing main parts of a memory array of a semiconductor integrated circuit device equipped with a DRAM according to an embodiment of the present invention. FIG. 2(B) is a cross-sectional view of the second device along the line X-X, FIGS. 3, 4, and 5, and FIGS. 6 to 9. FIG. 10, FIG. 12, and FIG. 13 show the main parts of a memory cell in each manufacturing process for explaining a method for manufacturing a semiconductor integrated circuit device equipped with a DRAM according to an embodiment of the present invention. The sectional view, FIG. 5(g)) is a plan view of the 51st prisoner, and FIG.
FIG. 14B is a plan view of the twelfth arrangement, and FIG. 14 is a plan view showing the main part of the memory array constructed by the memory cells of the present invention.

Claims (1)

[Claims] 1. A second conductive type provided on the entire surface of the semiconductor substrate of the first conductivity type.
An insulated gate field effect transistor having a pair of conductivity type semiconductor regions and a gate electrode formed on an insulating film covering a surface of a semiconductor substrate between the pair of first semiconductor regions; and the insulated gate field effect transistor. A semiconductor integrated circuit device comprising a capacitor section provided in connection with a first semiconductor region of 10,000 effect transistors, wherein the capacitor section includes a pore provided in a whole surface of a semiconductor substrate, and at least the pore. The first hole is provided to cover the side wall of the hole.
an insulating film; a first conductive capacitor plate provided to cover the first insulating film; a second insulating film provided above the first capacitor plate; and a second insulating film provided above the second insulating film. , and one end thereof is the above-
The invention is characterized by comprising a conductive second capacitor plate that is provided to be electrically connected to the first semiconductor region of the semiconductor device and is electrically separated from the first capacitor plate. Semiconductor integrated circuit device. 2. Permissible range of claims 1. In the semiconductor integrated circuit device according to claim 1, the capacitor section stores charges in a second insulating film that is an intervening portion between the first capacitor plate and the second capacitor gate. A semiconductor integrated circuit device characterized in that the second insulating film has an effective dielectric constant higher than that of the first insulating film.