JP2539304B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
ilmtransistor) Load type SRAM (st)
atic random access memory
The present invention relates to an improvement of a semiconductor memory device called y) and its manufacturing method.

Until recently, SRAMs of the type having a high resistance as a load have been widely used. However,
As the degree of integration increases and the number of memory cells increases, current consumption increases and various problems occur. Therefore, it is necessary to avoid them and the progress of semiconductor technology leads to TF.
SRAM with a load of T has come to be realized. However, another new problem occurs due to the use of the TFT as a load, and it is necessary to eliminate it.

[0003]

19 to 28 show a high resistance load type SRA.
29 is a sectional side view of a main part in a process step for explaining a conventional example of a method for manufacturing M, and FIGS. 29 to 34 are for explaining a conventional example of a method for manufacturing a high resistance load type SRAM. Each of the plan views of the essential parts in the process key points of
Hereinafter, description will be made with reference to these figures. The cut side views of the main parts of FIGS. 19 to 28 are taken along the line YY shown in FIG. 34 which is a plan view of the main parts.

19- (1) For example, a silicon dioxide (SiO ₂ ) film is used as a pad film,
Selective thermal oxidation (eg, local) using a silicon nitride (Si ₃ N ₄ ) film laminated thereon as an oxidation resistant mask film.
oxidation of silicon: LOC
OS) method to apply the silicon semiconductor substrate 1
A field insulating film 2 made of SiO ₂ and having a thickness of 4000 [Å] is formed thereon. 19- (2) Si ₃ N ₄ film and SiO ₂ used for selective thermal oxidation
The film is removed to expose the active region in the silicon semiconductor substrate 1.

See FIG. 20. 20- (1) By applying a thermal oxidation method, a gate insulating film 3 made of SiO ₂ and having a thickness of, for example, 100 [Å] is formed. 20- (2) The contact hole 3A is formed by selectively etching the gate insulating film 3 by applying a resist process in the photolithography technique and a wet etching method using hydrofluoric acid as an etchant. To do.

21 and 29. 21- (1) Chemical vapor deposition
The first polycrystalline silicon film having a thickness of, for example, 1500 [Å] is formed by applying the position (CVD) method. 21- (2) By applying the vapor phase diffusion method, for example, 1 × 10 ²¹
Phosphorus (P) of [cm ⁻³ ] is introduced to form an n ⁺ − impurity region 5 ′. In FIG. 29, the first polycrystalline silicon film is omitted for the sake of simplicity.

See FIG. 22. 22- (1) Resist ion process in photolithography and reactive ion etching using CCl ₄ / O ₂ as an etching gas.
ing: RIE) is applied to pattern the first polycrystalline silicon film to form the gate electrode 4. The gate electrode 4 is a word line, a driver,
This is the gate electrode of the transistor. 22- (2) By applying the ion implantation method, the dose amount is set to 3 × 1.
The source region 5 and the drain region 6 are formed by implanting As ions at 0 ¹⁵ [cm ⁻² ] and an acceleration energy of 40 [keV].

23 and FIG. 30. 23- (1) By applying the CVD method, the thickness is, for example, 1000.
The insulating film 7 made of SiO _{2 of} [Å] is formed. 23- (2) RIE in which resist process in photolithography technology and CHF ₃ / He as etching gas are used
Ground wire contact hole 7 by applying the method
Form A. The ground line contact hole 7A is not visible in FIG.

Refer to FIG. 24 24- (1) By applying the CVD method, the thickness is, for example, 1500.
A second polycrystalline silicon film of [Å] is formed. 24- (2) By applying the resist process in the photolithography technique and the RIE method using CCl ₄ / O ₂ as the etching gas, the second polycrystalline silicon film is patterned to form the ground line. 8 is formed.

25 and 31. 25- (1) By applying the CVD method, the thickness is, for example, 1000.
The insulating film 9 made of SiO _{2 of} [Å] is formed. 25- (2) By applying the resist process in the photolithography technique and the RIE method using CHF ₃ / He as the etching gas, the insulating film 9 is selectively etched to form the load resistance contact hole. 9A is formed.

See FIG. 26. 26- (1) By applying the CVD method, the thickness is, for example, 1500.
A third polycrystalline silicon film of [Å] is formed. 26- (2) The dose amount is set to 1 by applying the resist process and the ion implantation method in the photolithography technique.
× 10 ¹⁵ [cm ⁻² ], acceleration energy of 30
As [keV], As ions are implanted into a portion which should be a supply line of the positive power supply voltage _Vcc and a portion where a high resistance load contacts the gate electrode 4. 26- (3) By using the resist process in the photolithography technique and applying the RIE method using CCl ₄ / O ₂ as an etching gas, the third polycrystalline silicon film is patterned to form a contact portion. 10, high resistance load 1
1, V _cc power supply level supply line 12 is formed.

27 and 32. 27- (1) By applying the CVD method, the thickness is, for example, 1000.
[Å] SiO ₂ insulating film and thickness, for example 500
0 [Å] phospho-silicate glass (phospho-silic)
An insulating film made of ate glass (PSG) is formed. In the drawing, the two layers of the insulating film are integrally shown, and this is referred to as an insulating film 13. 27- (2) A heat treatment for reflowing and flattening the insulating film 13 is performed. 27- (3) In the photolithography technique, the resist process and the RIE method using CHF ₃ / He as the etching gas are applied to selectively etch the insulating film 13 and the like, thereby performing bit line contact. The hole 13A is formed.

28 and 33. 28- (1) By applying the sputtering method, the thickness, for example, 1
An Al film of [μm] is formed and is patterned by applying a normal photolithography technique to form the bit line 14. It should be noted that those not described with the symbols shown in FIGS. 28 and 33, such as BL, will become clear when compared with FIG. 35 described below.

FIG. 34 is a plan view of an essential part of a high resistance load type SRAM completed through the steps described above. The same symbols as those used in FIGS. 19 to 33 represent the same parts or the same. It has meaning. However, for the sake of simplicity, the bit line 14 made of Al shown in FIGS. 28 and 33 is removed from FIG. 34.

FIG. 35 is an equivalent circuit diagram of a main part of the high resistance load type SRAM described with reference to FIGS. 19 to 34. In the figure, Q1 and Q2 are driving transistors,
Q3 and Q4 are transfer gate transistors,
R1 and R2 are high-resistance load, WL denotes a word line, BL and / BL are bit lines, the S1 and S2 _node, the _{V cc} represents the positive supply _{voltage, V ss} is a negative supply voltage, respectively.

Operation in this high resistance load type SRAM,
In particular, memory retention is performed as follows.
Now, the positive power supply voltage V _cc = 5 [V], the negative power supply voltage V
_ss = 0 [V], and node S1 = 5
Assuming that [V] and node S2 = 0 [V], the transistor Q2 is on and the transistor Q1 is off. At node S1, transistor Q1
Is off and the resistance value in that case is high resistance load R
If it is sufficiently higher than 1, the potential is maintained at 5 [V]. At the node S2, if the transistor Q2 is in the ON state and the resistance value in that case is sufficiently lower than that of the high resistance load R2, the potential is maintained at 0 [V].

However, under the above conditions, the negative power supply voltage _{Vcc is} supplied from the positive power supply voltage _Vcc supply line side through the node S2.
DC current flows to the _ss supply line side, and the value is high resistance load R
It is inversely proportional to the value of 2.

As the integration degree of such a high resistance load type SRAM increases, the number of memory cells per chip increases, so that the current consumption of the entire chip increases unless the current consumption per memory cell is reduced. Will end up. Therefore, it is necessary to reduce the DC current, but it is necessary to increase the values of the high resistance loads R2 and R1. However, when this resistance value is increased, it becomes difficult to maintain a stable potential at the node on the side where the driving transistor is turned off, that is, the node S1 in the above example.

With the background as described above, a TFT load type SRAM using a TFT as a load instead of a high resistance has appeared.

The TFT load type SRAM will be described here. First, as in the case of the high resistance load type SRAM, the case of manufacturing the TFT load type SRAM will be described first.

36 to 39 are TFT load type SRAMs.
40A to 43C are side views of a main part cut in a process main part for explaining a conventional example of a method for manufacturing a TFT, and FIGS.
The plan views of the main parts in the process steps for explaining the conventional example of the method of manufacturing the load type SRAM are shown respectively, and the description will be given below with reference to these drawings. 36 to 39 are cut side views taken along the line Y-Y shown in FIG. 43, which is a plan view of the main part. The steps from 19- (1) to 25- (2), that is, the steps of manufacturing the high resistance load type SRAM described above, that is, the steps of forming the load resistance contact hole 9A are as follows.
Almost the same steps are applied in the process of manufacturing the TFT load type SRAM, and the TFT formed by the third polycrystalline silicon film is different from the ground line 8 formed by the second polycrystalline silicon film. The only difference is that the gate electrode is formed with an opening 8A (see FIG. 40) necessary for making contact with the gate electrode 4 formed of the active region and the first polycrystalline silicon film. It will be explained from the subsequent stage. Of course, the same symbols as those used in FIGS. 19 to 35 represent the same parts or have the same meanings.

36 and 40. 36- (1) By applying the CVD method, the thickness is, for example, 1500.
A third polycrystalline silicon film of [Å] is formed. 36- (2) The dose amount is set to 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ⁻² ], and the acceleration energy is 20 [k
eV], and P ions are implanted. 36- (3) By applying the resist process in the photolithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas, the third polycrystalline silicon film is patterned to form a TFT. The gate electrode 15 is formed.

See FIG. 37 37- (1) By applying the CVD method, the gate insulating film 16 of the TFT having a thickness of, for example, 300 [Å] and made of SiO ₂ is formed. 37- (2) The drain contact hole is formed by selectively etching the gate insulating film 16 by applying a resist process in the photolithography technique and a wet etching method using hydrofluoric acid as an etchant. 16
Form A.

38 and 41. 38- (1) By applying the CVD method, the thickness is, for example, 500.
A fourth polycrystalline silicon film of [Å] is formed. 38- (2) The dose amount is set to 1 by applying the resist process and the ion implantation method in the photolithography technique.
× 10 ¹⁴ [cm ⁻² ], and the acceleration energy was 5 [k
eV], B ions are implanted into the portions that will become the source and drain regions of the TFT and the portions that will become the V _cc supply line. 38- (3) By applying the resist process in the photolithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas, the fourth polycrystalline silicon film is patterned to form a TFT. A source region 17, a drain region 18, a channel region 19 and a V _cc supply line 20 are formed.

39 and 42. 39- (1) By applying the CVD method, the thickness is, for example, 1000.
[Å] SiO ₂ insulating film and thickness, eg 50
An insulating film made of PSG of 00 [Å] is formed. Note that, also in this figure, as in FIGS. 37 and 38, two layers of insulating films are integrally shown, and this is referred to as an insulating film 21. 39- (2) A heat treatment for reflowing and flattening the insulating film 21 is performed. 39- (3) By applying the resist process in the photolithography technique and the RIE method using CHF ₃ / He as the etching gas, the insulating film 21 and the like are selectively etched to contact the bit line contact. Form a hole. 39- (4) By applying a sputtering method, the thickness is, for example, 1
An Al film of [μm] is formed and is patterned by applying a normal photolithography technique to form the bit line 22. Those not described with the symbols shown in FIGS. 39 and 42, such as BL, will be apparent when compared with FIG. 44 described later.

FIG. 43 is a plan view of an essential part of a TFT load type SRAM completed through the steps described above. The same symbols as those used in FIGS. 19 to 42 represent the same parts or have the same meaning. Shall have. However, for simplification, the bit line 22 made of Al shown in FIGS. 39 and 42 is removed from FIG. 43.

FIG. 44 shows an equivalent circuit diagram of a main part of the TFT load type SRAM described with reference to FIGS. 36 to 42. The same symbols as those used in FIGS. 36 to 42 and FIG. 35 represent the same parts or have the same meanings. In the figure, Q5 and Q6 respectively represent transistors which are load TFTs.

Operation in this TFT load type SRAM,
In particular, memory retention is performed as follows.

Now, the positive side power supply voltage V _cc = 5 [V] and the negative side power supply voltage V _ss = 0 [V] are set, and the node S1 = 5 [V] and the node S2 = 0 [V]. Then, the transistor Q2 is on and the transistor Q2
6 is in the off state, the transistor Q1 is in the off state, and the transistor Q5 is in the on state. At the node S1, if the transistor Q1 is in the off state and the resistance value in that case is sufficiently higher than the on state of the transistor Q5, the potential is maintained at 5 [V]. At the node S2, if the transistor Q2 is in the on state and the resistance value in that case is sufficiently lower than the off state of the transistor Q6, the potential is 0.
It is maintained at [V].

As described above, under the above conditions, the resistance value of the transistor Q5 or the transistor Q6, which is a load, changes in accordance with the stored information, so that the high resistance load type SRA is used.
The problem in M is solved and stable information storage can be performed. The transistors Q5 and Q6 used here are
The channel of the load TFT, that is, the channel of the load TFT, is made of polycrystalline silicon, and its crystal state is much worse than that of single crystal. Therefore, even when it is in the off state, current leaks. Since it is easy and the leak current becomes the current consumption of the chip as it is, it is desirable to make it as small as possible.

By the way, as is apparent from FIG. 39, in this TFT load type SRAM, A is formed on the uppermost layer.
A bit line 22 made of an L film is provided, and a channel of the load TFT is present immediately below the bit line 22 via an insulating film 21 made of PSG or the like.

Such a structure can be regarded as a transistor in which the bit line 22 made of an Al film is the gate electrode and the insulating film 21 thereunder is the gate insulating film, and the bit which is the gate electrode. The electric potential of the line 22 is 0 [V]
It changes between (V _ss ) and 5 [V] (V _cc ), so that the TFT which should be in the off state, that is, the transistor Q.
6 becomes close to the ON state, the leak current increases, and the parasitic effect becomes remarkable. Therefore, in order to solve such a problem, a double gate structure TFT load type SRAM, which is an improved type of the TFT load type SRAM, has been developed.

This double gate structure TFT load type SRAM
Then, the fifth polycrystalline silicon film in the TFT load type SRAM described with reference to FIGS. 36 to 44, specifically, the fifth polycrystalline silicon film forming the second gate electrode having the same pattern as the gate electrode 15 of the TFT. The polycrystalline silicon film of the source region 17, the drain region 18, the channel region 19,
The above problem is solved by interposing it between the fourth polycrystalline silicon film forming the V _cc supply line 20 and the like and the bit line 22 made of Al.

45 to 47 show a double gate structure TFT.
FIG. 3 is a sectional side view of a main part at a process step for explaining a conventional example of a method of manufacturing a load type SRAM, which will be described below with reference to these drawings. It should be noted that steps 36- (1) to 38- (3), which are steps for manufacturing the TFT load type SRAM described above, that is, the TFT
Source region 17, drain region 18, channel region 1 of
9. The steps up to forming the V _cc supply line 20 are almost the same in the steps of manufacturing the double gate structure TFT load type SRAM, and therefore, the steps after that will be described. Of course, the same symbols as those used in FIGS. 19 to 44 represent the same parts or have the same meanings.

See FIG. 45. 45- (1) By applying the CVD method, the insulating film 23 made of SiO ₂ and having a thickness of, for example, 500 [Å] is formed. 45- (2) In the photolithography technique, the resist process and the RIE method using CHF ₃ + He as the etching gas are applied to selectively etch the insulating film 23 to form the fourth polycrystal. A contact hole 23A for the silicon film is formed.

See FIG. 46. 46- (1) By applying the CVD method, the thickness is, for example, 1000.
A fifth polycrystalline silicon film of [Å] is formed. 46- (2) By applying the thermal diffusion method, for example, 1 × 10 ²¹ [cm ⁻³ ] of P is diffused into the fifth polycrystalline silicon film. 46- (3) The fifth polycrystalline silicon film is patterned by applying the resist process in the photolithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas. The second gate electrode 24 is formed.

See FIG. 47. 47- (1) By applying the CVD method, the thickness is, for example, 1000.
[Å] SiO ₂ insulating film and thickness, eg 50
An insulating film made of PSG of 00 [Å] is formed. Note that, also in this figure, as in FIG. 39, a two-layer insulating film is integrally shown, and this is referred to as an insulating film 25. 47- (2) A heat treatment for reflowing and flattening the insulating film 25 is performed. 47- (3) By applying the resist process in the photolithography technique and the RIE method using CHF ₃ / He as the etching gas, the insulating film 25 or the like is selectively etched to contact the bit line contact. Form a hole. 47- (4) By applying the sputtering method, the thickness, for example, 1
An Al film of [μm] is formed and is patterned by applying a normal photolithography technique to form the bit line 26.

[0038]

DISCLOSURE OF THE INVENTION As described above,
SRAM begins with a high resistance load type,
It has progressed to a double gate structure TFT load type. However, first, FIGS. 19 to 28 (particularly FIG. 28) and FIG.
47 to 47 (particularly in FIG. 47), it should become clear from the high resistance load type SRAM to the double gate structure TF.
In the transition to the T-load type SRAM, the number of polycrystalline silicon films is increased by two layers, and the mask process is increased by four times.

Therefore, the inventors of the present invention connected the TFT load and the driver transistor to the same contact.
The number of manufacturing steps of the TFT load type SRAM can be reduced by making a simple modification such as a structure that can be performed in a hole. In that case, an insulating film made of SiO ₂ and a conductive film made of polycrystalline silicon are used. It is necessary to penetrate the layered portion in which the layers are laminated in one go at a stretch, and this causes a new problem.

48 to 53 are sectional side views of essential parts of a semiconductor memory device in process steps for explaining the case of forming a contact hole penetrating a multilayer laminated portion. A detailed description will be given with reference to the drawings. Note that the left side of the figure is an expected process, and the right side is an actual process, and the description will mainly be given along the actual process.

See FIG. 48. 48- (1) Here, in the illustrated semiconductor memory device, the first conductive film 32 made of polycrystalline silicon and the first conductive film made of SiO ₂ are already formed on the silicon semiconductor substrate 31. the insulating film 33, the second conductive film 34 made of polycrystalline silicon, the second insulating film 35 made of SiO _2, polycrystalline third conductive film 36 made of silicon, the third insulating film made of SiO ₂ 37 Are formed respectively.

See FIG. 49. 49- (1) The etching of the third insulating film 37 is performed by applying the resist process in the ordinary lithography technique and the RIE method in which the etching gas is CHF ₃ / He. Then, a part of the contact hole is formed. The resist film is omitted in the drawings, and the same applies to the following drawings. At this time, a part of the third conductive film 36, which is the base of the third insulating film 37, is also etched. Therefore, when the third conductive film 36 is thin, the remaining film becomes extremely small.

See FIG. 50. 50- (1) The third conductive film 36 is etched by applying the RIE method in which the etching gas is CCl ₄ / O ₂ . At this time, although it depends on the thickness of the second insulating film 35 which is the base of the third conductive film 36, it should be thin in the case of the present invention. Not only the second insulating film 35 but also a part of the second conductive film 34 is etched.

See FIG. 51. 51- (1) By applying the RIE method in which the etching gas is CHF ₃ / He, the second insulating film 35 is etched as intended. At this time, the second conductive film 3
4 and the first insulating film 33 may be etched to expose the first conductive film 32.

See FIG. 52. 52- (1) By applying the RIE method using CCl ₄ / O ₂ as an etching gas, the second conductive film 34 is etched as intended. At this time, the first conductive film 3
2 may be etched, and even a part of the silicon semiconductor substrate 31 may be etched.

See FIG. 53. 53- (1) By applying the RIE method using CHF ₃ / He as the etching gas, the first insulating film 33 is etched as intended. As a result, the contact hole completely cuts into the silicon semiconductor substrate 31.

If this happens, a leak occurs at the node portion of the driver transistor and the load transistor in the memory cell, and the operation of the memory cell becomes unstable. Considering the occurrence of such an accident, it may be considered that etching of each layer for forming a contact hole should be conserved, but it is impossible.

The reason for this is that the contact hole is
As shown in the figure, it is rare that it is formed on a flat place, but rather it is often formed on a place with a step,
In that case, if the etching is kept modest, the residue is likely to be present in the step portion in the contact hole, so that sufficient over-etching is necessary to remove the residue.

[0049]

In the semiconductor memory device and the manufacturing method thereof according to the present invention, the gate (or drain) of the driver transistor, the gate of the TFT load, and the drain of the TFT load are mutually contacted. Even if the contact hole is sufficiently over-etched so that there is no residue, an accident such as digging of the substrate does not occur, and an attempt is made to form a precise contact hole.

[0050]

1 to 6 are sectional side views of essential parts of a semiconductor memory device in process steps for explaining the principle of the present invention. Hereinafter, these figures will be referred to. I will explain. Incidentally, the same symbols as those used in FIGS. 48 to 53 represent the same parts or have the same meanings, and here again, the left side of the figure is the expected process, and the right side. Is an actual process, and the explanation will be given mainly according to the actual process.

1- (1) In the illustrated semiconductor memory device, the first conductive film 42 made of polycrystalline silicon, a high melting point such as W or WSi has already been formed on the silicon semiconductor substrate 41. the second conductive film 43, the first insulating film 44 made of SiO _2, the third conductive film 45 made of polycrystalline silicon, made of SiO ₂ second insulating film 46 made of a metal or its silicide, polysilicon It is assumed that a fourth conductive film 47 made of SiO ₂ and a third insulating film 48 made of SiO ₂ are formed.

See FIG. 2 2- (1) The etching of the third insulating film 48 is performed by applying the resist process in the ordinary lithography technique and the RIE method using CHF ₃ / He as the etching gas. Then, a part of the contact hole is formed. The resist film is omitted in the drawings, and the same applies to the following drawings. At this time, part of the fourth conductive film 47, which is the base of the third insulating film 48, is also etched. Therefore, when the fourth conductive film 47 is thin, the remaining film is extremely small, which is the same as the conventional technique.

See FIG. 3 3- (1) The fourth conductive film 47 is etched by applying the RIE method in which the etching gas is HBr / Ar. At this time, although it depends on the thickness of the second insulating film 46 which is the base of the fourth conductive film 47, it should be thin in the case of the present invention. Not only the second insulating film 46 but also a part of the third conductive film 45 is etched.

See FIG. 4 4- (1) By applying the RIE method in which the etching gas is CHF ₃ / He, the etching that should etch the second insulating film 46 is performed. At this time, the third conductive film 45 and the first insulating film 44 may be etched to expose the second conductive film 43.

See FIG. 5 5- (1) By applying the RIE method using HBr / Ar as the etching gas, the etching that should etch the third conductive film 45 is performed. At this time, the second conductive film 43 made of a refractory metal or a refractory metal silicide has already been exposed. However, since this is hardly etched by HBr, no problem occurs.

See FIG. 6 6- (1) By applying the RIE method in which the etching gas is CHF ₃ / He, the first insulating film 33 should be etched. Also at this time, the second conductive film 43 made of refractory metal or refractory metal silicide is CHF.
_Since it is hardly etched with ₃ / He, no problem occurs. Therefore, the contact hole is formed in an ideal state, and the only difference from the case where the conventional technique is applied is that the lowermost conductive film is formed of the first conductive film 42 and the second conductive film 43. The only difference is that

From the above, in the semiconductor memory device and the manufacturing method thereof according to the present invention, (1) it is configured to include a pair of transfer transistors, a pair of driver transistors and a pair of TFT loads, And T
FT load drain (eg drain region 18: FIG. 14)
And a gate electrode (for example, gate electrode 15: FIG. 14).
And a gate electrode of the driver transistor (for example, gate electrode 4: see FIG. 14), the memory cell having a connection region in which the drain and gate of at least a TFT load are provided. The electrode and the first conductive film of the driver transistor (for example, the first polycrystalline silicon film: see FIG. 7) and the second conductive film (for example, the second conductive film) made of a refractory metal (for example, W or Mo). : See FIG. 7), and a gate electrode is laminated via an insulating film (for example, insulating films 7, 9 and 16), and the laminated uppermost electrode is in the middle of the side surface of the electrode. Is characterized in that it is connected with the electrode of the lowermost layer and its surface, or,

(2) In the above (1), the gate electrode (eg, gate electrode 4: see FIG. 14) of the driver transistor is the first conductive film (eg, first polycrystalline silicon film: see FIG. 7). And a refractory metal silicide (for example, WSi) laminated thereon.
Or a second conductive film (for example, a second conductive film: see FIG. 7) made of MoSi or the like, or
Alternatively,

(3) In the above (1) or (2), each electrode in the connection region is the drain of the TFT load which is the uppermost layer (eg drain region 18: see FIG. 14) and the intermediate layer. TFT
Or a gate electrode of a load (eg, gate electrode 15: see FIG. 14) and a gate electrode of a driver transistor (eg, gate electrode 4: see FIG. 14) which is the lowermost layer, or

(4) In the above (1) or (2), the gate electrode in the TFT load has a channel region (for example, channel region 19:
An insulating film (for example, insulating film 16: FIG.
8)) and each electrode in the connection region is the uppermost gate electrode of the TFT load which is the uppermost layer (for example, the upper gate electrode 24: see FIG. 18) and the TFT load which is the intermediate layer. Drain (for example, drain region 18: see FIG. 18), lower gate electrode (for example, lower gate electrode 15: see FIG. 18), and driver which is the lowermost layer.
Gate electrode of transistor (eg, gate electrode 4: FIG.
8)), or

(5) A field insulating film (eg, field insulating film 2: see FIG. 14) is formed in a first region on the surface of a semiconductor substrate (eg, silicon semiconductor substrate 1: see FIG. 14) , and the first region is formed.
A step of forming a gate insulating film (for example, a gate insulating film 3: see FIG. 14) in a second region of the surface of the semiconductor substrate defined by the first conductive film ( For example, the first polycrystalline silicon film: see FIG. 7) and refractory metal (eg W
Alternatively, a second conductive film (for example, a second conductive film: see FIG. 7) made of Mo or the like is grown in order and then patterned to form a gate electrode of a driver transistor (for example, gate electrode 4: see FIG. 14). And then impurity is introduced into the semiconductor substrate using the field insulating film and the gate electrode as a mask to form impurity regions (for example, n ⁺ − source region 5 and n ⁺ − drain region 6: see FIG. 14). ) Is formed on the second conductive film.
Including a step of depositing and forming a first insulating film (for example, insulating films 7 and 9: see FIG. 14) on the semiconductor substrate , and then a third conductive film (for example, A third polycrystalline silicon film) is grown and patterned, and then a second insulating film (for example, insulating film 1) is formed on the surface of the third conductive film.
6: see FIG. 18), and then the second
The insulating film, the third conductive film, and the first insulating film are patterned.
Removing to expose the second conductive film on the bottom surface and
A process for forming an opening that exposes the third conductive film to a side surface.
And then the second conductive film exposed on the bottom surface of the opening.
And contact with the third conductive film exposed on the side surface of the opening.
And extend from inside the opening to outside the opening
A fourth conductive film (for example, a fourth polycrystalline silicon film) is formed so as to pass over the upper surface of the third conductive film, and is patterned (for example, to obtain a source region 17, a drain region 18, and a channel region 19). Patterning: See Figure 14)
And a step of forming the third conductive film and the fourth conductive film.
The channel of the TFT load in the area where the electrode film overlaps
One of the above steps so that the
In the overlapped region with the third conductive film and the third conductive film.
Select conductive impurities for either one of the four conductive films
Configured by introducing the

(6) In (5), the first conductive film (for example, the first polycrystalline silicon film: see FIG. 7) and the second conductive film made of refractory metal silicide are sequentially grown. Or a step of forming a gate electrode (for example, gate electrode 4: see FIG. 14) of the driver transistor by patterning from

(7) Semiconductor substrate (eg, silicon semiconductor substrate 1: see FIG. 18)
On the first area of the surface of the field.
Field insulating film 2: see FIG. 18), and the first region is formed.
A second region of the semiconductor substrate surface defined by
Forming an insulating film (for example, gate insulating film 3: see FIG. 18)
And then the first conductive film (for example, the first multi-layered film).
Crystalline silicon film) and refractory metal (such as W or Mo)
The second conductive film consisting of
Gate electrode of driver transistor
Step of forming (for example, gate electrode 4: see FIG. 18)
And then the field insulating film and the gate electrode
Impurities are introduced into the semiconductor substrate as a mask and
Pure regions (eg n ⁺ -source region 5 and n ⁺ -drain)
Area 6 (see FIG. 18), and then the second conductor is formed.
The first insulating film (eg, on the semiconductor film) on the semiconductor substrate.
Insulating films 7 and 9: see FIG. 18)
Then, on the first insulating film, a third conductive film (for example,
Patterning by growing a third polycrystalline silicon film)
Do (for example, formation of the gate electrode 15: see FIG. 18)
A second insulating film (for example, an insulating film) on the surface of the third conductive film.
16: see FIG. 18), and then the second
A fourth conductive film (for example, a fourth polycrystalline silicon film) on the insulating film of
Film) is grown and patterned, and then the fourth
Conductive impurities are selectively introduced into the conductive film of
On the surface of the fourth conductive film, a third insulating film (for example, insulating film 23:
18), and then the third insulation
A film, the fourth conductive film, the second insulating film, and the third
By patterning and removing the conductive film and the first insulating film,
Exposing the second conductive film on the bottom surface and exposing the third conductive film
Forming an opening to be exposed on the side surface, and then forming the opening.
Each of the second conductive film exposed on the bottom of the mouth and the side surface of the opening.
The exposed third conductive film and fourth conductive film
To be in contact with each other and from inside the opening to outside the opening
To extend the conductive impurities of the fourth conductive film.
The fifth conductive film (for example,
Fifth polycrystalline silicon film) formed and patterned (example
For example, patterning for forming the upper gate electrode 24: FIG.
8)), and the step of
The region into which the conductive impurities are introduced and the fifth conductive film are
A channel region is formed in the overlapping region, and T
Configured for FT load, or

(8) In the above (7), the first conductive film (for example, the first multi-connection) is used.
Crystalline silicon film) and refractory metal silicide (eg WS
i or MoSi, etc.) in sequence.
Driver transition after patterning after lengthening
Gate electrode (for example, gate electrode 4: see FIG. 18)
Is included.

[0065]

As apparent from the above description, according to the present invention, the interconnection of the gate electrode of the driver transistor and the gate electrode of the TFT load can be connected at the same location using the same contact hole. Therefore, the contact hole for interconnection between the driver transistor and the TFT load needs to be formed only once, and in the case of the normal TFT load type SRAM, compared with the conventional technique. It is possible to reduce the number of mask steps once, and in the case of using the dual gate structure TFT load type SRMA, it is possible to reduce the number of mask steps twice as compared with the conventional technique.・ Sufficient overrun to eliminate residue when forming holes ・
Even if etching is performed, there is no possibility that the exposed portion at the bottom of the contact hole will be damaged and the characteristics of the memory cell will be deteriorated. Therefore, this type of SRAM is easily and easily provided with good characteristics. Can be manufactured with high yield.

[0066]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 7 to 14 are sectional side views of a main part of a TFT load type SRAM in process steps for explaining one embodiment of the present invention, respectively, which will be described below with reference to these drawings. The details will be described. Incidentally, from the beginning of the step of manufacturing the conventional high resistance load type SRAM described with reference to FIGS. 19 to 28 to step 20- (2), that is, the gate insulating film 3 is selectively etched to form the contact hole 3A. The process is the same in this embodiment until the formation, and the description will be omitted and will be described from the next step. The description is based on the process for manufacturing the conventional TFT load type SRAM described with reference to FIGS. .

7- (1) Here, in the TFT load type SRAM, the field insulating film 2, the gate insulating film 3 and the contact hole 3A are already formed in the silicon semiconductor substrate 1. To do. 7- (2) A first polycrystalline silicon film having a thickness of, for example, 1000 [Å], which is the first conductive film, is formed by applying the CVD method. 7- (3) By applying the vapor phase diffusion method, for example, 1 × 10
²¹ [cm ⁻³ ] of phosphorus (P) is introduced to form an n ⁺ − impurity region 6 ′. 7- (4) A WSi film having a thickness of, for example, 1000 [Å], which is the second conductive film, is formed by applying the CVD method. still,
The WSi film can be replaced with a W film or another refractory metal film or another refractory metal silicide film.

See FIG. 8 8- (1) By applying the RIE method in which the resist process and the etching gas in the lithography technique are CCl ₄ / O ₂ (for WSi and for polycrystalline silicon),
The i-film and the first polycrystalline silicon film are patterned to form the gate electrode 4. The gate electrode 4 is a word line and a gate electrode of a driver transistor. 8- (2) The dose amount is set to 3 × 1 by applying the ion implantation method.
The source region 5 and the drain region 6 are formed by implanting As ions at 0 ¹⁵ [cm ⁻² ] and an acceleration energy of 40 [keV].

See FIG. 9 9- (1) By applying the CVD method, the thickness is, for example, 1000.
The insulating film 7 made of SiO _{2 of} [Å] is formed. 9- (2) RIE using resist process and etching gas CHF ₃ / He in photolithography technology
A ground line contact hole is formed by applying the method. It should be noted that the ground line contact hole cannot be represented in FIG. 9, but if necessary, it is preferable to refer to the conventional example shown in FIG.

See FIG. 10. 10- (1) By applying the CVD method, the thickness is, for example, 1500.
A second polycrystalline silicon film of [Å] is formed. 10- (2) The second polycrystalline silicon film is patterned by applying the resist process in the lithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas to form the ground line 8. Form.

See FIG. 11 11- (1) By applying the CVD method, the thickness is, for example, 1000.
The insulating film 9 made of SiO _{2 of} [Å] is formed on the entire surface. 11- (2) By applying the CVD method, the thickness is, for example, 500
A third polycrystalline silicon film of [Å] is formed. 11- (3) The dose amount is set to 1 × 1 by applying the ion implantation method.
0 ¹⁵ [cm ⁻² ], and the acceleration energy is 10 [k
eV], and P ions are implanted. 11- (4) By applying the resist process in the photolithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas, the third polycrystalline silicon film is patterned to form a TFT. The gate electrode 15 is formed.

See FIG. 12 12- (1) By applying the CVD method, the gate insulating film 16 of the TFT having a thickness of, for example, 200 [Å] and made of SiO ₂ is formed. 12- (2) CHF ₃ / He (for SiO ₂ ) and HB are used as the resist process and etching gas in the lithography technology.
By selectively applying the RIE method with r / Ar (for polycrystalline silicon), the gate insulating film 16, the gate electrode 15, which is the third polycrystalline silicon film, the insulating film 9, and the insulating film 7 are selectively etched. Then, a contact hole 16A reaching the gate electrode 4 of the driving transistor from the surface is formed. This step is the most characteristic step in this embodiment, and even if sufficient over-etching is performed so that there is no residue in the contact hole 16A, the base, that is,
The WSi film, which is the surface of the gate electrode 4, the first polycrystalline silicon film below the WSi film, the surface of the silicon semiconductor substrate 1, and the like are never damaged.

See FIG. 13 13- (1) By applying the CVD method, the thickness is, for example, 200.
A fourth polycrystalline silicon film of [Å] is formed. 13- (2) The dose amount is set to 1 by applying the resist process and the ion implantation method in the photolithography technique.
× 10 ¹⁴ [cm ⁻² ], and the acceleration energy was 5 [k
eV], B ions are implanted into the portions to be the source region and the drain region of the TFT. 13- (3) The source region of the TFT is patterned by patterning the fourth polycrystalline silicon film by applying the resist process in the lithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas. 17, drain region 1
8, a channel region 19, a _Vcc power supply level supply line, and the like are formed. Although the V _cc power supply level supply line cannot be represented in FIG. 13, it may be referred to the conventional example shown in FIG. 34 or FIG. 43, if necessary.

See FIG. 14 14- (1) By applying the CVD method, the thickness is, for example, 1000.
[Å] SiO ₂ insulating film and thickness, eg 50
An insulating film made of PSG of 00 [Å] is formed. Note that, also in this figure, as in FIG. 39, a two-layer insulating film is integrally shown, and this is referred to as an insulating film 21. 14- (2) A heat treatment for reflowing and flattening the insulating film 21 is performed. 14- (3) By applying the resist process in the lithography technique and the RIE method using CHF ₃ / He as the etching gas, the insulating film 21 and the like are selectively etched to form the bit line contact hole. Form. 14- (4) By applying the sputtering method, the thickness is, for example, 1
An Al film of [μm] is formed and is patterned by applying a normal photolithography technique to form the bit line 22.

As can be seen from the above description, FIG.
In the first embodiment of the present invention described with reference to FIG. 14,
The gate electrode of the driver transistor, the gate electrode of the TFT load, and the drain of the TFT load can be brought into contact with each other in a single mask step, and at the time of forming a contact hole that enables this, Even if over-etching is performed so that no residue is generated, there is no risk of damaging the base or substrate and degrading the characteristics of the memory cell. Incidentally, FIGS.
In the conventional example described for No. 4, two mask processes are required.

FIGS. 15 to 18 are sectional side views of a main part of the double gate TFT load type SRAM in the process steps for explaining the second embodiment of the present invention, respectively. Will be described in detail with reference to. 7 to 1
The same symbols as those used in FIG. 4 represent the same parts or have the same meanings, and from the beginning of the process in the embodiment described with reference to FIGS.
Up to (5), that is, T made of the third polycrystalline silicon film
Until the gate electrode 15 of the FT is formed, it is the same in this embodiment as well, so the description thereof will be omitted and the description will be given from the next step. Then, FIGS. 7 to 14 and FIGS.
The same symbols as those used in represent the same parts or have the same meanings. Incidentally, the description here will be referred to the steps of manufacturing the conventional double gate TFT load type SRAM described with reference to FIGS.

15- (1) Here, in the double gate TFT load type SRAM, the field insulating film 2, the gate insulating film 3 and the silicon semiconductor substrate 1 are provided.
WSi that is the first polycrystalline silicon film and the second conductive film
Gate electrode 4, n of driver transistor made of a film
⁺ -Source region 5, n ⁺ -drain region 6, n ⁺ -impurity region 6 ', insulating film 7, ground line 8 made of the second polycrystalline silicon film, lower gate electrode 15 in the TFT, T
It is assumed that the FT gate insulating film 16 is formed. 15- (2) By applying the CVD method, a thickness of, for example, 200
A fourth polycrystalline silicon film of [Å] is formed. 15- (3) The dose amount is set to 1 by applying the resist process and the ion implantation method in the photolithography technique.
× 10 ¹⁴ [cm ⁻² ], and the acceleration energy was 5 [k
eV], B ions are implanted into the portions to be the source region and the drain region of the TFT. 15- (4) By applying the resist process in the photolithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas, the fourth polycrystalline silicon film is patterned to form a TFT. A source region 17, a drain region 18, a channel region 19, and a _Vcc power supply level supply line (not visible in the figure) are formed.

See FIG. 16 16- (1) By applying the CVD method, the thickness is, for example, 500.
An insulating film 23 made of SiO _{2 of} [Å] is formed. 16- (2) CHF ₃ / He (for SiO ₂ ) is used as the resist process and etching gas in the photolithography technology.
And HBr / Ar (for polycrystalline silicon) are used to apply the insulating film 23, the drain region 18 of the TFT load, which is the fourth polycrystalline silicon film, the gate insulating film 16, and the third polycrystalline silicon film. Gate electrode 1 which is a crystalline silicon film
5, a contact which reaches the gate electrode 4 of the driving transistor made of the WSi film and the first polycrystalline silicon film from the surface by selectively etching the insulating film 9, the insulating film 9 and the insulating film 7.
The hole 23A is formed. This step is the most characteristic step in this embodiment.

See FIG. 17 17- (1) By applying the CVD method, the thickness is, for example, 500.
A fifth polycrystalline silicon film of [Å] is formed. 17- (2) By applying the thermal diffusion method, for example, P of 1 × 10 ²¹ [cm ⁻³ ] is diffused into the fifth polycrystalline silicon film. 17- (3) The fifth polycrystalline silicon film is patterned by applying the resist process in the photolithography technique and the RIE method using CCl ₄ / O ₂ as an etching gas to form a TFT. The upper gate electrode 24 is formed.

See FIG. 18 18- (1) By applying the CVD method, the thickness is, for example, 1000.
[Å] SiO ₂ insulating film and thickness, eg 50
An insulating film made of PSG of 00 [Å] is formed. Note that, also in this figure, as in FIG. 14, a two-layer insulating film is integrally shown, and this is referred to as an insulating film 25. 18- (2) A heat treatment for reflowing and flattening the insulating film 25 is performed. 18- (3) By applying the resist process in the photolithography technique and the RIE method in which the etching gas is CHF ₃ / He, the insulating film 25 and the like are selectively etched to contact the bit lines. Form a hole. 18- (4) By applying the sputtering method, the thickness is, for example, 1
An Al film of [μm] is formed and is patterned by applying a normal photolithography technique to form the bit line 26.

As can be seen from the description of FIGS. 15-18, it is clear that the present invention can be easily implemented in the case of a double gate TFT load, and in this embodiment as well, the contact When forming the holes, there is no possibility that the characteristics of the memory cell will be deteriorated by damaging the base or the substrate if over etching is performed so as not to generate a residue. 45 to 47.
Compared with the conventional example described above, the number of mask processes is reduced twice.

[0082]

The semiconductor memory device and the manufacturing method thereof according to the present invention include a pair of transfer transistors, a pair of driver transistors, and a pair of TFT loads.
And a memory cell having a connection region in which the drain and gate electrodes of the TFT load and the gate electrode of the driver transistor are connected to each other, wherein at least the drain and gate electrode of the TFT load and the driver transistor are provided in the connection region. Of the first conductive film and the gate electrode composed of the second conductive film made of a refractory metal are respectively laminated via an insulating film, and the laminated uppermost layer electrode is an intermediate electrode. It is connected on the side surface and is also connected to the lowermost layer electrode on its surface.

As is clear from the above description, in the present invention, the gate electrode of the driver transistor and the TFT
Since the gate electrodes of the load and the like can be connected to each other at the same location using the same contact hole, contact hole formation for interconnection between the driver transistor and the TFT load is not required. In the case of a normal TFT load type SRAM, it is possible to reduce the number of mask steps once compared with the conventional technique.
Further, when the double gate structure TFT load type SRAM is used, it is possible to reduce the number of masking steps by one time as compared with the conventional technique, and the contact
Even if sufficient over-etching is performed to eliminate the residue when forming the hole, there is no fear that the portion exposed at the bottom of the contact hole will be damaged and the characteristics of the memory cell will deteriorate. Therefore, this type of SRAM can be easily and easily manufactured with good characteristics and with good yield.

[Brief description of drawings]

FIG. 1 is a side sectional view of a main part of a semiconductor memory device in a process key point for explaining the principle of the present invention.

FIG. 2 is a side sectional view of a main part of a semiconductor memory device in a process key point for explaining the principle of the present invention.

FIG. 3 is a side sectional view of a main part of a semiconductor memory device in a process key point for explaining the principle of the present invention.

FIG. 4 is a side sectional view of a main part of a semiconductor memory device in a process key part for explaining the principle of the present invention.

FIG. 5 is a side sectional view of a main part of a semiconductor memory device in a process key point for explaining the principle of the present invention.

FIG. 6 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining the principle of the present invention.

FIG. 7 is a cutaway side view of a main part of a TFT load type SRAM in a process main part for explaining the first embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part of a TFT load type SRAM in a process essential part for explaining the first embodiment of the present invention.

FIG. 9 is a sectional side view of a main part of a TFT load type SRAM in a process main part for explaining the first embodiment of the present invention.

FIG. 10 is a cutaway side view of a main part of a TFT load type SRAM at a process main part for explaining the first embodiment of the present invention.

FIG. 11 is a cutaway side view of a main part of a TFT load type SRAM in a process main part for explaining the first embodiment of the present invention.

FIG. 12 is a cutaway side view of a main part of a TFT load type SRAM in a process main part for explaining the first embodiment of the present invention.

FIG. 13 is a sectional side view of a main part of a TFT load type SRAM in a process essential part for explaining the first embodiment of the present invention.

FIG. 14 is a cutaway side view of a main part of a TFT load type SRAM in a process main part for explaining the first embodiment of the present invention.

FIG. 15 is a side sectional view of a main part of a dual gate TFT load type SRAM in a process main part for explaining a second embodiment of the present invention.

FIG. 16 is a side sectional view of a main part of a double gate TFT load type SRAM in a process main part for explaining a second embodiment of the present invention.

FIG. 17 is a side sectional view showing a main part of a dual gate TFT load type SRAM in a process main part for explaining a second embodiment of the present invention.

FIG. 18 is a sectional side view of a main part of a double gate TFT load type SRAM in a process main part for explaining a second embodiment of the present invention.

FIG. 19 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 20 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 21 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 22 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 23 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 24 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 25 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 26 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 27 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 28 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 29 is a plan view of essential parts in the process essential part for explaining the conventional example of the method of manufacturing the high resistance load type SRAM.

FIG. 30 is a plan view of relevant parts in a process essential part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 31 is a plan view of relevant parts in a process essential part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 32 is a plan view of relevant parts in a process essential part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 33 is a plan view of relevant parts in a process essential part for explaining a conventional example of a method of manufacturing a high resistance load type SRAM.

FIG. 34 is a plan view of an essential part of a high resistance load SRAM completed through the steps described with reference to FIGS. 19 to 33;

FIG. 35 is an equivalent circuit diagram of a main part of the high resistance load type SRAM described with reference to FIGS. 19 to 34.

FIG. 36 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 37 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 38 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 39 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a TFT load type SRAM.

FIG. 40 is a plan view of essential parts in the process essential part for explaining the conventional example of the method of manufacturing the TFT load type SRAM.

FIG. 41 is a plan view of essential parts in the process essential part for explaining the conventional example of the method of manufacturing the TFT load type SRAM.

FIG. 42 is a plan view of essential parts in the process essential part for explaining the conventional example of the method for manufacturing the TFT load type SRAM.

FIG. 43 is a plan view of essential parts in the process essential part for explaining the conventional example of the method of manufacturing the TFT load type SRAM.

FIG. 44 is an equivalent circuit diagram of a main part of the TFT load type SRAM described with reference to FIGS. 36 to 43.

FIG. 45 is a cross-sectional side view of essential parts in a process essential part for explaining a conventional example of a method of manufacturing a dual-gate structure TFT-loaded SRAM.

FIG. 46 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a dual gate structure TFT load type SRAM.

FIG. 47 is a side sectional view of a main part in a process main part for explaining a conventional example of a method of manufacturing a dual gate structure TFT load type SRAM.

FIG. 48 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a case of forming a contact hole penetrating a multilayer stacked portion.

FIG. 49 is a sectional side view of the essential part of the semiconductor memory device in a process essential part for explaining the case of forming a contact hole penetrating a multilayer laminated portion.

FIG. 50 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a case of forming a contact hole penetrating a multilayer stacked portion.

FIG. 51 is a fragmentary side view of a semiconductor memory device in a process essential part for explaining a case of forming a contact hole penetrating a multilayer laminated portion.

FIG. 52 is a fragmentary side view of the semiconductor memory device in a process essential part for explaining the case of forming a contact hole penetrating a multilayer laminated portion.

FIG. 53 is a side sectional view of a main portion of a semiconductor memory device in a process key point for explaining a case of forming a contact hole penetrating a multilayer stacked portion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Field insulating film 3 Gate insulating film 3A Contact hole 4 Gate electrode 5 Source region 6 Drain region 6'Impurity region 7 Insulating film 8 Ground wire 9 Insulating film 15 Gate electrode 16 Gate insulating film 16A Contact hole 17 Source region 18 Drain region 19 Channel region 21 Insulating film 22 Bit line 23 Insulating film 23A Contact hole 24 Gate electrode 25 Insulating film 26 Bit line

Claims (8)

(57) [Claims] 1. A connection comprising a pair of transfer transistors, a pair of driver transistors, and a pair of TFT loads, wherein the drain and gate electrodes of the TFT loads and the gate electrodes of the driver transistors are mutually connected. A memory cell having a region, and in the connection region, at least a drain and a gate electrode of a TFT load, a first conductive film of a driver transistor and a gate formed of a second conductive film made of a refractory metal. The electrodes are laminated via an insulating film, respectively, and the laminated uppermost layer electrode is connected to the side surface of the intermediate electrode and the lowermost layer electrode is connected to the surface thereof. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the gate electrode of the driver transistor comprises a first conductive film and a second conductive film formed of a refractory metal silicide laminated thereon. . 3. Each electrode in the connection region is a top layer T
3. The semiconductor memory device according to claim 1, comprising a drain of the FT load, a gate electrode of the TFT load which is an intermediate layer, and a gate electrode of a driver transistor which is the lowermost layer. 4. A gate electrode in a TFT load is formed above and below a channel region through an insulating film, and each electrode in a connection region is an uppermost layer. An upper gate electrode of the TFT load and an intermediate layer. 3. The semiconductor memory device according to claim 1, further comprising a drain of the TFT load, a lower gate electrode, and a gate electrode of a driver transistor which is a lowermost layer. 5. A field insulating film is formed on a first region of a surface of a semiconductor substrate, and the half is defined by the first region.
A step of forming a gate insulating film in the second region on the surface of the conductor substrate ; and, subsequently, growing the first conductive film and the second conductive film made of a refractory metal in order and then patterning the same to form a driver transistor. forming a gate electrode, then the field insulating film and the gate electrode after forming the impurity regions perform the introduction of impurities into the semiconductor substrate as a mask, wherein said second conductive film on the
A step of depositing and forming a first insulating film on a semiconductor substrate , and then growing and patterning a third conductive film on the first insulating film , and then forming a third conductive film on the surface of the third conductive film . A step of forming a second insulating film, and then the second insulating film, the third conductive film, and the first conductive film.
Patterning and removing the insulating film of
Exposed on the surface and the third conductive film exposed on the side surface.
A step of forming an opening, and then the second conductive film exposed on the bottom surface of the opening and the second conductive film.
An electrical contact is made with the third conductive film exposed on the side surface of the opening.
And extend from within the opening to outside the opening.
So as to pass through the third conductive film on the upper surface Te, it includes a step of patterning by forming a fourth conductive film, and the third conductive film and the fourth conductive film are overlapped
In the region, a channel region for the TFT load will be formed.
In any of the above steps,
Of the third conductive film and the fourth conductive film.
It is constructed by selectively introducing conductive impurities into either side.
Method for manufacturing semiconductor memory device. 6. A step of forming a gate electrode of a driver transistor by sequentially growing a first conductive film and a second conductive film made of a refractory metal silicide and then performing patterning. The method for manufacturing a semiconductor memory device according to claim 5. 7. A field in a first region on the surface of a semiconductor substrate.
Forming an insulating film and defining the half defined by the first region
A process to form a gate insulating film on the second area of the conductor substrate surface.
And then a second conductive layer consisting of the first conductive film and the refractory metal.
The film is grown in order, then patterned and dried.
The step of forming the gate electrode of the gate transistor, and then the field insulating film and the gate electrode.
As impurities, impurities are introduced into the semiconductor substrate
Forming a region, including on the second conductive film,
A step of depositing and forming a first insulating film on a semiconductor substrate, and then growing a third conductive film on the first insulating film.
After patterning, a second layer is formed on the surface of the third conductive film.
And the step of forming a fourth conductive film on the second insulating film.
After patterning, selectively in the fourth conductive film
Is introduced into the surface of the fourth conductive film.
A step of forming a third insulating film, and then the third insulating film, the fourth conductive film, and the second conductive film.
Patterning the insulating film, the third conductive film, and the first insulating film.
By removing the second conductive film by exposing the bottom surface of the second conductive film.
And forming an opening exposing the third conductive film on the side surface.
Process, and then the second conductive film exposed on the bottom surface of the opening and the second conductive film.
The third conductive film and the fourth conductive film exposed on the side surfaces of the opening, respectively.
In electrical contact with the conductive film and in the opening
From the opening to the outside of the opening
The fifth conductor so that it passes over the region where the impurity is introduced.
Forming a conductive film and patterning the conductive film, and a region of the fourth conductive film into which the conductive impurities are introduced.
And the fifth conductive film in the region where they overlap with each other.
A channel region is formed and configured to serve as a TFT load.
Manufacturing method of semiconductor memory device. 8. A first conductive film and a refractory metal silicide
A second conductive film consisting of
To form the gate electrode of the driver transistor
The process according to claim 7, which further comprises a step of
Manufacturing method of semiconductor memory device.