JPH05121695A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To make cell ratio sufficiently high, and improve characteristics of data, by making impurity concentration in the drain region of a transfer gate transistor constituting a memory cell low, as compared with the impurity concentration in the drain region of a driver transistor. CONSTITUTION:Ion implantation method wherein a VSS power supply level feeding line 5, a gate electrode 61, a gate electrode 62 and a gate electrode 7 are used as masks is applied, and phosphorus is implanted by setting dosage and ion acceleration energy at, e.g. 1X10<13> [cm<2>]]and 60 [KeV], respectively, thereby forming a source region 8TG and a drain region 9Tg of a transfer gate electrode, and a source region 8OR and a drain region 9DR of a driver transistor. Ion implantation using resist film 22 as a mask is applied, and arsenic is implanted, thereby increasing impurity concentration of regions of the transfer gate transistor except the drain region 9TG.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (s) composed of a flip-flop circuit and a transfer gate transistor.
tatikrandom access memory
y: SRAM) and a method of manufacturing the same. At present, in the flip-flop circuit of SRAM, the one to which high resistance is added is widely used because of its good integration property, and its practicality is very high.
There is still room for improvement. For example, the ratio of the current drive capacity of the driver transistor to the current drive capacity of the transfer gate transistor, that is, high integration and stable operation are possible while maintaining a high cell ratio. I have to

[0002]

2. Description of the Related Art FIG. 20 is a circuit diagram of a main part for explaining a high resistance load type memory cell in an ordinary SRAM. In the figure, T ₁ and T ₂ are driver transistors, R ₁ and R ₂ are load resistors, T ₃ and T ₄ are transfer gate transistors, WL is a word line, BL
And / BL are bit lines, and V _CC is the positive power supply level.

In this high resistance load type memory cell, in order to obtain good retention characteristics of stored information, the current driving capability of the driver transistors T ₁ and T ₂ is set to the transfer gate transistor T ₃ and It is necessary to make the current drive capacity of T ₄ about three times or more.

The reason for doing this is that when the memory cell is selected according to the word line WL, the bit lines BL and / B are selected.
Depending on the potential at L, the driver transistor T ₁
And T ₂ may be affected and the data may be inverted.

From the above, in order to obtain the cell ratio between the driver transistors T ₁ and T ₂ and the transfer gate transistors T ₃ and T ₄ , the driver
The channel widths of the transistors T ₁ and T ₂ are made larger than the channel widths of the transfer gate transfer gates T ₃ and T ₄ , and the current driving capability of the driver transistors T ₁ and T ₂ is transferred.・
Gate transistors T ₃ and either increase compared to T _4, or, without changing the in channel width in the driver transistors T ₁ and T _2, the channel length of the transfer gate transistors T ₃ and T ₄ Big things are being done.

[0006]

As described above, by increasing the channel width of the driver transistors T ₁ and T ₂ or increasing the channel length of the transfer gate transistors T ₃ and T ₄ , the cell If you take measures to keep the ratio high, it goes without saying that memory,
The cell size becomes large and goes against the demand for high integration. In addition, in order to maintain a high cell ratio, the transfer gate
It is conceivable to reduce the channel width of the transistors T ₃ and T ₄ , but in such a case, a narrow channel effect appears and stable operation cannot be obtained.

As described above, in the high resistance load type SRAM according to the conventional technique, obtaining good retention characteristics of stored information and maintaining a high degree of integration include trade-offs. There is.

The present invention intends to improve the data retention characteristics in a semiconductor memory device and also improve the integration property.

[0009]

According to the present invention, a driver
To increase the cell ratio of the transistor and transfer gate transistor, positively decrease the current driving capability of the transfer gate transistor, specifically, increase the parasitic resistance in the transfer gate transistor. Take the means to make.

Therefore, in the semiconductor memory device and the manufacturing method thereof according to the present invention, (1) a transfer gate forming a memory cell
The impurity concentration in the drain region (eg, drain region 9 _TG ) of the transistor (eg, transfer gate transistors T ₃ and T ₄ ) is the drain region (eg, drain) of the driver transistor (eg, driver transistors T ₁ and T ₂ ). It is characterized in that it is lower than the impurity concentration in the region _9DR ), or

(2) In the above (1), the source region (eg source region 8 _TG ) of the transfer gate transistor is surrounded by the same low impurity concentration region as the drain region (eg drain region 9 _DR ). Characterized by comprising a region of high impurity concentration, or

(3) In the above (1), the impurity concentration in the source region of the transfer gate transistor is higher than the impurity concentration in the drain region. Alternatively,

(4) An impurity having a lower concentration than the impurity concentration in the drain region of the driver transistor is introduced into a portion where a drain region of the transfer gate transistor forming the memory cell is to be formed, to transfer the transfer gate transistor. Characterized in that it comprises a step of forming a drain region of the gate transistor, or

(5) A driver forming a memory cell
A step of introducing a predetermined low concentration impurity into each source region formation planned portion and each drain region formation planned portion of the transistor and the transfer gate transistor, and then forming a mask covering the drain region of the transfer gate transistor. From the step of forming the high concentration impurity region in each of the other low concentration impurity regions except the drain region of the transfer gate transistor.
Alternatively,

(6) The drain region of the transfer gate transistor forming the memory cell is covered with a mask except for the portion where the drain region is to be formed, and then an impurity of a predetermined low concentration is introduced. Then, after removing the mask, only the drain region of the transfer gate transistor is covered with a mask to introduce impurities of a higher concentration than the predetermined low concentration to form other regions. And a process are included.

[0016]

By adopting the above means, the cell ratio can be sufficiently high to improve the data retention characteristics, and it is not necessary to change the area of the memory cell. In order to realize the structure without deteriorating the characteristics, the technique which has been widely used in the past is applied, and the impurity concentration of the drain region in the transfer gate transistor is set to the drain concentration in the driver transistor. Since it suffices to make the impurity concentration relatively lower than the impurity concentration in the region, it is extremely simple and easy.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 10 are side sectional views of a main part of a semiconductor memory device at a process step for explaining a first embodiment of the present invention, and FIGS. 1 is a plan view of a main part of a semiconductor memory device at a process step for explaining a first embodiment of the present invention, which will be described in detail below with reference to these figures. 1 to 10 correspond to the state of being cut along the line YY seen in FIGS. 11 to 15. Also, the same symbols as those used in FIG. 20 represent the same parts or have the same meanings. Furthermore, in the plan views of the main parts of FIGS. 11 to 15, the insulating film is omitted and only the contact holes are shown for the sake of clarity.

1 and 11 1- (1) Selective thermal oxidation (loc) using a Si ₃ N ₄ film formed on an extremely thin SiO ₂ film as an oxidation resistant mask film
al oxidation of silicon: L
By applying the OCOS method, the field insulating film 2 made of SiO ₂ having a thickness of, for example, 600 [nm] is formed on the p-type silicon semiconductor substrate 1. 1- (2) The gate insulating film 4 made of SiO _{2 having} a thickness of 25 nm, for example, is formed by applying the thermal oxidation method after removing the oxidation resistant mask film to expose the active region 3. To form.

2 and 11 2- (1) By applying a resist process in the lithography technique, a resist film 21 having an opening 21A is formed at a required position. 2- (2) Reactive ion etching (reactive i) using CHF ₃ -containing etching gas
on etching (RIE) method, the gate insulating film 4 and the field insulating film 2 are selectively etched to contact holes C ₁ , C ₂ , C.
Form ₃ , C ₄ and C ₅ .

See FIGS. 3 and 12 3- (1) Chemical vapor deposition
By applying the r deposition (CVD) method, a polycrystalline silicon film having a thickness of, for example, 400 [nm] is formed. 3- (2) The polycrystalline silicon film formed in step 3- (1) is patterned by applying the RIE method using an etching gas containing SF ₆ as a gas, and V
_SS power level supply line 5, gate electrodes 6 _{1 and} 6 ₂ in the driver transistor, and gate electrode 7 in the transfer gate transistor which is the word line WL
To form. When the driver transistors T _{1 and} T ₂ and the transfer gate transistors T _{3 and} T ₄ shown in FIG. 20 are each represented by a gate electrode, the driver transistor T ₁ has a gate electrode 6
₁ , the driver transistor T ₂ has a gate electrode 6
₂ , the transfer gate transistors T _{3 and} T ₄ correspond to the gate electrode 7, respectively.

4 and 12, 4- (1) V _SS power supply level supply line 5, gate electrode 6 ₁ ,
By applying the ion implantation method using the gate electrodes 6 ₂ and 7 as masks, the dose amount is set to, for example, 1 × 1.
0 ¹³ [cm ⁻² ], the ion acceleration energy is, for example, 60 [ke
V] is implanted with phosphorus (P) to form the source region 8 _{TG and the} drain region 9 _TG in the transfer gate transistor and the source region 8 _{DR and the} drain region 9 _{DR in} the driver transistor. .. 4- (2)

5 and FIG. 12 5- (1) By applying the resist process in the lithography technique, the resist film 22 covering the drain region 9 _TG in the transfer gate transistor and its vicinity is formed. Form. 5- (2) The dose amount is, for example, 4 × 10 ¹⁵ [cm] by applying the ion implantation method using the resist film 22 as a mask.
^-2 ], arsenic (As) is implanted by setting the ion acceleration energy to, for example, 70 [keV] to increase the impurity concentration in regions other than the drain region 9 _TG in the transfer gate transistor. In the figure, for the sake of simplicity, a region having a high impurity concentration is indicated by the same symbol as the original region having a low impurity concentration. In FIG. 5, the source region 8 _{DR in the} transfer gate transistor is The state where the impurity concentration is increased is shown.

6 and FIG. 13 6- (1) By applying the CVD method, the interlayer insulating film 10 made of SiO ₂ having a thickness of, for example, 100 nm is formed. 6- (2) R using the resist process and etching gas in the lithographic technique as CHF ₃ -containing gas
By applying the IE method, the interlayer insulating film 10 is selectively etched to form the contact holes C ₆ and C ₇ .

7 and FIG. 14 7- (1) By applying the CVD method, a non-doped polycrystalline silicon film having a thickness of, for example, 200 nm is formed. 7- (2) By applying the resist process in the lithography technique, the load resistance of the driver transistors T ₁ and T _{2 in} the polycrystalline silicon film formed in the step 7- (1) By masking a portion to be formed and then applying an ion implantation method, ions of an n-type impurity such as As or P are dosed at 8 × 10 ¹⁵ [cm
^-2 ], so that the ion acceleration energy is 50 [keV]. The part where this ion is implanted is V _CC
It becomes the power level supply line.

7- (3) By applying the resist process in the lithography technique and the RIE method using the etching gas as a gas containing SF ₆ , the above-mentioned step 7-
By patterning the polycrystalline silicon film formed in (1), V _CC power supply level supply line 11, load resistances R _{1 and} R
Form ₂ . Since the process 7- (2) has been performed, the V _CC power level supply line 11 is doped with impurities at a high concentration and thus has a low resistance, but the load resistances R ₁ and R ₂ are High resistance is maintained as it is with undoped polycrystalline silicon.

See FIG. 8. 8- (1) By applying the CVD method, the interlayer insulating film 12 made of SiO _{2 having} a thickness of 200 nm and the phosphosilicate glass (phosp) having a thickness of 800 nm are used.
An interlayer insulating film 13 made of ho-silicate glass (PSG) is sequentially formed.

9 and 15 9- (1) R in which the resist process and etching gas in the lithography technique are CHF ₃ -containing gas
By applying the IE method, the interlayer insulating films 13 and 1
2 is selectively etched to form contact holes C ₈ and C ₉ . The contact holes C ₈ and C ₉ are formed by transferring a bit line made of, for example, Al.
It is for contacting the drain region 9 _TG of the gate transistor.

See FIG. 10. 10- (1) By applying the heat treatment method, PSG
Of the interlayer insulating film 13 and contact holes C
Perform reflow to smooth the edges of ₈ and C ₉ .
It should be noted that this step may be inserted if necessary. 10- (2) By applying the sputtering method,
An Al film having a thickness of, for example, 1 [μm] is formed. 10- (3) The Al film formed in step 10- (2) is patterned by applying a normal lithography technique to form the bit lines BL and / BL.

In the semiconductor memory device thus completed, it goes without saying that the resistance value in the drain region 9 _TG in the transfer gate transistor is large.

FIG. 16 shows a transfer gate transistor T in a memory cell manufactured according to the present invention.
₃ is a diagram in which the gate voltage [V] vs. drain current [mA] characteristics relating to ₃ or T ₄ are actually measured, and the horizontal axis represents the gate voltage [V] and the vertical axis represents the drain current [m].
A] are taken respectively. In the figure, A is a characteristic line of a transfer gate transistor manufactured according to the embodiment of the present invention, and B is a characteristic line of a transistor of the same dimension manufactured without carrying out the present invention. ..

From the figure, it is clear that according to the present invention, the cell ratio of the driver transistor and the transfer gate transistor can be obtained.

FIG. 17 is a sectional side view of a main part of a semiconductor memory device at a process step for explaining the second embodiment of the present invention. The symbols used in FIGS. The same symbol represents the same part or has the same meaning.
In this embodiment, in order to increase the impurity concentration in the process described with reference to FIG. 5 in the first embodiment, that is, in the regions other than the drain regions 9 _{TG of} the transfer gate transistors T ₃ and T _4. The process of performing the ion implantation of
Similar to the process of forming the source region and the drain region of the DD (lightly doped drain) structure, the side wall 23 made of SiO ₂ is formed on the side surface of the gate electrode 7, and the high impurity concentration region 24 is formed in the gate electrode 7.
It should be pulled away from. According to this, in this embodiment, the cell ratio can be improved by incorporating the LDD structure used for preventing the short channel effect, which is a problem when highly integrated, without increasing the number of steps.

FIGS. 18 and 19 are side sectional views of a main part of the semiconductor memory device in the process steps for explaining the third embodiment of the present invention, which are used in FIGS. The same symbols as those used to represent the same parts or have the same meanings.

In the present embodiment, in the step described with reference to FIGS. 4 and 5 in the first embodiment, that is, the step of forming the source region and the drain region in each transistor, the transfer gate. Transistors T ₃ and T ₄
In this case, only the drain region _9TG is formed independently with a low impurity concentration, and the other source regions and drain regions are formed with a high impurity concentration from the beginning.

See FIG. 18 18- (1) By applying a resist process in the lithography technique, a region to be formed other than the drain region forming portion of the transfer gate transistor is covered with the resist film 25. 18- (2) By applying the ion implantation method, phosphorus (P) is implanted with a dose amount of, for example, 1 × 10 ¹³ [cm ⁻² ] and an ion acceleration energy of, for example, 60 [keV]. To form the drain region 9 _TG in the transfer gate transistor.

19- (1) By removing the resist film 25 and then applying a resist process in the lithography technique again, the resist film is formed on the drain region 9 _TG of the transfer gate transistor. Cover with 26. 19- (2) By applying the ion implantation method, the dose is set to, for example, 4 × 10 ¹⁵ [cm ⁻² ], and the ion acceleration energy is set to, for example, 70 [keV] to implant As to drive the driver. - in the source region and the drain region in the transistor, and the like are formed transfer gate transistor in the source region 8 _TG.

In this embodiment, this makes it possible to further improve the cell ratio as compared with the above embodiments.

In the present invention, many modifications can be made in addition to the above-described embodiments. For example, in each of the embodiments, the gate electrode of each transistor is made of polycrystalline silicon. It is optional to substitute polycide, etc., and the high resistance is used for the load of the driver transistor in each of the above embodiments, but it may be a transistor load type.

[0039]

In the semiconductor memory device and the method of manufacturing the same according to the present invention, the impurity concentration in the drain region of the transfer gate transistor forming the memory cell is in the drain region of the driver transistor. It is made lower than the impurity concentration.

By adopting the above-mentioned structure, the cell ratio can be sufficiently high to improve the data retention characteristics, and it is not necessary to change the area of the memory cell. It doesn't get worse,
Moreover, in order to realize the configuration, a technique which has been frequently used is applied to compare the impurity concentration of the drain region in the transfer gate transistor with the impurity concentration of the drain region in the driver transistor. It is extremely simple and easy because it is sufficient to make it relatively low.

[Brief description of drawings]

FIG. 1 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a first embodiment of the present invention.

FIG. 2 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a first embodiment of the present invention.

FIG. 3 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a first embodiment of the present invention.

FIG. 4 is a cutaway side view of a main part of the semiconductor memory device at a process key point for explaining the first embodiment of the present invention.

FIG. 5 is a cutaway side view of a main part of a semiconductor memory device in a process main part for explaining a first embodiment of the present invention.

FIG. 6 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a first embodiment of the present invention.

FIG. 7 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a first embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part of the semiconductor memory device in a process main part for explaining the first embodiment of the present invention.

FIG. 9 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a first embodiment of the present invention.

FIG. 10 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a first embodiment of the present invention.

FIG. 11 is a plan view of a main portion of the semiconductor memory device in a process main part for explaining the first embodiment of the present invention.

FIG. 12 is a plan view of a main portion of the semiconductor memory device in a process key point for explaining the first embodiment of the present invention.

FIG. 13 is a main-portion plan view of the semiconductor memory device in a process main point for explaining the first embodiment of the present invention.

FIG. 14 is a plan view of a main portion of the semiconductor memory device in a process main part for explaining the first embodiment of the present invention.

FIG. 15 is a main-portion plan view of the semiconductor memory device in a process main point for explaining the first embodiment of the present invention.

FIG. 16 is a transfer gate transistor T ₃ or T in a memory cell manufactured according to the present invention.
It is the diagram which measured and represented the gate voltage [V] -drain current [mA] characteristic regarding ₄ .

FIG. 17 is a cutaway side view of a main part of a semiconductor memory device at a process key point for explaining a second embodiment of the present invention.

FIG. 18 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a third embodiment of the present invention.

FIG. 19 is a side sectional view of a main part of a semiconductor memory device in a process main part for explaining a third embodiment of the present invention.

FIG. 20 is a main part circuit diagram for explaining a high resistance load type memory cell in a normal SRAM.

[Explanation of symbols]

1 p-type silicon semiconductor substrate 2 field insulating film 3 active region 4 gate insulating film 5 _VSS power level supply line 6 ₁ gate electrode 6 ₂ gate electrode 7 gate electrode 8 source region in _DR driver transistor 8 _TG transfer gate・ Source region in transistor 9 _DR region in transistor _DR driver 9 Drain region in _TG transfer gate transistor 10 Interlayer insulation film 11 V _CC power level supply line 12 Interlayer insulation film 13 Interlayer insulation film 21 Resist Film 21A Opening 22 Resist film 23 Sidewall 24 High impurity concentration region T ₁ driver transistor T ₂ driver transistor R ₁ load resistor R ₂ load resistor T ₃ transfer gate transistor T ₄ transfer gate transistor WL word line B Bit line / BL the bit line V _CC positive supply level C ₁ contact hole C ₂ contact hole C ₃ contact hole C ₄ contact hole C ₅ contact hole C ₆ contact hole C ₇ contact hole

Claims (6)

[Claims] 1. A semiconductor characterized in that an impurity concentration in a drain region of a transfer gate transistor constituting a memory cell is lower than an impurity concentration in a drain region of a driver transistor. Storage device. 2. The semiconductor memory device according to claim 1, wherein the source region of the transfer gate transistor is formed of a region of high impurity concentration surrounded by a region of the same low impurity concentration as the drain region. 3. The semiconductor memory device according to claim 1, wherein the impurity concentration in the source region of the transfer gate transistor is higher than the impurity concentration in the drain region. 4. A transfer gate transistor, which comprises a memory cell, wherein an impurity having a concentration lower than that of an impurity concentration in a drain region of a driver transistor is introduced into a portion to be formed in a drain region of the transfer gate transistor. A method of manufacturing a semiconductor memory device, which comprises the step of forming a drain region of a transistor. 5. A step of introducing a predetermined low-concentration impurity into each source region formation scheduled portion and each drain region formation scheduled portion of a driver transistor and a transfer gate transistor which constitute a memory cell, and then a transfer step. Forming a mask covering the drain region of the gate transistor and introducing impurities again to form high concentration impurity regions in the other low concentration impurity regions other than the drain region of the transfer gate transistor; A method of manufacturing a semiconductor memory device, comprising: 6. A drain region of the transfer gate transistor is formed by covering a portion of the transfer gate transistor constituting the memory cell other than a portion where a drain region is to be formed with a mask and introducing a predetermined low concentration of impurities. And then removing the mask before transferring the transfer
A step of covering only the drain region of the gate transistor with a mask to form other regions by introducing an impurity having a higher concentration than the predetermined low concentration, and forming other regions. Production method.