KR960015786B1 - Semiconductor device and fabricating method thereof - Google Patents

Abstract

None.

Description

Semiconductor device and manufacturing method thereof

1 is a cross-sectional structure diagram of a memory cell of an SRAM according to a first embodiment of the present invention.

FIG. 2 is a first process diagram showing the manufacturing process of the memory cell shown in FIG.

FIG. 3 is a second process chart showing the manufacturing process of the memory cell shown in FIG.

FIG. 4 is a third process chart showing the manufacturing process of the memory cell shown in FIG.

FIG. 5 is a fourth process chart showing the manufacturing process of the memory cell shown in FIG.

FIG. 6 is a fifth process chart showing the manufacturing process of the memory cell shown in FIG.

FIG. 7 is a sixth process diagram showing a manufacturing process of the memory cell shown in FIG.

FIG. 8 is a seventh process diagram showing the manufacturing process of the memory cell shown in FIG.

FIG. 9 is an eighth process diagram showing the manufacturing process of the memory cell shown in FIG.

10 is a cross-sectional structure diagram of a memory cell of an SRAM according to a second embodiment of the present invention.

FIG. 11 is a first process diagram showing the main manufacturing process of the memory cell shown in FIG.

FIG. 12 is a second process diagram showing the main manufacturing process of the memory cell shown in FIG.

13 is a cross-sectional structure diagram of a semiconductor device according to the third embodiment of the present invention.

Fig. 14 is a planar structure diagram showing a planar structure of a lower layer portion of a memory cell of a conventional SRAM.

Fig. 15 is a planar structure diagram showing a planar structure of an upper layer portion of a memory cell of a conventional SRAM.

FIG. 16 is a cross-sectional structural view of the memory cell in the direction along the cutting line X-X in FIGS. 14 and 15. FIG.

17 is an equivalent circuit diagram of a memory cell of an SRAM.

FIG. 18 is a cross sectional view of the production process showing one manufacturing process of the memory cell shown in FIG.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 7: n ⁺ source / drain region

8a: wiring layer 9: interlayer insulating layer

10: direct contact 11: titanium silicide layer

15 silicon plug layer 16 openings

20a, 20b: n-channel MOS transistor for driving

21a, 21b: p-channel MOS thin film transistor for load

22a, 22b: n-channel MOS transistor for transmission

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the improvement of the contact structure of wiring in a high stepped region in a semiconductor device having a multilayer wiring structure.

In the field of semiconductor devices, there is a demand for improvement of the degree of integration and miniaturization of device structures.

In response to this demand, a structure in which a plurality of elements are three-dimensionally stacked on a surface of a semiconductor substrate has been devised.

While such a stacked semiconductor device improves the degree of integration of the main surface of the semiconductor substrate, some problems have been pointed out due to the arrangement of the stepped undulation of the wiring layer in a severe area.

As an example of a semiconductor device having a structure in which semiconductor elements are stacked on a substrate, a structure of an SRAM (static random access memory) will be described.

14 to 16 show a "4MSRAM memory cell using a polysilicon thin film transistor (TFT)" Tsumi et al., KI1. 90, no. 48. The structure of a memory cell of a CMOS type SRAM using a thin film transistor as a load disclosed in p7 to p13 is disclosed.

17 is an equivalent circuit diagram of a memory cell of an SRAM.

Referring to FIG. 17, a memory cell of a CMOS type SRAM has a pair of CMOS inverters.

One CMOS inverter has a driving n-channel MOS transistor 20a and a load p-channel MOS thin film transistor 21a.

The other CMOS inverter has a driving n-channel MOS transistor 20b and a load p-channel MOS thin film transistor 21b.

The gates of the transistors 20a and 21b of one CMOS inverter are connected to the memory nodes 25b common to each of the transistors 20b and 21b of the other CMOS inverter. Are connected to the common storage node 25a of one of the CMOS inverter transistors 20a and 21a to form a flip-flop circuit.

The source of the load p-channel MOS thin film transistors 21a and 21b is connected to the power source 23. Each of the n-channel MOS transistors 20a and 20b for driving is grounded.

The n-channel MOS transistors 22a and 22b for transfer are connected to the storage nodes 25a and 25b of the flip-flop circuit, respectively.

Gates of the n-channel MOS transistors 22a and 22b for transmission are connected to the word line 27.

The drain regions of the n-channel MOS transistors 22a and 22b for transfer are connected to the bit lines 26a and 26b, respectively.

A case of writing information into a memory cell will be described.

For example, when the memory node 25a is set to the ground potential and the memory node 25b is set to the power source potential, the bit line 26a is set to the ground level and the bit line 26b is set to the power supply level. The n-channel MOS transistors 22a and 22b for transmission are turned on by applying a predetermined potential.

The case where information is read from the memory cell will be described.

The bit lines 26a and 26b are connected to the sense amplifier circuit.

In this state, a predetermined potential is supplied to the word line 27 to turn on the transfer n-channel MOS transistors 22a and 22b.

By this operation, the potentials of the storage nodes 25a and 25b read the bit lines 26a and 26b. Next, the specific structure of the memory cell of the SRAM will be described with reference to FIGS.

14 and 15 are planar structural diagrams of memory cells. For convenience of description, the memory cell is divided into a lower layer and an upper layer of the substrate, and FIG. 14 shows a planar structure of the lower layer of the memory cell, and FIG. .

16 is a cross-sectional structural view in the direction along cut line X-X in FIGS. 14 and 15.

14 to 16, the memory cells of the SRAM are driven n-channel MOS transistors 20a and 20b and a n-channel MOS transistor 22a for transfer in the lower region close to the surface of the silicon substrate 1. ) And (22b) are arranged.

Load p-channel MOS thin film transistors 21a and 21b are arranged in the upper region formed on the main surface of the silicon substrate 1 via the interlayer insulating layer 9.

Referring to FIG. 16, the P well region 2 is formed on the surface of the silicon substrate 1.

The field oxide film 4 and the channel stop region 3 are formed in the element isolation region on the main surface of the P well region 2.

The n-channel MOS transistor 22b for transferring the driving n-channel MOS transistor 20a includes n ⁺ source / drain regions 7 and 7, a gate oxide film 5, and a gate electrode 6, respectively.

The gate electrode 6 has a polyside structure composed of a polycrystalline silicon layer and a metal silicide film formed on its surface.

The surface of the silicon substrate 1 is covered with a thick interlayer insulating layer 9.

On the surface of the interlayer insulating layer 9, a load p-channel MOS thin film transistor 21b is formed.

The thin film transistor 14 includes the gate electrode 8b formed on the surface of the interlayer insulating layer 9 and the gate oxide film 13 covering the surface of the gate electrode 8b and the P ⁺ source / drain regions 12a and 12c. ) And a channel region 12b.

The P ⁺ source / drain regions 12a and 12c and the channel region 12b are formed in a thin polycrystalline silicon layer having a thickness of about 200A.

The gate electrode 8b and P-type impurities are also included.

Next, the wiring structure of the storage node 25b to which the driving n-channel MOS transistor 20a formed in the lower layer, the transfer n-channel MOS transistor 22b, and the load p-channel MOS transistor 21b formed in the upper layer are connected. Explain.

Openings 16 are formed in the interlayer insulating layer 9.

The n ⁺ source / drain region 7 of the gate electrode 6 of the driving n-channel MOS transistor 20a and the transfer n-channel MOS transistor 22b is exposed inside the opening 16.

A wiring layer 8a made of polycrystalline silicon is formed in the opening 16 so that the gate electrode 6 of the n-channel MOS transistor 20a for driving and the n ⁺ source / drain of the n-channel MOS transistor 22b for transmission are formed. It is connected to the area | region 7 simultaneously.

Such a contact structure is called a shared contact.

Part of the wiring layer 8a extends on the surface of the interlayer insulating layer 9.

Thus, the polycrystalline silicon layer constituting the P ⁺ source / drain region 12a of the load P-channel MOS thin film transistor 21b is connected to the surface of the wiring layer 8a.

The wiring layer 8a is made of polycrystalline silicon and contains P-type impurities therein for obtaining conductivity.

At the bottom of the opening 16, a titanium silicide layer 11 is formed between the wiring layer 8a and the source / drain region 7.

The titanium silicide layer 11 prevents the pn junction from being formed by directly connecting the P-type wiring layer 8a and the n ⁺ source / drain regions 7.

In addition, the structure in which the wiring layer 8a disposed on the surface of the interlayer insulating film 9 is connected to the impurity region formed in the lower layer, for example, the silicon substrate, through the opening 16 is called direct contact.

However, in the case of forming a large direct contact structure with a high step like the wiring layer 8a used in the memory cell of the SRAM described above, a problem arises in that the patterning of the wiring layer becomes difficult.

FIG. 18 is a cross-sectional view showing the manufacturing process for forming the wiring layer 8a shown in FIG.

After the openings 16 are formed in the interlayer insulating layer 9, the polycrystalline silicon layer 8 is deposited on the entire surface by, for example, CVD.

Next, a resist is applied on the surface of this polycrystalline silicon layer 8.

Then, the resist is exposed to a predetermined pattern shape using the photolithography method, and then the film is loosened to form a resist mask.

Thereafter, the polycrystalline silicon layer 8 is etched using a resist mask to form the wiring layer 8a and the gate electrode 8b of the thin film transistor 14.

As shown in the figure, the polycrystalline silicon layer 8 is formed on the surface of the interlayer insulating layer 9 with severe stepped undulations.

In particular, the step of the polycrystalline silicon layer is large in the vicinity of the opening 16.

As described above, it is very difficult to form a fine resist mask on the surface of the polycrystalline silicon layer 8 having a large step by using an exposure technique.

In recent years, the exposure apparatus tends to be shallow in depth of focus.

Therefore, a problem arises in that the resolution of the resist mask is lowered and the pattern of the wiring layer 8a made of the polycrystalline silicon layer becomes unclear.

The deterioration of the accuracy of the wiring pattern inhibits the miniaturization of the wiring size and lowers the reliability of the wiring.

Therefore, an object of the present invention is to provide a wiring structure and a method of manufacturing the same, which are made to solve the above problems and which can improve the reliability of a multilayer wiring structure having a contact portion having a stepped relief.

A semiconductor device according to an aspect of the present invention includes a silicon layer and an interlayer insulating layer formed on the surface of the silicon layer and having contact holes.

The silicon plug layer is embedded in the contact hole.

On the surface of the silicon plug layer, an intermediate conductive layer made of either high melting point metal or high melting point metal silicide is formed.

The wiring layer made of polycrystalline silicon formed on the surface of the interlayer insulating layer is connected to this intermediate conductive layer.

A semiconductor memory device according to another aspect of the present invention has a pair of first and second CMOS inverters connected to form a flip-flop circuit and first and second transfer MOS transistors connected to each node point of the flip-flop circuit. A memory cell is provided.

The first CMOS inverter includes a first thin film transistor of the second conductivity type formed on the surface of the interlayer insulating layer formed on the main surface of the silicon substrate.

The second CMOS inverter has a first conductive MOS transistor of the first conductive type formed on the main surface of the silicon substrate and a second thin film transistor of the second conductive type formed on the surface of the interlayer insulating layer.

Further, a first transfer MOS transistor and a second transfer MOS transistor are formed on the main surface of the silicon substrate.

The gate electrode of the first MOS transistor, the source / drain region of the second transfer MOS transistor, and the source / drain region of the second thin film transistor are connected to each other by first wiring means.

The gate electrode of the second driving MOS transistor, the source / drain region of the first transfer MOS transistor, and the source / drain region of the first thin film transistor are connected to each other by second wiring means.

The first wiring means is embedded in an opening formed in the interlayer insulating layer and is connected to the gate electrode of the first driving MOS transistor and the source / drain regions of the second transfer MOS transistor and the surface of the silicon plug layer. And a wiring layer made of polycrystalline silicon electrically connected between the intermediate conductive layer formed of any one of the high melting point metal silicides and the source / drain regions of the second thin film transistor and extending on the surface of the interlayer insulating layer.

The second wiring means is embedded in the opening formed in the interlayer insulating layer, and the silicon plug layer and the silicon plug layer are connected to the gate electrode of the second driving MOS transistor and the source / drain region of the first transfer MOS transistor. It is made of polycrystalline silicon formed on the surface and electrically connecting the intermediate conductive layer made of either high melting point metal or high melting point metal silicide with the source / drain regions of the first thin film transistor and extending on the surface of the interlayer insulating layer. A wiring layer is provided.

A semiconductor device manufacturing method according to another aspect of the present invention includes the following process steps.

First, an interlayer insulating layer is formed on the surface of the first silicon layer.

Next, an opening reaching the surface of the first silicon layer is formed in the interlayer insulating layer.

Further, a second silicon layer is formed on the surface of the interlayer insulating layer and inside the opening.

Thus, the second silicon layer is etched back to form a silicon plug layer of the second silicon layer inside the opening.

Impurities are then injected into the silicon plug layer.

Further, by forming a high melting point metal layer on the surfaces of the interlayer insulating layer and the silicon plug layer and performing heat treatment, a high melting point metal silicide layer is formed on the surface of the silicon plug layer.

Thus, a wiring layer is formed by forming and patterning a polycrystalline silicon layer on the surfaces of the interlayer insulating layer and the high melting point metal silicide layer.

In a semiconductor device according to one aspect and another aspect of the present invention, a silicon plug layer is embedded in a contact hole.

Therefore, the wiring layer disposed on the surface of the interlayer insulating layer is formed on the surface of the silicon plug layer that is flat even in the region of the contact hole.

This improves the patterning accuracy of the wiring layer.

In the case where the silicon plug layer and the wiring layer have different conductivity types, an intermediate conductive layer made of a high melting point metal or the like sandwiched between them prevents the formation of a pn junction by direct contact between them.

In the method of manufacturing a semiconductor device according to another aspect of the present invention, a silicon plug layer is formed in the contact hole by using an etch back method. For this reason, the surface of a silicon plug layer and the surface of an interlayer insulation layer can be planarized easily.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows a cross-sectional structure of a memory cell of an SRAM according to the first embodiment of the present invention.

The planar structure is almost the same as the planar structure of the memory cell of the conventional SRAM shown in Figs.

FIG. 1 shows a cross-sectional structure at the same position as the cross-sectional position of FIG. 16 showing a conventional SRAM.

The cross-sectional structure of the memory cell shown in FIG. 1 differs from that of the conventional memory cell shown in FIG. 16 only in the structure of direct contact.

Therefore, the following mainly describes only the direct contact structure according to the present invention, and the description of the prior art for the structure of the other parts.

The direct contact portion 10 includes an n-type polycrystalline silicon plug layer 15, a titanium silicide layer 11, and a P-type polycrystalline silicon wiring layer 8a.

An opening (wiring contact portion) 16 is formed in the interlayer insulating layer 9.

At the bottom of the opening 16, n ⁺ source / drain region (impurity region) 7 of the n-channel MOS transistor 22b for transfer and the gate electrode 6 of the n-channel MOS transistor 20a for driving are exposed. .

The plug layer 15 made of polycrystalline silicon directly connected to the n ⁺ source / drain region 7 and the gate electrode 6 is embedded in the opening 16. Inside the polycrystalline silicon plug layer 15, n-type impurities such as phosphorus (P) and arsenic (As) for imparting conductivity are implanted.

A titanium silicide layer (intermediate conductive layer) 11 is formed on the surface of the polycrystalline silicon plug layer 15.

On the surface of the titanium silicide layer 11, a wiring layer 8a made of polycrystalline silicon is formed.

P-type impurities are introduced into the wiring layer 8a.

Thus, the direct contact structure between the wiring layer 8a, the source / drain region 7 and the gate electrode 6 has a flatness of the wiring layer 8a by embedding the polycrystalline silicon plug layer 15 inside the opening 16. To improve.

Further, the titanium silicide layer 11 is sandwiched between the wiring layer 8a and the polycrystalline silicon plug layer 15 so that the wiring layer 8a, the polycrystalline silicon plug layer 15, the source / drain region 7 and the gate are sandwiched. The ohmic contact between the electrodes 6 can be obtained.

That is, the formation of the pn junction is prevented by direct contact between the P-type wiring layer 8a of the titanium silicide layer 11 and the n-type polycrystalline silicon plug layer 15.

Next, a manufacturing process of the memory cell of the SRAM shown in FIG. 1 will be described.

2 through 9 are cross-sectional views of a manufacturing process of a memory cell of an SRAM.

Referring to FIG. 2, P-type impurities are implanted into the main surface of the silicon substrate 1 by, for example, ion implantation.

Thereafter, the P well 2 is formed by diffusing the implanted P-type impurity to a depth of about 2 to 3 µm from the main surface of the substrate 1.

In addition, a field oxide film 4 and a P ⁺ isolation layer 3 for device isolation are formed in a predetermined region on the surface of the P well 2 using the LOCOS (Local Oxidation of Silicon) method.

Next, an oxide film 5 having a film thickness of 12 nm to 15 nm is formed on the surface of the P well 2 using, for example, a thermal oxidation method.

The oxide film 5 constitutes the gate oxide film 5 of the MOS transistors 20a and 22b.

Furthermore, a polyside film composed of polycrystalline silicon and a high melting point metal silicide is deposited on the surface of the oxide film 5.

Thus, the polyside film is patterned into a predetermined shape using photolithography or etching.

As a result, the gate electrodes 6 and 6 of the MOS transistors 20a and 22b are formed.

In addition, the implanted amount of n-type impurity ions is implanted into the P well ² at 4x10 ¹⁵ particles / cm ² using the ion implantation method using the patterned gate electrode 6 as a mask.

Further, heat treatment is performed to form n ⁺ source / drain regions 7 of four MOS transistors 20a, 20b, 22a, and 22b.

Through the above steps, the n-channel MOS transistors 20a and 20b for driving and the n-channel MOS transistors 22a and 22b for transmission are formed.

Thereafter, a BOSG (Boro Phospho Silicate Glass) film is deposited on the entire surface of the silicon substrate 1 using, for example, atmospheric pressure chemical vapor deposition (CVD).

Thus, heat treatment is performed to soften the BPSG, thereby reflowing to planarize the surface of the BPSG film.

By this step, an interlayer insulating layer 9 having a flattened surface is formed.

In addition, an opening 16 for direct contact is formed in the interlayer insulating layer 9 using photolithography and etching.

As an etching method for forming the opening 16, for example, a reactive ion etching method is used.

Referring next to FIG. 3, a polycrystalline silicon layer 15a free of impurities is formed on the surface of the interlayer insulating layer 9 by using a low pressure chemical vapor deposition (LPCVD) method.

The polycrystalline silicon layer 15a completely fills the interior of the opening 16 and deposits so thick that its surface becomes nearly flat on top of the opening 16.

As a reference for the polycrystalline silicon layer 15a, a film thickness of at least half of the maximum diameter of the opening 16 is required.

Referring to FIG. 4 further, the polycrystalline silicon layer 15a is etched using the etch back method to remain only inside the opening 16.

By this process, the polycrystalline silicon plug layer 15 is formed.

Referring to FIG. 5, a resist pattern 17 having an opening only on the upper portion of the opening 16 is formed on the surface of the interlayer insulating layer 9.

By using the resist pattern 17 as a mask, ion implantation of impurity ions for imparting conductivity to the inside of the polycrystalline silicon plug layer 15 is carried out.

In this embodiment, ion implantation is performed with an implantation amount of n-type impurities such as phosphorus or arsenic as 1.5 x 10 ¹⁶ atoms / cm ² .

Heat treatment is then applied to activate the impurities.

6, the titanium layer 11a is deposited on the entire surface of the silicon substrate 1 using the sputtering method.

Thereafter, only the titanium layer located on the surface of the polycrystalline silicon plug layer 15 is silicided using the Rapid Thermal Annealing (RTA) method.

7, the unreacted titanium layer 11a formed on the surface of the interlayer insulating layer 9 is removed.

As a result, the titanium silicide layer 11 is formed on the surface of the polycrystalline silicon plug layer 15.

8, on the surfaces of the interlayer insulating layer 9 and the titanium silicide layer 11, a polycrystalline silicon layer 8 having no impurities introduced thereon is deposited by a film thickness of about 100 nm.

In addition, the amount of implantation of the P-type impurity ion 19 in the polycrystalline silicon layer 8 is 8x10.¹⁵Pcs / cm Ion implantation is carried out at about 2 degrees and heat-treated to activate P-type impurity ions.

Next, referring to FIG. 9, the P-type polycrystalline silicon layer 8 is patterned by using a photolithography method and an etching method.

By this process, the gate electrode 8b and the wiring layer 8a of the P-channel MOS thin film transistors 21a and 21b are formed.

Further, the gate oxide film 13 is deposited to a thickness of about 20 nm on the entire surface on the interlayer insulating layer 9 by, for example, LPCVD.

Thus, a part of the gate oxide film 13 located above the opening 16 is opened.

Thereafter, a thin polycrystalline silicon layer having a film thickness of about 10 nm is formed on the entire surface of the gate oxide film 13 by, for example, LPCVD.

Then, a resist is formed on the region of the polycrystalline silicon layer so as to be the channel region of the load P-channel MOS thin film transistors 21a and 21b.

Thus, using the resist as a mask, ion implantation of P-type impurity ions into the polycrystalline silicon layer is performed at about 1 × 10 ¹⁵ / cm ² .

As a result, P ⁺ source / drain regions 12a and 12c of the load P-channel MOS thin film transistors 21a and 21b are formed.

By the above process, the memory cell shown in FIG. 1 is completed.

Next, a description will be given of a first modification of the first embodiment.

In the first embodiment, the polycrystalline silicon layer 15a is formed by LPCVD in the process shown in FIG.

Instead of this process, a silicon layer can be selectively grown on the surface of the source / drain region 7 using a CVD method at a temperature of 900 to 1000 ° C.

Using this selective growth method, only the inside of the opening 16 can form a single crystal silicon layer.

Impurity ions for imparting conductivity are implanted into the single crystal silicon plug layer 15.

As a second modification, instead of depositing the non-doped polycrystalline silicon layer 15a, a method of depositing so-called doped polysilicon is used.

That is, phosphorus (P) can be introduced into the polycrystalline silicon by simultaneously flowing the PH3 gas at the time of forming the polycrystalline silicon layer by the LPCVD method.

In this case, the ion implantation step for imparting conductivity can be omitted.

Next, the structure of the memory cell of the SRAM according to the second embodiment of the present invention will be described.

10 is a cross-sectional structural view of the memory cell according to the second embodiment.

The memory cell according to the second embodiment is different from the transistor structure of the load P-channel MOS thin film transistors 21a and 21b and the structure of the wiring layer 8a as compared with the memory cell according to the first embodiment.

The thin film transistor 14 (21b) has P ⁺ source / drain regions 12a and 12c and a channel region 12b in a thin polycrystalline silicon layer formed on the surface of the interlayer insulating layer 9.

It is formed on the surface of the gate insulating layer 13 formed on the surfaces of the source / drain regions 12a and 12c and the channel region 12b of the gate electrode 8b.

The P-type polycrystalline silicon layer in which the source / drain regions 12a are formed extends on the surface of the titanium silicide layer 11.

Thus, the wiring layer 8a made of the polycrystalline silicon layer into which the P-type impurity is injected is connected to the source / drain region 12a through the opening formed in the gate insulating layer 13.

Next, a characteristic manufacturing process of the memory cell according to the second embodiment will be described.

11 and 12 are cross-sectional views of the manufacturing process showing the main manufacturing process of the memory cell shown in FIG.

In addition, the process before the process shown in FIG. 11 is the same as the process of FIGS. 2-7 which shows 1st Example, The description of the process is abbreviate | omitted here.

Following the process shown in FIG. 7, first, referring to FIG. 11, the polycrystalline silicon layer 12 is deposited on the surfaces of the interlayer insulating layer 9 and the titanium silicide layer 11 by, for example, LPCVD. It deposits about 10 nm in thickness.

Further, a gate oxide film 13 is formed on the surface of the polycrystalline silicon layer 12 with a film thickness of about 20 nm.

In addition, referring to FIG. 12, an opening is formed at a predetermined position of the gate oxide film 13.

This opening is formed at an upper portion of the opening 16 formed in the interlayer insulating layer 9 and adjacent to the load P-channel MOS thin film transistors 21a and 21b.

Next, P-type impurity ions are implanted into the polycrystalline silicon layer 12 with the resist mask used to form the openings in the gate oxide film 13 remaining.

In this ion implantation process, the resist mask prevents the impurity ions from being injected into the region of the polycrystalline silicon layer 12 where the impurity ions penetrate the thin gate oxide film 13 and do not require ion implantation.

Thereafter, the resist mask is removed.

Thus, the polycrystalline silicon layer 8 is formed on the entire surface of the gate oxide film 13 by, for example, LPCVD, at a thickness of about 100 nm.

In addition, the ion implantation method is used to implant P-type impurity ions into the polycrystalline silicon layer 8 at an amount of about 8 x 10 ¹⁵ atoms / cm ² , and then heat treatment is performed.

As a result, the polycrystalline silicon layer 8 is imparted with P-type conductivity.

Thereafter, the polycrystalline silicon layer 8 is patterned using photolithography and ion etching.

The wiring 8a and the gate electrode 8b are formed by this patterning process.

Further, a resist pattern larger than the width of the gate electrode 8b is formed on the gate electrode 8b.

Thus, the implantation amount of P-type impurity ions into the polycrystalline silicon layer 12 is implanted by 1 × 10 ¹⁵ particles / cm ² with the resist pattern as a mask.

The source / drain regions 12a and 12 are formed by this ion implantation.

The resist pattern is then removed.

By the above steps, the memory cell shown in FIG. 10 is completed.

In this manner, in the first and second embodiments, the upper wiring layer has P-type conductivity, and the lower impurity region has n-type conductivity.

Thus, in such a case, the silicon plug layer 15 and the n-type impurity region have good ohmic contact due to the n-type conductivity of the silicon plug layer 15.

In addition, a good ohmic contact can be obtained between the silicon plug layer and the upper wiring layer by sandwiching a high melting point metal layer or the like between the P-type wiring layer and the silicon plug layer.

The conductive type of the wiring layer, the silicon plug layer and the impurity region may be reversed from the above embodiment.

In other words, the upper wiring layer may have n-type conductivity and the lower impurity region may have P-type conductivity.

In this case, it is necessary to give P type conductivity to the silicon plug layer 15 by introducing P type impurities.

Here, reference is again made to the ion implantation process shown in FIG.

In the case where P-type impurities are introduced into the silicon plug layer 15, it is preferable to use a high energy ion implantation method capable of giving an ion implantation energy of 150 KeV or more.

This is because the diffusion coefficient is lower than that of P-type impurities such as B ⁺ and PF ₂ ⁺ .

Therefore, it is preferable to implant the ion deeply near the center of the silicon plug layer 15 using a high energy ion implantation method.

If the P-type impurity ions are introduced to the center portion of the silicon plug layer 15, it is easy to diffuse the impurities throughout the silicon plug layer 15 by lamp annealing thereafter.

As a result, the entirety of the silicon plug layer 15 can be reduced in resistance.

Next, a third embodiment of the present invention will be described.

13 is a cross-sectional structural view of the direct contact structure according to the third embodiment of the present invention.

On the surface of the silicon substrate 1, for example, an n-type impurity region 30 is formed. On the surface of the n-type impurity region 30, a pad layer 31 of polycrystalline silicon is formed. The upper side of the pad layer 31 of polycrystalline silicon is formed to have a diameter larger than the diameter of the opening 16, and its trademark surface is in contact with the silicon plug 15.

An opening 16 reaching the pad layer 31 is formed in the interlayer insulating layer 9. The silicon plug layer 15 is embedded in the opening 16. On the surface of the silicon plug layer 15, a high melting point metal silicide layer, for example titanium silicide 11, is formed. On the surface of the interlayer insulating layer 9, a wiring layer 8a having P-type conductivity is formed.

Part of the wiring layer 8a is connected to the titanium silicide layer 11.

The surface of the wiring layer 8a is covered with the second interlayer insulating layer 32.

Also in this embodiment, the case where the conductivity types of the silicon plug layer 15 and the wiring layer 8a are reversed may be reversed.

In addition, although the example which used titanium silicide as an intermediate conductive layer in the said 1st-3rd Example was demonstrated, you may use another high melting metal silicide or high melting metal silicide.

The direct contact structure of the semiconductor device according to the present invention is such that the silicon plug layer is embedded in the contact hole and the upper wiring layer is formed on the planarized layer. The patterning accuracy of the wiring layer using the photolithography method is improved and the wiring Reliability is improved.

By interposing an intermediate conductive layer between the silicon plug layer and the wiring layer, good ohmic contact can be realized between layers having different conductivity.

Moreover, the silicon plug layer can be formed using a known CVD method and an etching method, and thus does not require a complicated manufacturing process.

Claims (20)

A semiconductor device having a wiring contact portion 7 of the first conductive type, comprising: a silicon layer 2, an interlayer insulating layer 9 on the surface of the silicon layer, and a portion of the interlayer insulating layer so that the wiring contact portion is exposed; A wiring layer 8a of polycrystalline silicon having an opening 16 to be formed, a silicon plug 15 of a first conductivity type embedded in the opening, a second conductivity type formed on a surface of the interlayer insulating layer, and A semiconductor device having a first conductive type wiring contact portion including a wiring layer and an intermediate conductive layer (11) for reducing the magnitude of the pn junction voltage drop between the wiring layer and the wiring contact portion. The semiconductor device according to claim 1, wherein the intermediate conductive layer is made of a material which prevents formation of a pn junction between the wiring layer and the wiring contact portion. The semiconductor device according to claim 1, wherein said intermediate conductive layer is made of a material that is doped so as to conduct higher than said wiring layer and said silicon plug. The semiconductor device of claim 1, wherein the intermediate conductive layer is positioned flat to the surface of the silicon plug in the opening. The semiconductor device of claim 4, wherein a surface of the silicon plug and a surface of the interlayer insulating layer are horizontal to each other. The semiconductor device of claim 1, further comprising an additional conductive layer in the interlayer insulating layer and having a portion exposed through sidewalls of the opening. The semiconductor device according to claim 6, wherein the intermediate conductive layer contacts the opening. The semiconductor device of claim 1, further comprising a pad layer of polysilicon having a diameter larger than the opening, wherein the silicon plug contacts the pad layer in the opening. A silicon layer 2, an interlayer insulating layer 9 formed on the surface of the silicon layer, an opening 16 formed in the interlayer insulating layer, a silicon plug layer 15 embedded in the opening, An intermediate conductive layer 11 formed of either a high melting point metal silicon or a high melting point metal formed on the surface of the silicon plug layer, and polycrystalline silicon formed on the surface of the interlayer insulating layer and connected to the intermediate conductive layer A semiconductor device having a wiring contact portion including a wiring layer (8a). 10. The semiconductor device of claim 9, wherein the silicon layer and the silicon plug layer include impurities of the same conductivity type, and the wiring layer has a wiring contact portion including an impurity of a conductivity type different from that contained in the silicon plug layer. Device. The semiconductor device according to claim 9, wherein the silicon plug layer has a wiring contact portion formed of polycrystalline silicon. The semiconductor device according to claim 9, wherein the silicon plug layer has a wiring contact portion formed of single crystal silicon. 10. The semiconductor device according to claim 9, wherein the silicon layer includes a silicon substrate 1 including an impurity region 7, and the silicon plug layer has a wiring contact portion connected to the impurity region formed on the silicon substrate. . A pair of first and second CMOS inverters connected to form a flip-flop circuit, and first and second transfer MOS transistors connected to each node point of the flip-flop circuit, respectively, wherein the first CMOS inverter is formed of silicon. A first driving MOS transistor of the first conductive type 20a formed on the main surface of the substrate and a second thin film transistor 21a of the second conductive type formed on the surface of the interlayer insulating layer; The second CMOS inverter includes a second driving MOS transistor 20b of the first conductive type formed on the main surface of the silicon substrate and a second thin film transistor 21b of the second conductive type formed on the surface of the interlayer insulating layer. The first transfer MOS transistor and the second transfer MOS transistor include a memory cell formed on a main surface of the silicon substrate, wherein the gate electrode of the first drive MOS transistor, and the second MOS transistor source for transmission A first wiring means for connecting a drain region and a source / drain region of the second thin film transistor, a gate electrode of the second driving MOS transistor, a first transfer MOS transistor, and a first thin film transistor. A first wiring means for connecting source / drain regions, said first wiring means being embedded in an opening 16 formed in said interlayer insulating layer, said first driving MOS An intermediate conductive layer 11 of any one of a high melting point metal or a high melting point metal silicide formed on a surface of a silicon plug layer connected to a gate electrode 6 of a transistor and a source / drain region of the second transfer MOS transistor, And a wiring layer 8a of polycrystalline silicon electrically connected to the source / train region 7 of the intermediate conductive layer and the second thin film transistor and extending onto the surface of the intermediate insulating layer. In contrast, the second wiring means is a silicon plug layer embedded in an opening formed in the interlayer insulating layer and connected to a gate electrode of the second driving MOS transistor and a source / drain region of the first transfer MOS transistor ( 15), an intermediate conductive layer 11 of either a high melting point metal or a high melting point metal silicide formed on the surface of the silicon plug layer, and a source / drain region 7 of the intermediate conductive layer and the second thin film transistor. And a memory cell having a wiring layer of polycrystalline silicon electrically connected to and extending on the surface of the intermediate insulating layer. 15. The SRAM of claim 14, wherein the silicon plug layer includes impurities of a conductivity type different from that of the wiring layer. The SRAM of claim 15, wherein the silicon plug layer is formed of polycrystalline silicon or single crystal silicon. A method of manufacturing a semiconductor device having a wiring contact portion, comprising: forming an interlayer insulating layer 9 on a surface of a first silicon layer, and openings 16 reaching the surface of the first silicon layer of the interlayer insulating layer. ), Forming a second silicon layer (15a) on the surface of the opening and the interlayer insulating layer, and etching back the second silicon layer to form a second silicon or the like in the opening Forming a silicon plug layer (15), implanting impurities into the silicon plug layer, forming a high melting point metal silicide layer (11a) on the surfaces of the interlayer insulating layer and the silicon plug layer, and Forming a high melting point metal layer 11 on the surface of the silicon plug layer by heat treatment, and forming and patterning a polycrystalline silicon layer 8 on the surface of the interlayer insulating layer and the high melting point metal silicide layer Forming a wiring layer (8a). 18. The method of claim 17, wherein the implanting the impurity into the silicon plug layer comprises implanting the impurity into the silicon plug layer using an ion implantation method of ion implantation energy of 150 KeV or more. Forming an interlayer insulating layer (9) on the surface of the first silicon layer (1), forming an opening (16) in the interlayer insulating layer reaching the surface of the first silicon layer; Forming a high melting point metal silicide layer on the surface of the silicon layer, forming a second silicon layer on the surface of the interlayer insulating layer and in the opening, and etching back the second silicon into the opening Forming a silicon plug layer of the second silicon layer, implanting impurities 19 into the silicon plug layer, and forming and patterning a polycrystalline silicon layer on the surface of the interlayer insulating layer and the silicon plug layer Forming a wiring layer (8a). Forming an interlayer insulating layer 9 on the surface of the first silicon layer 1, forming an opening 16 reaching the surface of the first silicon layer in the interlayer insulating layer; Forming a second silicon layer 15a in the surface of the insulating layer and in the opening, and etching back the second silicon layer to form the silicon plug layer 15 of the second silicon layer in the opening; Implanting impurities 18a into the silicon plug layer, and forming a high concentration impurity layer on the surface of the silicon plug layer, the impurity layer having a higher concentration than that of the impurity contained in the silicon plug layer; And forming a polycrystalline silicon layer on the surface of the interlayer insulating layer and the impurity layer of high concentration to form a wiring layer (8a).