JP2596198B2 - MOS type read-only semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS read-only semiconductor memory device, and more particularly, to a NOR read-only semiconductor memory device.

[Prior Art] To increase the capacity of MOS-type read-only semiconductor memory devices, N
An AND type cell array is often used, but this type has a drawback that the reading speed is slow. On the other hand, a NOR type cell array is used for a device requiring high-speed reading, but this type is not suitable for high integration because of its large cell size. On the other hand, Japanese Patent Application Laid-Open No. 63-131568 proposes a semiconductor memory device having both the features of the high integration degree of the NAND type and the features of the high-speed reading of the NOR type.

Hereinafter, a storage device proposed by the publication will be described with reference to FIG. In this storage device, as shown in the figure, a plurality of n-type buried layers (diffusion layers) 101a and 101b are provided in a surface region of a p-type semiconductor substrate at intervals of a channel length of a memory cell transistor. , 101c are formed, and a plurality of gate electrodes 102a to 102h that vertically intersect with the buried layer via a gate insulating film are formed on the semiconductor substrate.
Are formed. Each buried layer is connected to an upper Al wiring 104 via a contact hole 103.

In the memory cell thus formed, as in the case of the memory cell 105, for example, the buried layer 101b serves as the drain of the memory cell transistor, the buried layer 101a serves as the source of the memory cell transistor, and the longitudinal direction of the gate electrode 102a corresponds to the long direction. The direction is the channel direction of the memory cell transistor. Unlike a normal NOR type memory cell, this type of memory cell does not require contact holes and element isolation regions on both sides of the channel, so that high density can be achieved. , High-speed reading is possible.

[Problems to be Solved by the Invention] However, the memory cell having this structure has serious drawbacks in the following two points. First, there is the problem of setting the potential of the non-selective buried layer. Fifth case of selecting the memory cell 105 for example, in the storage device of Figure, the gate electrode 102a and the potential V _G (positive potential) (other gate electrode 102b~102h ground potential), the buried layer 101b is potential V _D (positive potential ), The buried layer 101a is in a potential V _S (ground potential) state. At this time, the potential of the non-selected buried layer 101c must be V _D or floating potential. This is to prevent leakage of current from the buried layer 101b to 101c when the memory cell 105 is in the selected state. Actually, the unselected buried layer is often designed to be in a floating potential state, but in any case, the peripheral circuit becomes extremely complicated in the above-described conventional example.

The second drawback is a problem in the data writing process that is unique to the manufacture of a read-only storage device. In a normal case, data writing is performed after a gate electrode is formed, and impurity ions are selectively transmitted through a gate electrode and a gate insulating film using a photoresist mask and introduced into the surface of a semiconductor substrate, and a threshold voltage of a memory cell transistor is determined. Is controlled by controlling The photoresist mask used at this time includes a gate electrode (102a to 102h) and a buried n-type diffusion layer (101a to 101h).
101c). However, positioning with respect to the gate electrode is easy due to a large pattern step, but positioning with respect to the buried layer is generally extremely difficult because the buried layer has no geometrical feature. For this reason, a pattern different from the buried layer (eg, a gate electrode or a field insulating film) is actually used.
Indirectly. Therefore, it is necessary to provide a margin for alignment, which has been an obstacle to high integration.

[MEANS FOR SOLVING THE PROBLEMS] A MOS-type read-only semiconductor memory device according to the present invention includes a plurality of parallel grooves formed in a surface region of a p-type semiconductor substrate and filled with an insulator therein. An n-type diffusion region provided along each groove and separated from each other on both sides of each groove, and vertically intersects with the groove formed on the semiconductor substrate via a gate insulating film. And n-type diffusion regions provided on both sides of the groove are formed in self-alignment with the groove.

[Example] Next, an example of the present invention will be described with reference to the drawings.

1 (a), 1 (a '), 1 (b) to 1
FIG. 2F is a plan view showing a manufacturing process according to an embodiment of the present invention, and FIGS. 2A to 2D and 3A to 3D.
(D) and FIGS. 4 (a) to 4 (d) show the first
FIG. 4A is a cross-sectional view during the manufacturing process along a line II-II, a line III-III, and a line IV-IV in FIGS. 2A to 4D, and FIGS. This corresponds to each of the steps (a) to (d) in FIG.

First, as shown in FIG. 1A to FIG. 4A, a film is heated in an oxidizing atmosphere to form a film having a thickness of 200 to 400.
Gate insulating film 2 is formed, and a chemical vapor deposition (CV)
A polycrystalline silicon film 3 of 4000 to 6000 Å and a silicon oxide film 4 of 1000 to 2,000 そ れ ぞ れ are formed by the method D). Thereafter, the silicon oxide film 4 and the polycrystalline silicon film 3 are selectively removed by a photoetching method to form a groove opening expected region 5.

Next, as shown in FIG. 1 (a '), a photoresist film 10 covering both ends of the groove opening region 5 is formed, and an n-type impurity, for example, arsenic ion is removed from the groove opening region 5 by 1 ×. 10 ¹⁵
To 5 × 10 ¹⁵ to introduce about cm ^-5, to form a buried layer 6 of the n-type heat treatment is performed in about one hour in a nitrogen atmosphere at 950 ° C. [in Fig. 1 - Fig. 4 (b)].

Next, using the uppermost silicon oxide film 4 as a mask, a buried layer separating groove 7 having a depth of 2 to 3 μm is formed in the p-type semiconductor substrate 1. This groove is formed sufficiently deeper than the buried layer to completely divide the buried layer 6 into two. next,
As shown in FIG. 1C to FIG. 4C, the inside of the buried layer separation groove 7 is buried with a buried oxide 8. As this oxide, BPSG with high fluidity or the like can be used.

Next, a tungsten silicide film 9 is deposited on the surface of the substrate, and the tungsten silicide film 9 and the polycrystalline silicon film 3 are selectively removed to form a gate electrode orthogonal to the isolation trench 7 [FIGS. (D) of FIG. 4].

Next, as shown in FIG. 1 (e), in order to selectively form an n-type diffusion layer for drawing out the buried layer 6, a photoresist film 11 is applied, and one end of the buried layer 6 is applied to this. A hole is formed in the n-type diffusion layer forming region 12 exposing. The photomask used at this time is not a special mask for forming the n-type diffusion layer, but can be shared with the mask used for forming the source and drain regions of the n-channel transistor of the CMOS device of the peripheral circuit. Therefore, even if the n-type diffusion layer is formed here, the manufacturing process itself does not increase. Subsequently, an n-type impurity such as arsenic is ion-implanted to form an n-type diffusion layer.
13 (FIG. 1 (f)) is formed, and the photoresist film 11 is peeled off.

Subsequently, writing is performed on this memory cell. In a photoresist step for that purpose, a gate electrode (tungsten silicide film 9) and a buried oxide 8 are used for alignment. The planar shape of the buried oxide 8 matches that of the isolation trench 7, and the buried layer 6 is formed in a self-aligned manner with the isolation trench 7, so that the alignment is performed accurately.

Finally, as shown in FIG. 1 (f), the entire surface is covered with an interlayer insulating film, and the tungsten silicide film 9 and n
Forming a contact hole 14 opening on the diffusion layer 13
The wiring 15 is formed. In this case, the tungsten silicide film 9 is formed on the LOCOS oxide film outside the active region 16 by the Al wiring 15.
Connected to

According to the present invention, it is not necessary to set the unselected buried layer to a positive potential or a floating potential. Therefore, as shown in FIG. 1F, the buried layer on one side of the groove can be fixed to the source region and connected to the common Al wiring 15. Therefore, wiring and peripheral circuits are significantly simplified.

[Effects of the Invention] As described above, according to the present invention, since the buried layer which is the source / drain region is separated by the separation groove, according to the present invention, the potential of the unselected buried layer is set to the ground potential. Even if it is set, leakage current does not occur. Therefore, according to the present invention, there is no need to set the non-selective buried layer to a positive potential or to make the unselected buried layer float.
Wiring and peripheral circuits are simplified.

Also, since the buried layers are separated by grooves,
The load capacity of the selected buried layer is significantly reduced, and a high-speed operation is achieved.

Further, since the photoresist mask in the data writing step can be directly aligned with the buried layer separation groove in which the buried layer is self-aligned, high accuracy can be expected and the size of the memory cell can be reduced.

[Brief description of the drawings]

1 (part 1) to (part 4) are plan views of a manufacturing process of an embodiment of the present invention, FIGS. 2 to 4 are cross-sectional views of the same, and FIG. It is a top view. DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 2 ... gate insulating film, 3 ... polycrystalline silicon film, 4 ... silicon oxide film, 5 ... planned groove opening area, 6, 101a, 101b, 101c ... buried layer (N-type diffusion region), 7: buried layer separation groove, 8: buried oxide, 9: tungsten silicide film, 10, 11 ...
Photoresist film, 12 ... n-type diffusion layer formation region, 13 ...
n-type diffusion layer, 14, 103 ... contact hole, 15, 104 ... Al
Wiring, 16 Active region, 102a-102h Gate electrode, 10
5 Unit memory cell.

Claims (3)

(57) [Claims] 1. A plurality of parallel grooves formed in a surface region of a semiconductor substrate of a first conductivity type and filled with an insulator therein, and on both sides of each groove along and along each groove. A second conductivity type diffusion region provided by being separated from each other by a groove, and a plurality of gate electrodes which are formed on the semiconductor substrate via a gate insulating film and intersect the groove perpendicularly,
MOS-type read-only semiconductor memory device comprising: 2. The MOS read-only semiconductor memory device according to claim 1, wherein said diffusion regions provided on both sides of said groove are formed in a self-aligned manner with respect to said groove. 3. The MOS read-only semiconductor memory device according to claim 1, wherein the diffusion regions arranged on one side of the plurality of grooves are commonly connected to the same metal wiring.