JP3536469B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [0001] The present invention relates to a semiconductor device manufacturing method.
For example, applied to manufacturing of static RAM
It is suitable. [0002] 2. Description of the Related Art A thin film transistor is formed on a driver transistor.
Configuration in which load transistors composed of transistors (TFTs) are stacked.
Static RAM with low power consumption and data
Good durability characteristics and high integration possible by lamination
Therefore, it has been attracting attention. FIG. 13 shows a static RAM of this type.
FIG. 3 is a plan view illustrating an example of a memory cell. In FIG. 13, reference numeral 101 denotes a semiconductor substrate.
The field insulating film formed in
N used as a source region or a drain region⁺Expansion of mold
Layer, G₁, G_TwoIndicates a gate electrode, and WL indicates a word line.
You. Gate electrode G₁And the diffusion layers 102 and 103
Driver transformer composed of n-channel MOS transistors
Jista Q₁Is formed. Similarly, the gate electrode G_Two
And diffusion layers 104 and 105 form an n-channel MOS transistor.
Driver transistor Q consisting of a transistor_TwoFormed
Have been. Also, the word line WL and the diffusion layers 103 and 106
As a result, the action of the n-channel MOS transistor
Set transistor Q_FiveIs formed, and the word line WL and the diffusion
The layers 107 and 108 form an n-channel MOS transistor.
Access transistor Q₆Is formed
You. [0005] C₁₀₁~ C₁₀₃Is a buried contact (bu
ried contact). And
Driver transistor Q₁Gate electrode G₁One end of this
Contact hole C₁₀₁Driver Transis through
TA Q_TwoContact with the diffusion layer 104, and the other end
Contact Hall C₁₀₂Through the access transistor Q
₆Contact with the diffusion layer 107. Also dry
Transistor Q_TwoGate electrode G_TwoIs a contact
C₁₀₃Through the driver transistor Q₁And a
Access transistor Q_FiveContact the diffusion layer 103 of
ing. Although not shown, the driver transistor
Q₁, Q_TwoThin film transistor with an interlayer insulating film on top
Load transistor Q_Three, Q_FourIs formed. FIG. 14 shows an equivalent of the memory cell shown in FIG.
It is a circuit diagram. In FIG. 14, V_DD, V_SSIs power, B
L and BL bars indicate bit lines. [0008] SUMMARY OF THE INVENTION The present invention is constructed as described above.
In order to reduce the size of the memory cell
Transistor Q₁, Q_TwoChannel width, access traffic
Transistor Q_Five, Q₆Gate length, driver transformer
Jista Q₁Gate electrode G₁And access transistor Q
₆Between word line WL and driver transistor
Q_TwoGate electrode G_TwoAnd access transistor Q_FiveNo
It is effective to reduce the distance from the word line WL. However, the memory cell is stable at a low voltage.
To operate, the cell ratio (= driver transistor
Must be large.
Driver transistor Q₁, Q_TwoNo cha
The width of the tunnel cannot be reduced indiscriminately. The access transistor Q_Five, Q₆of
Reduction of the gate length is necessary for high-speed operation of memory cells.
It is effective, but in order to secure the cell ratio, dry
Transistor Q₁, Q_TwoChannel width must be increased.
Need to reduce the size of memory cells
Can not. Next, the driver transistor Q₁Gate of
Electrode G₁And access transistor Q₆And the word line WL
Spacing and driver transistor Q_TwoGate electrode G
_TwoAnd access transistor Q_FiveOf the word line WL
Is determined by the resolution limit of photolithography
Beyond the resolution limit, the driver transistor Q₁of
Gate electrode G₁And access transistor Q₆Word line
WL and driver transistor Q_TwoGate of
Electrode G_TwoAnd access transistor Q_FiveAnd the word line WL
It is difficult to reduce the interval between the two. In addition, photolitho
Resolution limit l_minIs the wavelength λ of the light source and the aperture
Using the unit NA, l_min= Kλ / NA. This
Here, K is used for manufacturing conditions such as photoresist and developing conditions.
It is a constant determined by In order to avoid the above-mentioned problem, the size of the memory cell is reduced.
Driver transistor and access
A method of overlapping with a transistor has been proposed (IEDM
Tech. Dig., Pp. 809-812, 1993). According to this method,
After forming the gate electrode of the driver transistor,
Thermal oxidation of the substrate surface again to form a gate oxide film and another layer
To form a word line. This method uses the driver transistor
Si substrate damaged by irradiation due to etching during star formation
It is necessary to form a gate oxide film on the surface again.
Driver transistor wiring layer and access transistor
An access transistor is used to electrically isolate the wiring layer.
Gate electrode of driver transistor before forming wiring layer
Must be covered with an insulating film, which complicates the manufacturing process.
Disadvantage. Therefore, the object of the present invention is to
Form patterns with dimensions below the resolution limit of the lithography
For example, in a static RAM,
Semiconductor device capable of reducing the size of a molycell
Is provided. [0014] [MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
This departureMing is, Buried on one main surface of semiconductor substrate
Forming an insulating film having a contact opening;
Step of forming a first thin film on the entire surface after forming an insulating film
Forming a second thin film serving as a mask material on the first thin film
Having a first dimension in one direction in the second thin film;
And a first opening overlapping the opening for the buried contact.
Forming a third thin film on the entire surface;
Side of the first opening by etching back the thin film of
Forming a first spacer on the substrate;
And etching the first thin film using the second thin film as a mask
To limit the resolution of photolithography in one direction.
A second dimension smaller than the field and a buried contact
Forming a second opening overlapping with the opening for
After forming the opening, a fourth thin film is formed on the entire surface,
Side of the second opening by etching back the thin film of
Forming a second spacer on the substrate;
After formation, a fifth conductive thin film is formed on the entire surface to form a second thin film.
Semi-conducting through the opening for the buried contact and the opening for the buried contact
Making a buried contact with the body substrate.
A method of manufacturing a semiconductor device. This departureClearIn one embodiment, the first
The thin film is made of polycide, but made of other materials
There may be. Further, the second thin film and the third thin film are
What kind of mask can be used when etching thin film 1
Although it may be made of a material, specifically, for example,
An oxide film is used. [0016] [0017] Manufacturing of the semiconductor device according to the present invention described above.
According to the method, the resolution below the resolution limit of photolithography
A pattern having dimensions can be formed. [0019] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
This will be described with reference to the drawings. FIG. 1Reference exampleMethod for Manufacturing Semiconductor Device
FIG. ThisReference exampleSemiconductor device manufacturing method
First, as shown in FIG. 1A, the semiconductor substrate 1
An insulating film 2 is formed on the surface. Next, finally photolithography
The space below the resolution limit of the
Then, a first thin film 3 is formed on the entire surface. Next, with the mask material
A second thin film 4 is formed on the entire surface. This second thin film 4
As a material for the first thin film 3, etching is selected.
The material is selected so that a large selection ratio can be obtained. Then one side
Resist pattern 5 having an opening having a width L1
2 is formed on the thin film 4. At this time, the width L1 is
It may be almost the same as the resolution limit of sography or it
May be slightly larger than Next, as shown in FIG.
Etching the second thin film 4 using the mask 5 as a mask.
And the opening H₁After forming the resist pattern 5
Remove. Next, a third thin film (not shown) is formed on the entire surface.
After that, this third thin film is applied to the surface of the semiconductor substrate 1.
By etching back in the vertical direction, the opening H₁Side of
Side wall spacer made of the material of the third thin film on the surface
6 is formed. At this time, the side wall spacer 6
The width W1 is a minute space to be formed on the first thin film 3 later.
Is defined as L2, L2 = L1-2 × W1.
Is chosen. Next, as shown in FIG.
A distaste pattern 7 is formed. Next, using the resist pattern 7 as a mask
Etching the second thin film 4 to form an opening (not shown)
I do. Next, after removing the resist pattern 7, the second
Using the thin film 4 and the sidewall spacer 6 as a mask
1D by etching the first thin film 3
As shown in FIG._Two, H_ThreeTo form After this,
2 thin film 4 and sidewall spacer 6
Removed. At this time, the opening H_TwoWidth L2 is L1-2 ×
W1, which is 2 times higher than the resolution limit of photolithography.
× W1. As explained above, thisReference exampleBy half
According to the method of manufacturing a conductor device, photolithography
A fine space having a size smaller than the resolution limit
3 can be formed. Next, the present inventionFruitThe embodiment will be described.
You. ThisFruitThe embodiment is based on the driver transistor already described.
A load transistor consisting of a TFT is stacked on a
This invention is applied to the manufacture of a static RAM
It is. Structure of memory cell of this static RAM
Is, for example, the same as that shown in FIG. FIGS. 2 to 12 show the present invention.FruitIn form
Sectional view showing a method for manufacturing a static RAM according to the present invention.
You. ThisFruitOf the static RAM according to the embodiment
In the manufacturing method, first, as shown in FIG.
In a semiconductor substrate 11 such as an n-type silicon (Si) substrate
Form n-well 12 and p-well 13 adjacent to each other
I do. These n-well 12 and p-well 13 are
Specifically, for example, it is formed as follows. That is,
Oxidized by thermally oxidizing the surface of the semiconductor substrate 11
A film (not shown) is formed. Next, p-type oxide is formed on this oxide film.
Prescribed resist pattern covering the surface of the well formation area
(Not shown), and using this resist pattern as a mask
For example, phosphorus (P) by ion implantation
For example, an n-type impurity is implanted at an energy of 50 keV and a dose of
Amount (1-10) x 10¹²cm^-2Doping under the following conditions. Next
After removing the resist pattern, an n-well is formed.
Oxide film with resist pattern of predetermined shape covering the surface of the region
Formed on top and using this resist pattern as a mask
For example, p-type impurities such as boron (B) by ion implantation
For example, the object is implanted at an energy of 30 keV and a dose (1 to 1).
10) x 10¹²cm^-2Doping under the following conditions. Then this
After removing the resist pattern, for example, a temperature of 1150 ° C.
Heat for three hours at a temperature,
Activation. This allows doping with n-type impurities
N-well 12 is formed in the region
A p-well 13 is formed in the defined region. Next, the semiconductor substrate 11 is formed on the surface of the semiconductor substrate 11.
After the oxide film is removed by etching, for example, a selective oxidation method (L
Element separation is performed by the OCOS method. That is,
And a pad oxide film on the surface of the semiconductor substrate 11 by thermal oxidation.
(Not shown). Next, the entire pad oxide film
Silicon nitride (Si)_ThreeN_Four) A film is formed and
It is patterned into a predetermined shape by etching.
Next, this Si_ThreeN_FourSemiconductor substrate with film as oxidation mask
11 by selectively thermally oxidizing the surface,
A field insulating film 14 having a thickness of about 400 nm is formed to
Perform separation. At this time, in the part of the p-well 13,
The ions are implanted into the selective oxidation portion of the p-well 13 in advance.
The diffused p-type impurity such as B
Under the field insulating film 14, for example, p⁺Type channel
A top region 15 is formed. Next, Si_ThreeN_FourD membrane
Etching removal and etching removal of pad oxide film
Then, the surface of the semiconductor substrate 11 is exposed. Next, the fee
Thermal oxidation of the surface of the active region surrounded by the field insulating film 14
After forming an oxide film (not shown)
A p-type impurity such as B is introduced into the semiconductor substrate 11 by the implantation method.
The threshold voltage is adjusted by doping. Next
After removing the oxide film by etching,
To thermally oxidize the surface of the active region surrounded by the edge film 14
For example, about 16 nm thick SiO_TwoGate like membrane
An insulating film 16 is formed. Next, a predetermined shape (not shown)
Using the resist pattern as a mask,
The gate insulating film 16 is etched with, for example, buffered hydrofluoric acid.
Substrate contact area, that is,
Contact hole C for contact₁To form Next, as shown in FIG.
For example, a polycrystalline Si film 17 having a thickness of about 100 nm is
Formed at a temperature of 620 ° C. Next, this polycrystalline Si film 1
7, for example, POCl_ThreeBy the thermal diffusion method using
Thus, P is doped at a high concentration to lower the resistance. Also this
Sometimes, contact hole C₁P well 1 in the area
P is diffused into 3 to form an n-type diffusion layer 18. Next
Then, on the surface of the polycrystalline Si film 17 during the thermal diffusion,
After removing the phosphorus glass by etching, the polycrystalline Si film
17 by sputtering or CVD, for example,
About 100 nm of tungsten silicide (WSi_Two)
A film 19 is formed. Next, on the entire surface by CVD method or the like,
For example, about 200 nm thick SiO_TwoInterlayer insulation like film
A film 20 is formed. Next, as shown in FIG.
Cell driver transistor Q₁And access transis
TA Q₆To the portion corresponding to the region between
Insulation of resist pattern 21 of predetermined shape having opening
After being formed on the film 20, this resist pattern 21 is
The interlayer insulating film 20 is used as a mask, for example, by reactive ion etching.
By anisotropic etching such as RIE
Openings 22a and 22b are formed. These openings 22
a, the width L1 in one direction of 22b is
It may be about the same as the resolution limit of the fee,
May be larger. Next, the resist pattern 21 is removed.
Next, as shown in FIG.
For example, SiO_TwoAfter the film is formed, a half
Etch back vertically to the surface of the conductive substrate 11
As a result, SiO 2 is formed on the side surfaces of the openings 22a and 22b._TwoOr
A side wall spacer 23 is formed. This service
The width W1 of the id wall spacer 23 is different from the opening 22a, 2
2b, the width L1 in one direction and the driver transistor Q
₁Gate electrode and access transistor Q₆Word line
The design is made in consideration of the final distance L2 from the WL. Next, as shown in FIG.
The strike pattern 24 is formed. Next, using the resist pattern 24 as a mask,
The interlayer insulating film 20 by RIE or the like.
To Next, after removing the resist pattern 24, the layer
WSi using the interlayer insulating film 20 as a mask_TwoMembrane 19 and polymorph
The crystalline Si film 17 is sequentially anisotropically etched. By this
As shown in FIG. 7, the polycrystalline Si film 17 and the WSi
_TwoDriver transistor Q composed of film 19₁Gate of
Electrode G₁, Word line WL, word line WL ′, and peripheral circuits
Transistor gate electrode G '₁, G '_Two, And its
Another wiring (not shown) is formed. At this time, the gate
Electrode G₁L2 between the word line WL and the word line WL
When the width of the spacer 23 is W1, L2 = L1-2 × W
1, which is smaller than L1. Illustration is omitted.
But with the gate electrode of another driver transistor
Between the word line WL of another access transistor
The gap will be smaller as well. Next, as shown in FIG.
Part of the surface covered with a resist pattern (not shown)
In the state, the gate electrode G₁, G '₁, Word lines WL and
In the p-well 13 using the word line WL 'as a mask, for example,
N-type impurities such as arsenic (As)
For example, dose (1-5) × 10¹³cm^-2Under the conditions
Dope. Next, this n-type impurity is used for ion implantation.
After removing the resist pattern, the portion of the p-well 13 is removed.
With the surface covered with a resist pattern (not shown)
Then, the gate electrode G '_TwoIs used as a mask in n-well 12
Then, for example, by ion implantation, a p-type impurity such as B
For example, dose amount (0.5 to 5) × 10¹³cm^-2Condition
Dope. Next, the resist pattern was removed.
Thereafter, for example, an S-layer of about 150 nm thick is formed on the entire surface by CVD.
iO_TwoAfter forming the film, the SiO_TwoFor example, RIE
Etch perpendicular to the surface of the semiconductor substrate 11 by a method such as
Back to gate electrode G₁, G '₁, G '_Two, Word line
Sidewall spacers on the side surfaces of WL and word line WL '
The sensor 25 is formed. Next, the surface of the n-well 12 is resisted.
Cover with side patterns (not shown)
Spacer 25, gate electrode G₁, G '₁, Word line W
L and word line WL 'as a mask, p well 13
In the inside, for example, an n-type impurity such as As by an ion implantation method.
For example, dose amount (1-5) × 10¹⁵cm^-2Under the condition of
Do Next, it was used for ion implantation of this n-type impurity.
After removing the resist pattern, the p-well 13
With the surface covered with a resist pattern (not shown),
Sidewall spacer 25 and gate electrode G '_TwoTo
As a mask, for example, by ion implantation in the n-well 12
For example, a p-type impurity such as B is added to a dose (1 to 5), for example.
× 10¹⁵cm^-2Doping under the following conditions. Next, this Regis
After removing the gate pattern, if necessary,
Heat treatment is performed for aerial activation. As a result, the n-type
In the side wall spacer 25 in the region doped with a pure substance
On the other hand, n⁺A mold diffusion layer 26 is formed.
This n⁺Type diffusion layer 26 is formed in the side wall spacer 2.
5 on the lower part^-Type low impurity concentration portion 26a
You. Similarly, the side wall is formed in the region doped with the p-type impurity.
P in self-alignment with the⁺Mold diffusion layer
27 are formed. This p⁺Type diffusion layer 27
P on the lower part of the wall spacer 25^-Low impurity of mold
It has a density portion 27a. Next, as shown in FIG.
On the entire surface, for example, a 50 nm thick SiO_TwoMembrane-like isolation
An edge film 28 is formed. Next, a predetermined amount of the interlayer insulating film 28 is formed.
By etching away the part, the bit line contour
Contact hole C_Two, Memory cell grounding
And contact holes for the contacts of peripheral circuits (Figure
(Not shown). Next, by CVD method,
A polycrystalline Si film 29 having a thickness of, for example, 50 nm
After being formed at 20 ° C., for example,
For example, an n-type impurity such as As is implanted by an ON implantation method.
Energy 30 keV, dose amount (1-10) × 10¹⁵
cm^-2Doping under the following conditions. Next, the sputtering method
For example, WSi having a thickness of 50 nm is formed on the entire surface by the CVD method._Twofilm
Form 30. Next, using the resist pattern as a mask
WSi_TwoThe film 30 and the polycrystalline Si film 29 are formed by, for example, RI
Anisotropic etching by E method etc.
Ground wiring, landing pads for bit contacts and
Pattern to the shape of the second wiring layer (not shown)
You. Next, as shown in FIG.
Over the entire surface, for example, a 70 nm thick SiO_TwoInterlayer like membrane
An insulating film 33 is formed. Next, e.g.
Iodine-phosphosilicate glass (BPSG) film 34 over the entire surface
After that, heat treatment is performed at a temperature of about 850 ° C. for 30 minutes.
BPSG film 34 is reflowed. Next, BPSG
A predetermined portion of the film 34 and the interlayer insulating film 33 is removed by etching.
And the driver transistor Q₁Gate electrode G₁With
Contact hole C for contact_ThreeTo form Next
Then, for example, a 50 nm-thick polycrystalline
A Si film 35 is formed at a temperature of about 620 ° C.
A p-type impurity such as B is doped, for example, by ion implantation.
Size (1-10) x 10¹³cm^-2Doping under the following conditions.
Then, using the resist pattern as a mask, the polycrystalline Si film is used.
Etching 35 and patterning it into a predetermined shape
As a result, the load transistor Q_ThreeGate electrode G_ThreeForm
I do. Next, as shown in FIG.
Over the entire surface, for example, a 40 nm thick SiO_TwoGaming like a membrane
The insulating film 36 is formed. This gate insulating film 36 is made of TF
Load transistor Q consisting of T_Three, Q_FourGate insulation film
It becomes. Next, a predetermined portion of the gate insulating film 36 is etched.
Removes the memory cell memory node.
Contact Hall C_FourTo form Next, by the CVD method
Amorphous silicon with a thickness of, for example, about 500 nm on the entire surface
After forming the film at a temperature of about 480 ° C.,
The crystallization is performed by annealing with. Next,
The polycrystalline Si film obtained by crystallization
Etching as a mask to pattern into a predetermined shape
As a result, the load transistor Q_FourChannel region 3
7. Load transistor Q_ThreeChannel area and power supply
Pressure V_DDA supply wiring (not shown) is formed. Then figure
Although not shown, a resist pattern is formed in a predetermined shape
Then, using this resist pattern as a mask,
Jista Q_Three, Q_FourDiffusion layer and power supply voltage V_DDFor supply
Wiring (not shown) is connected to B by ion implantation, for example.
Such a p-type impurity is, for example, a dose amount (2 to 10) × 10¹⁴
cm^-2Doping under the following conditions. In this way, the TFT
Load transistor Q_Three, Q_FourIs formed. Next, as shown in FIG.
Over the entire surface, for example, about 70 nm thick SiO_TwoLayer like membrane
An interlayer insulating film 38 is formed. Next, the entire surface is formed by the CVD method.
For example, a BPSG film 39 having a thickness of about 250 nm was formed.
Thereafter, annealing at a temperature of about 875 ° C.
The G film 39 is reflowed. Next, resist pattern
(Not shown), and using this resist pattern as a mask
BPSG film 39, interlayer insulating film 38, gate insulating film
36, BPSG film 34, interlayer insulating film 33, and interlayer insulating
The film 28 is anisotropically etched by RIE or the like, and
Contact to landing pad for socket contact
Hall C_FiveFor the diffusion layers 26 and 27 in the peripheral circuit section
Kuto Hall C₆, C₇, C₈, C₉, C_TenTo form
Next, for example, the aluminum is
After forming an aluminum (Al) film, this Al film is
Patterning to form a lower layer wiring 40
To achieve. Next, for example, about 40
About 400 nm thick SiO 2 at a temperature of 0 ° C._TwoLayer like membrane
An inter-layer insulating film 41 is formed. Next, spin-on glass (S
OG) After coating the film 42 to a thickness of about 500 nm,
Backing is performed to make the surface almost flat. Next, the CVD method
On the entire surface, for example, SiO having a thickness of about 600 nm_TwoLike a membrane
After forming the interlayer insulating film 43, the interlayer insulating film 43 and the
And predetermined portions of the interlayer insulating film 41 are removed by etching.
Contact hole C for contact to layer wiring 40₁₁To
Form. Next, for example, an Al film is formed by a sputtering method.
Is formed on the entire surface, and then this Al film is
The upper layer wiring 44 is formed by patterning into a fixed shape. Next
Then, for example, in a forming gas at a temperature of about 400 ° C.
After performing the neal, for example, S
A passivation film 45 such as an iN film is formed. Next
Although not shown, the passivation film 45
Bonding by etching and removing specified parts
An opening for the pad is formed, and the desired static RA
Complete M. As explained above,FruitDepends on form
According to the method of manufacturing the static RAM, the driver
Transistor Q₁Gate electrode G₁And access transistor
Q₆Between the word line WL and
The gate electrode of one driver transistor and the other
The distance between the access transistor and the word line WL is
Dimensions below the resolution limit of trilithography
The size of the memory cell can be reduced.
Thus, high integration density of memory cells can be achieved. Ma
In this case, the cell ratio can be increased
Thus, stable operation of the memory cell can be achieved. As described above, the embodiment of the present invention is specifically described.
However, the present invention is limited to the above-described embodiment.
It is not intended to be limited to various types based on the technical idea of the present invention.
Deformation is possible. For example,FruitNumbers listed in the embodiment
The values are only examples and are not intended to be limiting.
There is no. In addition, the aboveFruitIn the embodiment,
Case where Akira is applied to the manufacture of static RAM
As described, the present invention relates to the resolution of photolithography.
Various semiconductors that require formation of sub-dimensional patterns
It can be applied to the manufacture of devices. [0046] As described above, according to the present invention,
According to the method of manufacturing a conductor device, photolithography
It is possible to form a pattern with dimensions below the resolution limit,
For example, in a static RAM, the size of a memory cell
Size can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to a reference example . [2] Static RA by the implementation form of the invention
It is sectional drawing which shows the manufacturing method of M. [3] Static RA by the implementation form of the invention
It is sectional drawing which shows the manufacturing method of M. [4] Static RA by the implementation form of the invention
It is sectional drawing which shows the manufacturing method of M. [Figure 5] static RA by implementation embodiment of the present invention
It is sectional drawing which shows the manufacturing method of M. [6] Static RA by the implementation form of the invention
It is sectional drawing which shows the manufacturing method of M. [7] static RA by implementation embodiment of the present invention
It is sectional drawing which shows the manufacturing method of M. [8] static RA by implementation embodiment of the present invention
It is sectional drawing which shows the manufacturing method of M. [9] Static RA by the implementation form of the invention
It is sectional drawing which shows the manufacturing method of M. [10] Static R by the implementation form of the invention
It is sectional drawing which shows the manufacturing method of AM. [11] Static R by the implementation form of the invention
It is sectional drawing which shows the manufacturing method of AM. [12] Static R by the implementation form of the invention
It is sectional drawing which shows the manufacturing method of AM. FIG. 13 is a plan view showing a structure of a memory cell of a general static RAM. 14 is an equivalent circuit diagram showing a memory cell of the static RAM shown in FIG. DESCRIPTION OF THE SYMBOLS 1, 11 Semiconductor substrate 2 Insulating film 3 First thin film 4 Second thin film 5, 7, 21, 24 Resist pattern 6, 23, 25 Sidewall spacer 12 N well 13 P well 14 Field Insulating films 16, 36 Gate insulating films 17, 29, 35 Polycrystalline Si films 18, 26, 27 Diffusion layers 19, 30 WSi ₂ films 20, 28, 33, 38, 41, 43 Interlayer insulating films 22a, 22b Openings 34, 39 BPSG film 37 Channel region 40 Lower wiring 42 SOG film 44 Upper wiring 45 Passivation films Q ₁ , Q ₂ Driver transistor Q ₃ , Q ₄ Load transistor Q ₅ , Q ₆ Access transistors G ₁ , G ₂ , G ′ ₁ , G _'2 gate electrode WL, WL' word line H _1, H _2, H ₃ opening

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/11 H01L 29/786 H01L 21/8244

Claims (1)

(57) Claims 1. A step of forming an insulating film having an opening for a buried contact on one main surface of a semiconductor substrate, and forming a first film on the entire surface after forming the insulating film. Forming a second thin film serving as a mask material on the first thin film; and providing the second thin film with a first dimension in one direction and using the buried material. Forming a first opening overlapping with the contact opening; forming a third thin film on the entire surface; and etching back the third thin film to form a first spacer on a side surface of the first opening. And forming a second dimension smaller than the resolution limit of photolithography in the one direction by etching the first thin film using the first spacer and the second thin film as a mask, And the above-mentioned belid contact Forming a second opening that overlaps the second opening; and forming the second opening, forming a fourth thin film on the entire surface, and etching back the fourth thin film to form the second opening. Forming a second spacer on the side surface of the opening; and forming the second spacer on the entire surface after forming the second spacer.
Forming a thin film and making a buried contact with the semiconductor substrate through the second opening and the buried contact opening.