JPS63229848A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the operation speed from decelerating by a method wherein the substrate potential of MOS type transfer gate transistor is raised in case of accumulating data to lower the sub-threshold value leakage current while the substrate potential is lowered in case of a reading/writing process. CONSTITUTION:P wells 12 in the line direction on an n type Si substrate are split by SiO2 layers 13 into memory cells 14. Transfer electrodes and word lines 16 are provided on the regions between capacity electrodes 15, n<-> layers 18 and n<+> layers 19 on the regions 14 using polySi 16. The surface is covered with an SiO2 film 20 and openings 21 are made to provide Al bit lines 17 for connection to pick up layers of P wells 12. The P wells 12 connected to Al wirings 23 through the intermediary of the holes 22 are supplied with the substrate potential. In case of reading/writing process, the P wells in the selected line are supplied with a low substrate potential while in case of accumulating data, the P wells in the selected line are supplied with high substrate potential. Through these procedures, the charge accumulated in capacitors shall not leak through the intermediary of a transfer gate transistor not to erase the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to control of substrate potential.

(Prior Art) Generally, a substrate potential is applied to a semiconductor memory device having an MO3 type transfer gate transistor, such as a dynamic RAM. This reduces pit line capacitance,
And the subthreshold leakage current of the transfer gate transistor is reduced. However, as the miniaturization of each element progresses, the channel length of the transfer gate transistor also becomes shorter (for example, L-0.5 μm), and at the currently used substrate potential of about -2V to -3V, as shown in Figure 3, Subthreshold leak current tends to increase. Figure 3 shows the gate voltage of the MO3 type transfer gate transistor. This shows the characteristics of the drain current Io with respect to
In the case of AM, even if information is written, the information cannot be retained.

That is, the charge accumulated in the capacitor escapes via the transfer gate transistor, and the written information is erased. In order to prevent such information loss, the substrate potential must be set deeper than before (for example, -5V).
However, if the substrate potential is set deep (low) in this way, it becomes necessary to apply a high voltage to the gate to turn on the transfer gate transistor, which reduces the speed of writing and reading. Furthermore, when a high voltage is applied to the gate of the transfer gate transistor, a high electric field is applied to the transistor, causing problems such as the gate oxide film being easily destroyed and the device deteriorating.

(Problems to be Solved by the Invention) As described above, in conventional semiconductor memory devices, subthreshold leakage current increases as elements become smaller.
Attempts to reduce this current have the drawback of reducing write and read speeds and deteriorating the device.

This invention was made in view of the above circumstances,
The purpose is to provide a semiconductor memory device that can reduce subthreshold leakage current without reducing write and read speeds or deteriorating elements.

[Structure of the invention] (Means and effects for solving the problem) In other words, in this invention, in order to achieve the above object, a MOS
The substrate potential of the type transfer gate transistor is made deep when information is poorly held, and selectively made shallow only when writing and reading information.

By doing this, the substrate potential of the MOS type transfer gate transistor is deep when holding information, so subthreshold leakage current can be reduced, and it is shallow when writing and reading information, so the operation speed is reduced. There isn't.

Moreover, since it is not necessary to apply a high voltage to the gate to turn on this transistor, the gate oxide film is not easily destroyed due to element deterioration.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(C) show the present invention as a dynamic RAM 1. : Shows the configuration of the memory cell when applied, (a) is a pattern plan view, (b) is (a)
Figure (C) is a cross-sectional view taken along line xx'' in the figure, and Figure (C) is a cross-sectional view taken along line Y-Y' in Figure (a).
11 is, for example, an n-type silicon substrate, and this silicon substrate 11 has p-type well regions 121 and 12.
2.

123 are selectively formed in the row direction. The p-well regions 121, 122, and 123 have element isolation regions 131 and 132 made of silicon oxide film and extending in the column direction.
, and element isolation regions 133 and 134 made of a silicon oxide film and extending in the row direction.

These element isolation regions 131 to 134 form a memory cell region 14. in the p-well region. ~14 days are formed. Note that the element isolation WA area 13 extending in the column direction
1 and 132, the bottoms of which are located above the p-well region [12 (boundary with silicon substrate 11) by a predetermined distance, as shown in FIG. On the other hand, the element isolation region [133.degree. , 122 and 123 questions are also separated. In other words, the memory cell area [141-143.144-1
4. ．． 147 to 149 are element isolation regions 133, respectively.
, 134. Then, the memory cell regions 141 to 149 and the element isolation region 1
31. On t32, capacitor electrodes 151 to 153
and N, which is made of polycrystalline silicon and also serves as a transfer gate.
Poles 161-163 are provided.

That is, the electrodes 151 to 153 on each memory cell region 111141 to 149 function as capacitor electrodes, and the n-
Type diffusion layers 181 to 183 and n+ type diffusion layers 191 to 19
Electrodes 161-163 on the regions between 3 function as transfer gate electrodes and word lines.

Furthermore, capacitor electrode 15. An interlayer insulating film 20 made of a silicon oxide film is formed to cover the entire surface including the tops of the gate electrodes 161 to 153 and the gate electrodes 161 to 163. Contact holes 211 to 219 are opened in this interlayer insulation WA20, and aluminum wiring (
bit lines) 171 to 173 are formed, and the p well region 121 is formed through the contact holes 211 to 21B.
, 122, and 123 are connected to p+ type impurity regions 12a of high 1 degree. Further, contact holes 221 to 223 for applying a substrate potential are formed in the p-well regions 121 to 123, and are connected to a substrate potential generation circuit (substrate potential supply means) not shown through aluminum wirings 231 to 233. be done. This substrate potential generation circuit supplies a potential of, for example, -2V to -3V to the p-well region in which the selected transfer gate transistor is formed when reading or writing information, and the transfer gate transistor of the unselected memory cell is For example, -5V is supplied to the formed p-well region. On the other hand, in the information retention state, for example, -5■ is applied to all p-well regions 121 to 12.
The configuration is such that it supplies to 3.

Next, the operation in the above configuration will be explained.

First, in the case of writing and reading, the substrate potential of the selected row is set shallowly by the output of the substrate potential generation circuit. For example, a substrate potential of, for example, -2■ is applied to the p-well region 121 via the aluminum wiring 231. At this time, the subthreshold leakage current characteristics of the transfer gate transistor become as shown in FIG. 3, and the gate voltage V
Even if o is OV, current flows and the transfer gate transistor is turned on. Therefore, there is no need to apply a high voltage to the gate electrode, and destruction of the gate oxide film due to element deterioration can be prevented. Note that leakage current flows at this time, but in the case of writing, even if there is some leakage current, refreshing (
There is no particular problem since the data will be rewritten (rewritten).

Next, when information is held in the capacitor (non-selected), a substrate potential of, for example, -5V is applied to the p-well region of the selected row. As a result, the subthreshold leak current characteristic of the transfer gate transistor becomes as shown in FIG. 2, and when the gate voltage Va is OV, this current is suppressed to about 1×10'LA [A]. Therefore,
It is possible to prevent the electric charge accumulated in the capacitor from leaking through the transfer gate transistor and to prevent written information from being lost.

According to such a configuration, as described above, the substrate potential of the MOS type transfer gate transistor is deep when information is held, so that subthreshold leakage current can be reduced.

Furthermore, since the depth is shallow during information enrichment and readout, the access speed does not decrease, and there is no need to apply a high voltage to the gate to turn on this transistor, so there is no need to damage the gate oxide film or damage the device. Deterioration etc. can be prevented.

[Effects of the Invention] As described above, according to the present invention, a semiconductor memory device can be obtained in which subthreshold leakage current can be reduced without reducing write and read speeds or deteriorating elements.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing subthreshold leak current characteristics in the device shown in FIG. 1, and FIG. 3 is a diagram for explaining a conventional semiconductor memory device. FIG. 3 is a diagram showing subthreshold leak current characteristics in a storage device. 11... Silicon substrate, 121-123... Well region, 131-134... Element isolation region, 141-1
49...Memory cell area. Applicant's agent Patent attorney Takehiko Suzue Figure 1 VG (V) -

Claims (3)

[Claims] (1) In a semiconductor memory device having a MOS type transfer gate transistor, a substrate potential supply means is provided that makes the substrate potential of the MOS type transfer gate transistor shallow when reading or writing information, and sets it deep when in an information retention state. A semiconductor memory device characterized by: (2) The semiconductor memory device according to claim 1, wherein the substrate potential is supplied to a well region of a conductivity type opposite to that of the semiconductor substrate. (3) The semiconductor memory device according to claim 1, wherein the substrate potential is selectively supplied only to selected rows or columns.