JPH1092954A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a low power consumption and high operation speed by providing gate electrodes through a gate insulation film on the sbstrate surface at two sandwiched regions to form 3-terminal Esaki tunnel elements and by forming circuits with loads each connected to a drain diffusion layer at one end and high level voltage source at the other end. SOLUTION: On the surface of a p-type Si substrate 1, an n<+> type source diffusion layer 2 and a p<+> type drain diffusion layer 3 are selectively formed, gate electrodes 5 are disposed through a gate insulation film 4 on the substrate surface at regions held between the diffusion layers 2, 3 to form 3-terminal Esaki tunnel elements ET, which form a circuit along with loads L where one end of each tunnel element ET is connected to the drain diffusion layer 3 and the other end of each tunnel element ET connected to a high level voltage source Vdd. Thus the low power consumption and high speed operation are realized at once.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device characterized by a storage signal storage unit for storing a storage signal.

[0002]

2. Description of the Related Art An SRAM that statically stores a storage signal is widely used as one of semiconductor storage devices. As the SRAM cell, there is known an SRAM cell composed of six MOS transistors and a SRAM cell composed of four MOS transistors and two high resistance elements. Each SRAM cell requires the use of six elements.

On the other hand, there has been proposed an SRAM cell in which the SRAM cell is composed of three elements (two Esaki diodes and one MOS transistor) and which is effective for high integration (Japanese Patent Laid-Open Publication No. Sho. 58-153295). FIG.
FIG. 9 shows an equivalent circuit diagram of this SRAM cell.

This SRAM cell has two Esaki diodes ED1 and ED2 which are connected in a forward direction between a high level voltage power supply Vdd and a low level voltage power supply Vss, and one of the sources and drains is an Esaki diode. ED1, ED2
And the other source / drain is a bit line BL,
The MOS transistor Tr has a gate connected to the word line WL.

FIG. 30 shows an SRAM constructed as described above.
4 shows current-voltage characteristics of Esaki diodes ED1 and ED2 in a cell.

The intersection points A ₀ and A ₁ between the characteristic curve of the Esaki diode ED1 and the characteristic curve of the Esaki diode ED2
, The state is stabilized and the latch characteristics are exhibited. The SRAM cell uses these two stable states for a storage signal.

The writing and reading of the storage signal and the holding (standby) of the signal charge are performed by the MOS transistor Tr.

That is, in the case of writing, the MOS transistor Tr is turned on, and the selected bit line B
L and the connection point N are electrically connected. As a result, a charge as a storage signal corresponding to the product of the parasitic capacitance and the voltage of the bit line BL is accumulated at the connection point N. Bit line BL
Voltage is chosen to be a stable state in which the system is to correspond to the intersection A ₀ or intersection A _1.

In the case of reading, the MOS transistor Tr is turned on to connect the connection point N as a storage signal.
Is read out from the selected bit line BL. In the case of standby, the operation is performed by turning off the MOS transistor. However, this SRA
The M cell has the following problems.

[0010] That is, the SRAM cell, in order to always flow a constant level of the driving current (tunnel current) I _0, it is difficult to improve the reading speed of the power consumption and the memory signal during standby at the same time. This is because the drive current I ₀ needs to be reduced in order to suppress the power consumption during standby, whereas the drive current I ₀ needs to be increased in order to increase the reading speed.

[0011]

As described above, a conventional SRAM cell using an Esaki diode is an excellent memory cell in terms of high integration, but simultaneously achieves low power consumption and high speed operation. There was a problem that it was difficult to achieve.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory device including a storage signal storage unit effective for high integration, low power consumption, and high speed operation. To provide.

[0013]

[Means for Solving the Problems]

[Summary] In order to achieve the above object, a semiconductor memory device according to the present invention (claim 1) is connected to a semiconductor substrate and a first voltage power supply, and is selectively formed on a surface of the semiconductor substrate. A first conductivity type source diffusion layer, a second conductivity type drain diffusion layer selectively formed on a surface of the semiconductor substrate in a region different from the source diffusion layer, and sandwiched between these two diffusion layers; A first three-terminal Esaki, comprising a gate electrode disposed on the substrate surface of the region via a gate insulating film.
The storage signal storage unit includes a tunnel element and a load having one end connected to the drain diffusion layer and the other end connected to a second voltage power supply.

In another semiconductor memory device according to the present invention (claim 2), in the semiconductor memory device (claim 1), the load is a second three-terminal Esaki tunnel element, a MOS transistor, an Esaki -It is characterized by being a diode or a resistance element. In another semiconductor memory device according to the present invention (claim 3), in the semiconductor memory device (claim 1), the second three-terminal Esaki tunnel element or the gate electrode of the MOS transistor is used as a refresh circuit. It is characterized by being connected.

[Operation] When a predetermined voltage is applied to the gate electrode of the three-terminal Esaki tunnel element to form an inversion layer,
An Esaki diode (tunnel diode) is formed by the inversion layer and a source / drain diffusion layer of the opposite conductivity type to the inversion layer. As a result, the system including the three-terminal Esaki tunnel element and the load can take a plurality of stable states. The plurality of stable states are used for a storage signal as in the case of a conventional system including two Esaki diodes.

The tunnel current of the Esaki diode can be controlled by the gate voltage. That is, as the carrier density of the inversion layer is increased by adjusting the level of the gate voltage, the tunnel current increases.

Thus, according to the present invention, the tunnel current (drive current) can be increased, and the stored signal can be read at high speed. Further, according to the present invention, the tunnel current (drive current) can be reduced, and the power consumption during standby can be reduced.

Further, according to the present invention, the constituent elements of the storage signal storage section include two terminals of a three-terminal Esaki tunnel element and a load.
, It is easy to achieve high integration.

Therefore, according to the present invention, high integration,
It is possible to realize a storage signal storage unit effective for low power consumption and high-speed operation.

[0020]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 14 is an equivalent circuit diagram showing a storage signal storage unit of the SRAM cell according to the embodiment.

The storage signal accumulating section includes a low-level voltage power supply Vss (first voltage power supply) and a high-level voltage power supply Vdd.
(Second voltage power supply) and a three-terminal Esaki tunnel element ET, which is connected in the forward direction to the second terminal and a three-terminal Esaki tunnel element provided between the three-terminal Esaki tunnel element ET and the voltage power supply Vdd. Load L connected in series to ET
It is composed of As the load L, for example, 3
Examples include terminal Esaki tunnel elements, MOS transistors, Esaki diodes, and resistance elements.

FIG. 2 shows a cross-sectional perspective view and a symbol of a three-terminal Esaki tunnel element. In short, the structure of this element is a MOS transistor in which the conductivity type of the source diffusion layer and the conductivity type of the drain diffusion layer are opposite to each other.

In FIG. 1, reference numeral 1 denotes a p-type silicon substrate, and an n ⁺ -type source diffusion layer 2 and a p ⁺ -type drain diffusion layer 3 having a high impurity concentration are selectively formed on the surface of the p-type silicon substrate 1. Is formed.

The n ⁺ -type source diffusion layer 2 has a voltage power supply Vss, p
⁺ Type drain diffusion layer 3 is connected to voltage power supply Vdd. Further, for example, the impurity concentration of the n ⁺ -type source diffusion layer 2 and the p ⁺ -type drain diffusion layer 3 is set to 1 × 10 ¹⁹ / cm ³ or more so that the current-voltage characteristics of the element exhibit negative differential resistance. .

A gate electrode 5 is provided on the surface of the substrate between the n ⁺ -type source diffusion layer 2 and the p ⁺ -type drain diffusion layer 3 with a gate insulating film 4 interposed therebetween.

FIG. 3 shows the current-voltage characteristics of the three-terminal Esaki tunnel device.

When the gate voltage Vg is 0 V, the drain current, more specifically, the diffusion current does not flow unless the drain voltage exceeds a certain value. When the drain voltage exceeds a certain value, the current increases in proportion to the drain voltage.

On the other hand, when the gate voltage Vg is a positive voltage, an n ⁺ -type inversion layer 6 is formed on the substrate surface below the gate electrode 3,
An Esaki diode ED is generated near the interface between the n ⁺ -type inversion layer 6 and the p ⁺ -type drain diffusion layer 3. As a result,
In the three-terminal Esaki tunnel element ET, the current-voltage characteristic shows a negative differential resistance.

As a result, the system including the three-terminal Esaki tunnel element ET and the load L can take a plurality of stable states. The plurality of stable states are used for a storage signal as in the case of a conventional system including two Esaki diodes.

Further, as the gate voltage Vg increases, n
^Since the electron density in the ⁺ type inversion layer 6 increases, if the gate voltage Vg is a positive voltage, the tunnel current increases as the gate voltage Vg increases.

Therefore, a large driving current can be obtained by increasing the gate voltage Vg at the time of reading a storage signal (accumulated charge). On the other hand, during standby, the gate voltage V
Power consumption can be reduced by reducing g and driving current.

The storage signal accumulating section of the present embodiment comprises three
It is composed of two elements, a terminal Esaki tunnel element ET and a load L. On the other hand, the storage signal storage section of the conventional SRAM cell advantageous for high integration shown in FIG. 29 is composed of two elements (Esaki diodes ED1 and ED2). Therefore, the storage signal storage section of the present embodiment is advantageous for high integration, like the conventional SRAM cell of FIG.

As described above, the storage signal storage section of the present embodiment is effective for high integration, low power consumption and high-speed operation. Therefore, if an SRAM cell is configured using the storage signal accumulating unit of the present embodiment, an SRAM with high integration, low power consumption, and high-speed operation can be realized.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 14 is an equivalent circuit diagram showing a storage signal storage unit of the SRAM cell according to the embodiment. In the following drawings, those having the same reference numerals as those in the above-mentioned drawings indicate the same or corresponding portions, and detailed description thereof will be omitted.

The SRAM cell of the present embodiment is obtained by embodying it in the first embodiment, an example using a three-terminal Esaki tunnel device ET _L as a load L. 3 terminal Esaki tunnel element ET, to the gate of the ET _L common gate voltage Vg is applied. Figure 5 shows a current-voltage characteristic of the three-terminal Esaki tunnel device ET _L in configured storage signal storage unit in this way. This is when a positive voltage is applied to the gate electrode.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
FIG. 14 is an equivalent circuit diagram showing a storage signal storage unit of the SRAM cell according to the embodiment.

The SRAM cell of this embodiment is a specific example of that of the first embodiment, and is an example in which a MOS transistor Tr _L is used as the load L. 3 to the gate terminal Esaki tunnel device ET and MOS transistor Tr _L common gate voltage Vg is applied.

FIG. 7 shows three-terminal Esaki tunnel elements ET and M in the storage signal storage section thus configured.
4 shows current-voltage characteristics of the OS transistor Tr _L. This is when a positive voltage is applied to the gate electrode.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
FIG. 14 is an equivalent circuit diagram showing a storage signal storage unit of the SRAM cell according to the embodiment.

The SRAM cell of this embodiment is a specific example of the SRAM cell of the first embodiment.
This is an example using a diode ED. The Esaki diode ED is connected in the forward direction.

FIG. 9 shows the current-voltage characteristics of the three-terminal Esaki tunnel element ET and Esaki diode ED in the storage signal storage section configured as described above. This is when a positive voltage is applied to the gate electrode.

(Fifth Embodiment) FIG. 10 is an equivalent circuit diagram showing a storage signal storage section of an SRAM cell according to a fifth embodiment of the present invention.

The SRAM cell of the present embodiment is a specific example of the SRAM cell of the first embodiment, and is an example in which a resistance element R is used as a load L.

FIG. 11 shows the current-voltage characteristics of the three-terminal Esaki tunnel element ET and the resistance element R in the storage signal storage section configured as described above. This is when a positive voltage is applied to the gate electrode. As shown, 2
The state is stabilized at the intersection points A ₀ and A ₁ of the two characteristic curves.

(Sixth Embodiment) FIG. 12 is an equivalent circuit diagram showing an SRAM cell according to a sixth embodiment of the present invention.

This SRAM cell is constituted by the storage signal storage section of FIG. 1 and the MOS transistor Tr.
One source / drain of the MOS transistor Tr is 3
A connection point N between the terminal Esaki tunnel element ET and the load R,
The other source / drain is connected to the bit line BL, and the gate is connected to the word line WL.

The writing, reading and holding of the stored charge are performed by the MOS transistor Tr.

That is, to write the stored charge, the MO
The S transistor Tr is turned on to electrically connect the selected bit line BL to the connection point N. As a result,
At the connection point N, a charge as a storage signal corresponding to the product of the parasitic capacitance and the voltage of the bit line BL is accumulated at high speed, and the storage signal is written. The voltage of the bit line BL is selected so that the system including the three-terminal Esaki tunnel element ET and the load L is in a stable state.

In order to read out the accumulated charge, a high level positive voltage is applied to the gate of the three-terminal Esaki tunnel element ET, and the tunnel current is drawn to the maximum.
The OS transistor Tr is turned on. As a result, the charge as the storage signal stored at the connection point N is
L will be read out at high speed.

To hold the accumulated charge, a low-level voltage is applied to the gate of the three-terminal Esaki tunnel element ET, and the MOS transistor Tr is turned off while the tunnel current is kept to a minimum. . As a result, the connection point N
Is stored as a storage signal with low power consumption.

(Seventh Embodiment) FIG. 13 is an equivalent circuit diagram showing an SRAM cell according to a seventh embodiment of the present invention. FIG. 14 is a sectional view of a storage signal storage section of the SRAM cell.

The SRAM cell of this embodiment is a specific example of that of the sixth embodiment, and is an example in which the storage signal storage section shown in FIG. 4 is used. The storage signal storage section is formed on the SOI substrate, and the buried oxide film 7 is thin. This is to increase the capacitance at the storage node (connection point N) to increase the amount of charge stored as a storage signal. Thus, the storage signal is not lost even if some leakage current occurs.

In order to increase the capacitance at the storage node, a p ⁻ -type impurity diffusion layer 8 is provided in the region where the inversion layer is formed. The p ⁻ -type impurity diffusion layer 8 reduces the width of the depletion layer of the pn junction and increases the capacitance at the storage node. Note that, depending on the situation, the amount of accumulated charge may be increased by forming a capacitor as in the case of the DRAM cell. In the drawing, reference numeral 9 denotes a wiring (electrode) for short-circuiting the n ⁺ -type source diffusion layer 2 and the p ⁺ -type drain diffusion layer 3.

FIG. 15 shows current / voltage characteristics of the SRAM cell of this embodiment at the time of standby and at the time of reading.
During standby, the gate voltage Vg can be reduced sufficiently,
As shown in FIG. 15, tunnel current is minimized. As a result, power consumption becomes extremely small.

At the time of reading, the gate voltage Vg can be sufficiently increased, so that the tunnel current (drive current) is drawn to the maximum as shown in FIG. as a result,
τ _pd becomes sufficiently small, and the reading speed becomes extremely high.

[0057] Further, SRAM cell of the present embodiment is constituted by three elements of the three-terminal Esaki tunnel element ET, ET _L and the MOS transistor Tr. Thereby, according to the present embodiment, the conventional SRAM of FIG.
The same level of integration as the cell can be achieved.

Therefore, by using the SRAM cell of the present embodiment, it is possible to realize an SRAM with high integration, low power consumption and high-speed operation.

(Eighth Embodiment) FIG. 16 is an equivalent circuit diagram showing an SRAM cell according to an eighth embodiment of the present invention.

This SRAM cell is a specific example of that of the sixth embodiment, and is an example in which a storage signal storage unit having the configuration shown in FIG. 6 is used.

Also in the present embodiment, by controlling the gate voltage Vg, as shown in FIG. 17, the same current and voltage characteristics as those of the sixth embodiment can be obtained during standby and reading, so that low power consumption and low power consumption can be obtained. High-speed operation can be realized.

The SRAM cell according to the present embodiment has an MO
S transistor Tr _L , 3-terminal Esaki tunnel element E
It is composed of three elements, T and a MOS transistor Tr. Thus, according to the present embodiment, it is possible to achieve the same level of high integration as before.

Therefore, by using the SRAM cell of this embodiment, it is possible to realize an SRAM with high integration, low power consumption and high speed operation.

In the present embodiment, to simplify the circuit operation, the gate of the MOS transistor Tr _{L and} the gate of the three-terminal Esaki tunnel element ET are made common. It can be easily realized by optimizing the threshold voltage of Tr _L.

(Ninth Embodiment) FIG. 18 is an equivalent circuit diagram showing an SRAM cell according to a ninth embodiment of the present invention.

The feature of the SRAM cell of this embodiment is that the three-terminal Esaki tunnel elements ET _L and ET are connected in the forward direction.
Is that the gates are independent. That is, the gate voltages Vg1 of the three-terminal Esaki tunnel elements ET _L and ET,
Vg2 can be independently controlled by a gate voltage control circuit.

In the case of the present embodiment, reading of a stored signal,
The holding (standby) is the same as the previous embodiments, but the writing method of the storage signal is different from the previous embodiments.

[0068] That is, when writing low-level storage signal is first 3 while fixing the gate voltage Vg2 of the terminal Esaki tunnel element ET, 3 terminal Esaki tunnel device ET gate voltage of the gate voltage Vg1 of the _L Vg2, and the devices ET and ET, as shown in FIG.
_It is ensured that the number of intersections A _L of the characteristic curve of _L is one, that is, only one stable state is formed on the low voltage side.

Next, the gate voltage Vg1 is gradually increased to the gate voltage Vg.
g2, and as shown in FIG.
_{When the number} of intersections A ₀ and A _{1 of the L} characteristic curve is set to two, the system automatically becomes stable on the low voltage side, and a low-level storage signal is written.

When writing a high-level storage signal,
First, the gate voltage V of the three-terminal Esaki tunnel element ET
With g2 fixed, 3-terminal Esaki tunnel element ET
_L the gate voltage Vg1 of sufficiently higher than the gate voltage Vg2, as shown in FIG. 20, element ET, as intersection A _H characteristic curve of ET _L is one securely, that is, high voltage Only one stable state is formed on the side.

Next, the gate voltage Vg1 is gradually increased to the gate voltage Vg.
g2, and as shown in FIG.
_{When the number} of intersections A ₀ and A _{1 of the L} characteristic curve is set to two, the system automatically becomes stable on the high voltage side, and a high-level storage signal is written.

Note that the two stable states at the intersections A _L and A _H may be low-level and high-level storage signals, respectively. In this case, the two stable states correspond to the low-level and high-level storage signals. It is necessary to generate two voltages using a voltage generation circuit.

As in the case of the SRAM cell of FIG. 13, it is possible to write a storage signal using MOS transistor Tr. In this case, too, two voltages are generated using a voltage generation circuit. There is a need to.

Further, in the present embodiment, the writing of the storage signal when the gate voltage Vg2 is fixed has been described. However, the writing of the storage signal can be performed in the same manner even when the gate voltage Vg1 is fixed. Current-voltage characteristics corresponding to FIGS. 19 and 20 when the gate voltage Vg1 is fixed are shown in FIGS. 21 and 22, respectively.

In the SRAM using the conventional Esaki diode, there is no gate electrode, and therefore, the current / voltage characteristics cannot be changed by the gate voltage. Therefore, the writing method as in this embodiment is impossible. .

(Tenth Embodiment) FIG. 23 is an equivalent circuit diagram showing an SRAM cell according to a tenth embodiment of the present invention.

The SRAM cell of this embodiment has a configuration in which a refresh circuit 11 is provided in the SRAM cell of the seventh embodiment shown in FIG. During standby, refresh circuit 1
According to 1, a so-called refresh operation of recovering a stored signal by applying a pulse voltage to the gate at a constant cycle is performed. This effectively prevents the storage signal from being destroyed due to the loss of the charge as the storage signal stored at the connection point N in the form of a leak current. This embodiment can be similarly applied to the eighth embodiment shown in FIG.

FIG. 24 shows an example of the SRAM cell array. The SRAM cells (cells) are arranged in a matrix, and the SRAM cells (cell) in the same row are connected to the same word line WL, and the SRAM cells (c) in the same column.
ell) are connected to the same bit line BL. This S
Since a RAM cell array is excellent in high integration, it is possible to achieve an integration degree of 1 giga or more.

FIG. 25 shows an example of the sensing method. This is based on the comparison of the magnitude relationship between the voltage of the storage signal (storage voltage) read from the SRAM cell (cell) and the voltage (reference voltage) of the reference signal read from the dummy cell (dummy). Detection circuit) and, for example, "1" if the storage voltage is higher than the reference voltage.
Is detected, and if the storage voltage is smaller than the reference voltage,
Is detected.

When applied to the SRAM cell array of FIG. 24, for example, as shown in FIG.
Are provided with dummy cells. The differential amplifier is common. Then, the SRAM cells are sequentially sensed using the column recorder and the row recorder.

(Eleventh Embodiment) FIG. 27 is an equivalent circuit diagram showing an SRAM cell according to an eleventh embodiment of the present invention.

In the embodiments described so far, the binary memory has been described. For example, if the SRAM cell shown in FIG. 27 is used, the gate voltages Vg1 and Vg2 are controlled as shown below, thereby As shown at 28, four different voltages are obtained as the voltage Vout at the connection point N.
Therefore, by using the cell configuration shown in FIG. 13 and the sensing method shown in FIG. 26, a four-valued memory can be realized.

The gate voltages Vg1 and Vg2 are controlled as follows.

[0084] by controlling the gate voltages Vg1, Vg2, 3 terminal Esaki tunnel device ET _L in the off state, to the ON state 3 pin Esaki tunnel device ET. In this case, the voltage Vout at the connection point N has a value equal to the second voltage power supply Vss.

Also, by controlling the gate voltages Vg1 and Vg2,
3 terminal Esaki tunnel device ET _L ON state, to turn off the three-terminal Esaki tunnel device ET. In this case, the voltage Vout at the connection point N has a value equal to the first voltage power supply Vdd.

Also, by controlling the gate voltages Vg1 and Vg2,
3 terminal Esaki tunnel device ET _L ON state, to turn on the 3 pin Esaki tunnel device ET. In this case, as in the previous embodiments, two stable states (l
(atch1 and latch2), two different voltages are obtained as the voltage Vout at the connection point N. These voltages are voltages between the voltage power supply Vss and the voltage power supply Vdd.

By controlling the gate voltages Vg1 and Vg2 in this way, a total of four different voltages can be obtained as the voltage Vout at the connection point N, and a four-valued memory can be realized.

[0088]

As described in detail above, according to the present invention, 3
By using a storage signal storage unit consisting of a terminal Esaki tunnel element and a load, high integration of the storage signal storage unit is achieved.
Low power consumption and high-speed operation can be realized simultaneously.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a storage signal storage unit of an SRAM cell according to a first embodiment of the present invention.

FIG. 2 is a sectional perspective view of a three-terminal Esaki tunnel element and a diagram showing symbols.

FIG. 3 is a characteristic diagram showing current-voltage characteristics of a three-terminal Esaki tunnel device.

FIG. 4 is an equivalent circuit diagram showing a storage signal storage unit of an SRAM cell according to a second embodiment of the present invention.

FIG. 5 shows a three-terminal Esaki in the storage signal storage section of FIG.
Characteristic diagram showing current-voltage characteristics of tunnel element

FIG. 6 is an equivalent circuit diagram showing a storage signal storage unit of an SRAM cell according to a third embodiment of the present invention.

FIG. 7 is a characteristic diagram showing current / voltage characteristics of a three-terminal Esaki tunnel element and a MOS transistor in the storage signal storage unit configured in FIG. 6;

FIG. 8 is an equivalent circuit diagram showing a storage signal storage section of an SRAM cell according to a fourth embodiment of the present invention.

FIG. 9 shows a three-terminal Esaki in the storage signal storage unit of FIG.
Characteristic diagram showing current-voltage characteristics of tunnel element and Esaki diode

FIG. 10 is an equivalent circuit diagram showing a storage signal storage section of an SRAM cell according to a fifth embodiment of the present invention.

11 is a diagram showing current-voltage characteristics of a three-terminal Esaki tunnel element and a resistance element in the storage signal storage section of FIG.

FIG. 12 is an equivalent circuit diagram showing an SRAM cell according to a sixth embodiment of the present invention.

FIG. 13 is an equivalent circuit diagram showing an SRAM cell according to a seventh embodiment of the present invention.

14 is a cross-sectional view of a storage signal storage section of the SRAM cell of FIG.

FIG. 15 is a characteristic diagram showing current / voltage characteristics of the SRAM cell in FIG. 13 during standby and during reading;

FIG. 16 is an equivalent circuit diagram showing an SRAM cell according to an eighth embodiment of the present invention.

FIG. 17 is a characteristic diagram showing current / voltage characteristics of the SRAM cell in FIG. 16 during standby and during reading;

FIG. 18 is an equivalent circuit diagram showing an SRAM cell according to a ninth embodiment of the present invention.

FIG. 19 is a characteristic diagram showing current / voltage characteristics when a low-level storage signal is written in the SRAM cell of FIG. 18;

20 is a characteristic diagram showing current / voltage characteristics when writing a high-level storage signal in the SRAM cell of FIG. 18;

21 is another characteristic diagram showing current / voltage characteristics when writing a low-level storage signal in the SRAM cell of FIG. 18;

22 is another characteristic diagram showing current / voltage characteristics when writing a high-level storage signal in the SRAM cell of FIG. 18;

FIG. 23 is an equivalent circuit diagram showing an SRAM cell according to a tenth embodiment of the present invention.

FIG. 24 is a diagram showing an example of an SRAM cell array.

FIG. 25 illustrates an example of a sensing method.

FIG. 26 is a view for explaining an example in which the sensing method of FIG. 25 is applied to the SRAM cell array of FIG. 24;

FIG. 27 is an equivalent circuit diagram showing an SRAM cell according to an eleventh embodiment of the present invention.

FIG. 28 is a diagram showing a method of writing a storage signal in the SRAM cell of FIG. 27;

FIG. 29 shows a conventional SRAM using an Esaki diode.
Cell equivalent circuit diagram

FIG. 30 is a characteristic diagram showing current-voltage characteristics of Esaki diodes ED1 and ED2 in the SRAM cell of FIG. 29;

[Explanation of symbols]

Vss ... low-level voltage supply (first voltage supply) Vdd ... high voltage power supply (second voltage supply) ED ... Esaki diode ET ... 3 terminal Esaki tunnel device ET _L ... 3 terminal Esaki tunnel device (Load) L ... Load R ... Resistance Tr ... MOS transistor TrL ... MOS transistor (load) 1 ... p-type silicon substrate 2 ... n ⁺ type source diffusion layer 3 ... p ⁺ type drain diffusion layer 4 ... gate insulating film 5 ... gate electrode 6 ... n ⁺ -type inversion layer 7 ... buried oxide film 8 ... p ^- -type impurity diffusion layer 9 ... wire (electrode)

Claims (3)

[Claims] A first conductive type source diffusion layer connected to a semiconductor substrate and a first voltage power supply and selectively formed on a surface of the semiconductor substrate; and a source diffusion layer in a region different from the source diffusion layer. A drain diffusion layer of the second conductivity type selectively formed on the surface of the semiconductor substrate, and a gate electrode disposed on the substrate surface in a region interposed between the two diffusion layers via a gate insulating film. A semiconductor signal storage device comprising: a first three-terminal Esaki tunnel device; a storage signal storage unit including one end connected to the drain diffusion layer and the other end connected to a load connected to a second voltage power supply. apparatus. 2. The semiconductor memory device according to claim 1, wherein said load is a second three-terminal Esaki tunnel element, a MOS transistor, an Esaki diode, or a resistance element. 3. The semiconductor memory device according to claim 1, wherein said second three-terminal Esaki tunnel element or a gate electrode of said MOS transistor is connected to a refresh circuit.