JP2003069417A - Semiconductor device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device acting like a memory cell employing a negative resistive element operated at a high-speed even under a low voltage and to provide its drive method. SOLUTION: The semiconductor device includes a series connection comprising two IBTDs 12, 13 and a DTMOS whose source electrode is connected to a memory node 17 between the IBTDs 12 and 13 and whose drain electrode is connected to a bit line 15. Since the gate and the body region of the DTMOS for controlling data input output are connected to a word line 16, even when a gate voltage of the DTMOS is low at data input output, the drain current is increased more than that of a conventional semiconductor device to deliver data at a higher speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a negative resistance element.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits have been formed based on the technology of MOS type elements. The MOS type device has a feature that its operating speed, power consumption and degree of integration are improved by miniaturization, and has played a very important role in industry. However, due to the limit of fine processing and statistical fluctuation of impurity concentration, it is industrially 0.1 μm.
It is considered that it is very difficult to put the MOS-type device after the m-th generation into practical use.

On the other hand, in the market, further integration of LSIs and memories and reduction of power consumption are demanded for wearable portable devices.

Currently, memories used in portable devices are mainly volatile static random access memory (SRAM) and dynamic random access memory DRAM. However, the current SRAM and DRA
It is difficult for M to satisfy both low power consumption and high integration.

Since a DRAM memory cell can be formed by one transistor and one capacitor, the cell area per cell is small and is highly integrated. However, there is a disadvantage in that the power consumption is high because the periodic refresh operation is required to hold the data. On the other hand, the SRAM memory cell is excellent in high speed and low power consumption, but the CMOS type memory cell which has been often used conventionally is formed of six transistors.
It has a drawback that it has a large cell area and is not suitable for high integration.

On the other hand, various memory cells using an element whose operation principle is completely different from that of a MOS type element have been proposed so far.

For example, Esaki tunnel diode (L. Esaki, Ph
ys.Rev., 109, (1953), 603) using a bistable circuit in which two ys.Rev., 109, (1953), 603) are connected in series.
Proposed by E. Goto et al. In 1960 (E. Goto et al., I
RE Trans. Electron. Comp., March, 1960, p.25). Furthermore, if a transistor for writing and reading data is added to the memory node (connection point of two negative resistance elements) of a bistable circuit in which two negative resistance elements are connected in series, a conventional SRAM cell is obtained. A memory cell can be formed by three elements, which is half the number of elements. The SRAM based on the negative resistance element has a small cell area and is suitable for high integration, and does not require a regular refresh operation unlike DRAM, and thus has low power consumption and high integration. It is an SRAM cell.

Furthermore, in order to realize an SRAM cell suitable for high integration, a negative resistance element is a Si interband tunnel element (= IBTD: K. Morita et al, Ext.Abst.DRC'98, 42).
(1998)) was proposed.

The IBTD has a structure in which a tunnel insulating film (oxide film, nitride film, etc.) having a very thin film thickness (2 nm or less) is inserted between the degenerated pn junctions. Due to the energy barrier of this tunnel insulating film, the IBTD effectively suppresses the thermal forward bias current as compared with the band-to-band tunnel current, and exhibits a remarkable negative resistance characteristic at room temperature. Also,
Mutual diffusion of dopant impurities is suppressed by the tunnel insulating film, and a steep pn junction can be formed with a high yield.

FIG. 2 is a circuit diagram showing a conventional memory cell using IBTD.

As shown in FIG. 1, the conventional memory cell is
IBTD112 and IBTD1 connected in series with each other
13 and the source electrodes are IBTD112 and IBTD113
And an I / O control MOS transistor 111 whose drain electrode is connected to the bit line 115. Input / output control MOS
On / off of the transistor 111 is controlled by a word line 116, and the IBTD 112 and the IBTD 113 form a latch circuit 114. In addition, the latch circuit 114
Has one end connected to the power supply voltage line 118 and the other end connected to the ground line 1
It is connected to 19.

As described above, if a negative resistance-based bistable circuit using IBTD and a transistor are used, 0.5 V
It is possible to configure a highly integrated SRAM circuit that operates at the following ultra-low voltage.

[0013]

However, when a conventional MOS type element is used as a writing and reading transistor in a memory cell, the drain current value at an ultra-low voltage of 0.5 V or less is low, and therefore IBTD There is a problem that it takes a long time to switch the formed bistable state. This allows the IB
Since the operation speed of writing and reading operations of the memory circuit using the TD becomes slow, it is difficult to operate the memory cell at high speed when all the voltages in the memory cell are low voltage of 0.5 V or less. .

It is an object of the present invention to provide a semiconductor device which functions as a memory cell and operates at a high speed under a low voltage by using a negative resistance element such as IBTD, and a driving method thereof.

[0015]

The semiconductor device of the present invention comprises:
A bit line supplying a voltage for inputting / outputting data, two elements including at least one negative resistance element connected in series with each other via a memory node, the bit line and the memory node A semiconductor device having a field effect transistor interposed between the word line and a word line supplying a voltage for controlling on / off of the field effect transistor, the semiconductor device functioning as a memory cell, comprising: The gate electrode of the effect transistor and the body region are electrically connected.

As a result, since the gate electrode of the field effect transistor and the body region are electrically connected, even if the voltage applied to the gate electrode of the field effect transistor is as low as 0.5 V or less, it is usually MOS
A driving current larger than that of a transistor flows. Since this drive current is used for data input / output,
The semiconductor device of the present invention can operate as a memory cell even under a low voltage. In addition, when the gate voltage is not normally applied (0 V) and the data is held in the memory cell, the leakage current from the transistor is also a normal MOS.
This is equivalent to using a transistor.

Further, the semiconductor device of the present invention includes two bit lines each including a bit line supplying a voltage for inputting / outputting data and at least one negative resistance element connected in series via a memory node. An element, a field effect transistor interposed between the bit line and the memory node, and a word line for supplying a voltage for controlling on / off of the field effect transistor, A semiconductor device functioning as a cell may include means for controlling the voltage of the body region of the field effect transistor.

Thus, for example, when inputting / outputting data to / from the memory cell, the voltage applied to the body region of the field effect transistor is made equal to the gate voltage to increase the drive current, and the data is held in the memory cell. At times, it is possible to apply a negative voltage to the body without changing the gate voltage to reduce the leakage current from the transistor, and to increase the degree of freedom in designing the semiconductor device.

The above field effect transistor has the S
By using a heterojunction field effect transistor in which a semiconductor layer containing Si and at least one of Ge and C is stacked on the i layer, for example, SiGe or SiGeC having a higher carrier mobility than silicon is used.
When is used as a channel layer, the speed of data input / output operation can be improved.

A semiconductor device driving method of the present invention includes a bit line supplying a voltage for inputting / outputting data, and at least one negative resistance element connected in series with each other through a memory node. One element, a field effect transistor interposed between the bit line and the memory node, and a word line that supplies a voltage for controlling on / off of the field effect transistor, A method of driving a semiconductor device functioning as a memory cell, comprising applying a voltage for writing data from the bit line, and applying a voltage higher than a ground potential to the gate electrode and the body region of the field effect transistor. Then, the data is written in the memory cell.

According to this method, since a voltage higher than the ground voltage is applied to both the gate electrode and the body region of the field effect transistor, it is large even when the gate voltage is low as compared with the case where the voltage is applied only to the gate electrode. The drive current will flow. Therefore, even when the gate voltage is low, data can be written in the memory cell.

In particular, when writing the data in the memory cell, by applying the same voltage to the gate electrode and the body region of the field effect transistor, a large drive current flows even if the gate voltage is low, so that Data can be written more reliably when the voltage is low.

When the data is written in the memory cell, the range of voltage applied to the gate electrode and the body region of the field effect transistor is 0.2 V or more and 1.0 V or less, so that the memory including the field effect transistor. The cell operates normally, and the data write operation can be performed more reliably.

Data is read by applying a voltage higher than the ground potential to the gate electrode and the body region of the field effect transistor, so that even if the gate voltage is small, it is larger than that of a normal field effect transistor. Since the drive current flows, data input / output can be reliably performed.

By applying the same voltage to the gate electrode and the body region of the field-effect transistor when reading data, the data storage operation can be surely performed even when the gate voltage is low.

When the data is held in the memory cell, the voltage applied to the gate electrode and the body region of the field effect transistor is in the range of -1.0V to 0V, so that the field effect transistor is Since the leakage current from the device is suppressed to a small value, the destruction of the latch data can be suppressed, and the current consumption during standby can be decreased.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a circuit diagram showing an SRAM cell which is a semiconductor device according to an embodiment of the present invention.

As shown in the figure, the semiconductor device of this embodiment has an IBTD (negative resistance element) 12 and an IBTD 13 connected in series with each other, and a source electrode IBTD1.
2 and an IBTD 13 and a transistor 11 which is a DT (Dynamic Threshold) MOS for input / output control, which is connected to a memory node 17 and whose drain electrode is connected to a bit line 15. The gate of the DTMOS transistor and the body region of the substrate are electrically connected to each other. The input / output control MOS transistor 11 is controlled to be turned on / off by the word line 16, and the IBTD 12 and IB
The TD 13 constitutes a latch circuit 14. Further, one end of the latch circuit 14 is connected to the power supply voltage line 18, and the other end is connected to the ground line 19. Further, the IBTD 12 and the IBTD 13 have different current-voltage characteristics from each other.

The DTMOS used in this embodiment is F.
A field-effect transistor proposed by Assaderaghi et al., By electrically connecting the gate and body region, a large drive current can be obtained at a lower threshold voltage than that of a normal MOS transistor, and high-speed operation is possible. (Int. Electron Devices Meet. Tech. Dig., Pp.8
09-812).

In the semiconductor device of this embodiment, the DTMOS
Is used as a data input / output control transistor, a sufficient drain current can be obtained even when the voltage of the latch circuit 14 is as low as 0.5 V or less. In addition, the time required to input / output data is greatly reduced.

Next, the operation of the semiconductor device of this embodiment will be described.

FIG. 3 is a characteristic diagram showing current-forward voltage characteristics of the latch circuit 14 shown in FIG. A characteristic curve 20 in the figure shows a current-forward voltage characteristic of the IBTD 13.
The characteristic curve 21 shows the current-forward voltage characteristic of the IBTD 12. Further, the power supply voltage 24 of the latch circuit 14 is indicated by ◯. Of the points where the characteristic curve 20 and the characteristic curve 21 intersect, the low voltage side is the first stable point 22 and the high voltage side is the second stable point 23. These two points are stable points at which data can be latched.

In the semiconductor device of this embodiment, the first
The stable point 22 can represent the data “0”, and the second stable point 23 can represent the data “1”. For example, the latch circuit 1
When the power supply voltage applied to No. 4 is 0.4V, the voltage value of the lower stable point is about 0.02V, and the higher stable point is about 0.38V. The transistor 11 controls input / output of data latched by the memory node 17 of the latch circuit 14.

First, when inputting data, bit line 1
A voltage close to the voltage of the data to be input to 5 is applied, and a voltage of 0.5 V or less is applied to the word line 16 to turn on the transistor 11. At this time, the transistor 1
The voltage of the word line 16 is applied to the substrate electrode of the transistor 11 connected to the word line 16 as in the case of the gate electrode of No. 1 and the transistor 11 is dynamically threshold-driven, so that a larger drain current than that of a normal MOS transistor is generated in the latch circuit 14. To the memory node 17.
The drain current value is larger than the peak current value of IBTD,
If the capacity of the IBTD can be charged or discharged up to the voltage value at the stable point, the data of the latch circuit 14 will be the bit line 15 data.
It is rewritten to the desired data prepared in.

In the semiconductor device of the present invention, since the transistor 11 for controlling data input is driven by dynamic threshold, data is input by a large drain current even under a low voltage as compared with the conventional semiconductor device. It is possible to write desired data at higher speed.

Similar to the input operation, the output operation can be speeded up by the semiconductor device of this embodiment. In the output operation, contrary to the input operation, the voltage of the memory node 17 in the memory cell is transmitted to the bit line 15. The dynamic threshold drive of the transistor 11 allows a larger drain current to flow under a low voltage than that of a conventional semiconductor device, so that desired data can be read at a higher speed.

However, if the capacity of the bit line is much larger than the capacity of the memory node 17, there is a risk of destructive reading of data. In that case, the read data can be prevented from being destroyed by reading and rewriting the read data using a sense amplifier capable of rewriting the read data, for example, a cross sense amplifier. The sense amplifier may have the same structure as that used in a general DRAM.

In the semiconductor device of this embodiment, IB
It is necessary to always supply current from the power supply voltage line 18 connected to TD. However, since the current required for the IBTD operation is small, a DRAM that requires a refresh operation is required.
Compared with the above, the semiconductor device of this embodiment can reduce power consumption.

In the semiconductor device of this embodiment, data is input and output through the same path, but a read-only circuit can be connected to the memory node 17, for example. However, in that case, the area of the memory cell becomes large.

Next, in order to show the effectiveness of the present invention, the operation of the semiconductor device of this embodiment and the operation of the conventional semiconductor device were compared by actually measuring the voltage waveform at the time of data input.

FIGS. 6A and 6B show the memory node, the word line and the bit line when data "1" and "0" are input to the semiconductor device of this embodiment and the conventional semiconductor device, respectively. FIG. 6 is a waveform diagram showing the result of measuring the voltage waveform of No. 2 with an oscilloscope.

A voltage of 0.4 V, which is slightly higher than the stable point of the latch circuit, is applied to the bit line (see FIG. 6).
(See (a) 31 and FIG. 6 (b) 35), when 0.5V is applied to the word line (32 in FIG. 6 (a) and FIG.
(See (b) 36), the voltage of the memory node begins to rise, and eventually settles to a stable point having a value slightly lower than 0.4V. This voltage change is as shown in FIGS.
It was found in both this embodiment and the conventional semiconductor device. Next, even if the voltage of the word line becomes 0V and the transistor is turned off, the voltage of the memory node is kept at about 0.38V which is the voltage value at the stable point, indicating that the memory is operating normally. It could be confirmed.

The rising waveform and the rising time until reaching the stable point are shorter in the semiconductor device of this embodiment shown in FIG. 6A than in the conventional semiconductor device shown in FIG. For semiconductor devices, the rise time is about 18
In contrast to ms, in the present embodiment, about 340
It was possible to reduce the rise time to about 1/50 μs (see 33 and 34 in FIG. 6A).

On the other hand, the fall time when data "0" is input is about 7.6 in the semiconductor device of this embodiment.
μs, about 50 μs in the conventional semiconductor device, and the fall time is greatly shortened in the semiconductor device of this embodiment.

Next, the current of the input / output control transistor −
The voltage characteristics will be described with reference to the drawings.

FIG. 7 is a characteristic diagram showing typical Id-Vg characteristics of a DTMOS used as an input / output control transistor and a normal MOS transistor (Id is drain current, Vg is gate voltage). From the figure, 0.5V
At the gate voltage of
In the case of S (see graph 41), a normal M indicated by a circle
It can be seen that the drain current is about one digit higher than that of the OS transistor (see graph 42). From this result, by using the DTMOS in the memory cell, the data input can be speeded up when the voltage in the memory cell is driven at a low voltage of at least 0.5 V or less as compared with the case of using a normal MOS transistor. It is thought to be possible. Although only the voltage range of 0.5 V or less is shown in FIG. 7, data input is actually performed without any problem even if the maximum value of the gate voltage applied to the DTMOS in a pulse shape is about 1.0 V. . The maximum gate voltage is 0.2
V to 1.0 V is preferable, and 0.2 V to 0.5 V is more preferable.

Further, in the case of DTMOS, the subthreshold characteristic is improved as compared with a normal MOS transistor, and S
Value (Vg change rate with respect to Id: Unit mV / decad
Since e) becomes small, the drain current of DTMOS becomes smaller than that of a normal MOS transistor in the negative region where the gate voltage is 0 V, and so-called leakage current of the transistor is reduced. Therefore, in the semiconductor device of the present embodiment, the voltage in the negative region (less than 0 V is -1.0.
(V or more is preferable) is set to the minimum voltage value applied to the gate during standby, the leakage current of the transistor becomes smaller, so that the destruction of latch data due to leakage is suppressed and the current consumption during standby is reduced. You can

The transistors and IB used in this measurement
TD has a transistor W = 50 to 200 μm, a gate length of 5 μm, a gate oxide film thickness of 30 nm, and an IBTD element area of 1 × 10 ⁻³ cm ² , which is larger than that actually used. Input time is sub ms
~ It is as long as several tens of ms, but transistors and IBTs
When the size of D is miniaturized, the driving force of the transistor is improved and the element capacitance of the IBTD is reduced, so that a higher speed operation can be obtained as described below.

FIG. 8 is a graph showing the relationship between the data write time and the IBTD size in the conventional semiconductor device having the IBTD formed on the Si substrate. However, the size of the transistor is fixed, the bit line voltage during writing is 0.4 V, and the current value during writing is 0.9 m.
It is A. In addition, the graph shown by the dotted line in the figure shows the simulation result, and the data shown by the mark ◯ shows the measured value.

From the figure, it can be seen that the data write time is shortened as the IBTD size is reduced. Further, this measured value is in good agreement with the simulation result, and it is estimated from this simulation result that by reducing the size of the IBTD to 1 μcm ² , the data writing speed at the memory cell level is about 6
It can be improved to 0 ps.

It is to be noted that the measurement here is performed on the conventional semiconductor device having a normal MOS transistor, but the change of the writing time due to miniaturization is also the same in the semiconductor device of the present embodiment having a DTMOS. it is conceivable that.

As described above, according to the semiconductor device of the present embodiment, by using the DTMOS as the input / output control transistor, it is possible to operate at a high speed even under a low voltage as compared with the conventional semiconductor device, and the transistor is used. It is possible to reduce the leakage current from.

That is, it can be said that the semiconductor device of this embodiment which functions as a memory cell is a semiconductor device which has high speed and low power consumption, has a small cell area, and is suitable for high integration.

Although the DTMOS is used as the data input / output control transistor in this embodiment, the channel layer in the substrate or the layer that induces strain in the channel layer has a band gap larger than that of Si such as SiGe or SiGeC. A hetero DTMOS using a small material may be used. As a result, the mobility of carriers in the channel layer is higher than that in ordinary Si, and thus the driving force of the transistor is increased. That is, data input / output can be performed at higher speed.

Alternatively, as the input / output control transistor, a VT-MOS in which the body region of the MOS transistor is connected to a voltage source different from the word line can be used.

FIG. 1B is a circuit diagram showing a first modification of the semiconductor device of this embodiment using a VT-MOS as an input / output control transistor.

In the case of this modification, the VT-MO is controlled from the body voltage control line 19b when writing and reading data.
By applying a positive body voltage to the body of S, the drain current can be increased, and at other times, a negative body voltage can be applied to suppress the leak current. This increases the degree of freedom in circuit design.

Further, the IBTD used in this embodiment has, for example, Si doped with a high concentration of p-type impurities.
On the substrate, a SiO ₂ film with a thickness of 2 nm or less, a high concentration n
Since a MOS structure, such as sequentially forming a polysilicon film doped with a type impurity, can be adopted, it can be easily manufactured using a normal MOS transistor manufacturing facility. The DTMOS may be either an n-channel type or a p-channel type.
The IBTD can be formed on the source of the TMOS, which is advantageous for high integration.

Although IBTD is used as the negative resistance element in the present embodiment, a tunnel diode having no insulating film sandwiched between pn junctions may be used instead of IBTD.

In addition, as a combination of elements,
At least one of the two elements may be a negative resistance element.

FIGS. 4A and 4B are circuit diagrams showing a second modification of the semiconductor device of the present embodiment in which the latch circuit 14 is composed of the IBTD 13 and the resistance element 40, respectively, and the semiconductor device at that time. 3 is a characteristic diagram showing current-voltage characteristics of the latch circuit included in FIG.

FIGS. 5A and 5B show a third modification of the semiconductor device of this embodiment in which the latch circuit 14 is composed of the IBTD 13 and the n-type depletion type transistor 42, respectively. FIG. 3 is a circuit diagram and a characteristic diagram showing current-voltage characteristics of a latch circuit included in a semiconductor device at that time.

As shown in FIG. 4A, when the latch circuit is composed of the IBTD 13 which is a negative resistance element and the resistance element 40, as shown in FIG. 4B, the characteristic straight line of the resistance element 40. 41 between the characteristic curve 20 of IBTD13 and 2
You can get a stable point. However, in this case, 2
It is difficult to increase the potential difference between two stable points.
Since the current value at the stable point 22 becomes large, the power consumption becomes large.

Even if the latch circuit is composed of the IBTD 13 which is a negative resistance element and the depletion type transistor 42 as shown in FIG. 5A, the depletion type transistor 42 is provided as shown in FIG. 5B. Characteristic straight line 4
Two stable points can be taken between 3 and the characteristic curve 20 of the IBTD 13. In this case, the potential difference between the two stable points can be made large, but the current value at the first stable point 22 becomes large.

In the semiconductor device of this embodiment, it is possible to combine the elements as described above, but since the voltage difference between the two stable points can be made large and the power consumption is small, the elements used in the present invention are as follows: A combination of tunnel diodes is preferable.

The larger the ratio (PV ratio) of the upper and lower peak currents in the current-voltage curve (see FIG. 3) of the tunnel diode used in this embodiment, the larger the voltage difference between the two stable points becomes. The larger the ratio, the better.
Add other compounds to Si to increase PV ratio,
A compound semiconductor substrate other than Si may be used.

[0067]

According to the semiconductor device and the method of driving the same of the present invention, since the gate electrode of the control transistor and the body region (substrate region) are electrically connected at the time of inputting / outputting data, it is low. Since the drain current value under the gate voltage becomes larger than that of the conventional semiconductor device,
When inputting / outputting the data latched in the latch circuit including the series connection of the negative resistance elements, the data transmission can be further speeded up.

[Brief description of drawings]

1A and 1B are a circuit diagram showing a semiconductor device according to an embodiment of the present invention and a circuit diagram showing a first modified example of the semiconductor device of the present embodiment, respectively.

FIG. 2 is a circuit diagram showing a conventional semiconductor device.

FIG. 3 is a characteristic diagram showing current-voltage characteristics of a latch circuit included in the semiconductor device according to the embodiment of the present invention.

4 (a) and 4 (b) respectively show a latch circuit IB.
FIG. 9 is a circuit diagram showing a second modification of the semiconductor device of the present embodiment configured by TDs and resistance elements, and a characteristic diagram showing current-voltage characteristics of a latch circuit included in the semiconductor device at that time.

5 (a) and 5 (b) respectively show a latch circuit IB.
A circuit diagram showing a third modification of the semiconductor device of the present embodiment composed of TDs and n-type depletion type transistors, and a characteristic diagram showing current-voltage characteristics of a latch circuit included in the semiconductor device at that time. Is.

FIG. 6A and FIG. 6B are measured waveform diagrams showing changes over time in the voltage on the bit line, the word line, and the memory node at the time of data input of the semiconductor device according to the embodiment of the present invention, respectively. FIG. 9 is an actually measured waveform diagram showing changes over time in voltage on a bit line, a word line, and a memory node in a semiconductor device.

FIG. 7 is a characteristic diagram showing measurement results of current-voltage characteristics of the DTMOS included in the semiconductor device according to the embodiment of the present invention and the MOS transistor included in the conventional semiconductor device.

FIG. 8 is a graph showing the relationship between the size of IBTD and the write time in the semiconductor device of the present invention.

[Explanation of symbols]

11 transistors 12,13 IBTD 14 Latch circuit 15 bit line 16 word lines 17 memory nodes 18 Power supply voltage line 19 Ground wire 19b Body voltage control line 20 IBTD13 current-voltage characteristic curve 21 IBTD12 current-voltage characteristic curve 22 First stable point 23 Second stable point 24 Latch circuit power supply voltage

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kiyoyuki Morita             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5B015 HH01 HH03 JJ21 KA04 KA13                       QQ01 QQ08                 5F083 BS50 GA05 GA09                 5J056 AA03 BB02 BB16 BB17 BB51                       CC14 DD00 EE04 KK01 KK03

Claims (9)

[Claims] 1. A bit line supplying a voltage for inputting / outputting data, two elements including at least one negative resistance element connected in series with each other via a memory node, and the bit line. A semiconductor device having a field effect transistor interposed between the memory node and a word line supplying a voltage for controlling ON / OFF of the field effect transistor, the semiconductor device functioning as a memory cell. A semiconductor device in which the gate electrode of the field effect transistor and the body region are electrically connected. 2. A bit line supplying a voltage for inputting / outputting data, two elements including at least one negative resistance element connected in series via a memory node, and the bit line. A semiconductor device having a field effect transistor interposed between the memory node and a word line supplying a voltage for controlling ON / OFF of the field effect transistor, the semiconductor device functioning as a memory cell. A semiconductor device comprising means for controlling the voltage of the body region of the field effect transistor. 3. The semiconductor device according to claim 1, wherein the field effect transistor has an S layer on a Si layer of a substrate.
A semiconductor device, which is a heterojunction field effect transistor in which a semiconductor layer containing i and at least one of Ge and C is laminated. 4. A bit line supplying a voltage for inputting / outputting data, two elements including at least one negative resistance element connected in series with each other via a memory node, and the bit line. A semiconductor device having a field-effect transistor interposed between the memory node and a word line supplying a voltage for controlling on / off of the field-effect transistor, which functions as a memory cell. A driving method, wherein a voltage for writing data is applied from the bit line, and a voltage higher than a ground potential is applied to the gate electrode and the body region of the field effect transistor to write data in the memory cell. A method for driving a semiconductor device, comprising: 5. The method of driving a semiconductor device according to claim 4, wherein the same voltage is applied to the gate electrode and the body region of the field effect transistor when writing data in the memory cell. Method for driving a semiconductor device. 6. The method for driving a semiconductor device according to claim 4 or 5, wherein a range of voltage applied to the gate electrode and the body region of the field effect transistor is 0. A semiconductor device having a voltage of 2 V or more and 1.0 V or less. 7. The method of driving a semiconductor device according to claim 4, wherein a voltage higher than a ground potential is applied to the gate electrode and the body region of the field effect transistor. A method for driving a semiconductor device, which comprises reading data. 8. The method for driving a semiconductor device according to claim 4, wherein the same voltage is applied to the gate electrode and the body region of the field effect transistor when reading data. A method for driving a semiconductor device, comprising: 9. The method for driving a semiconductor device according to claim 4, wherein when data is held in a memory cell, the field effect transistor has a gate electrode and a body region. A method for driving a semiconductor device, wherein the range of applied voltage is −1.0 V or higher and 0 V or lower.