KR20000045902A - Memory cell structure of sdram having pnpn diode and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A memory cell structure of a SDRAM and method for manufacturing the same is to improve a current transmitting ability of an access transistor. CONSTITUTION: A memory cell structure of a SDRAM includes: a first and second pull-up transistors(T3,T4) which are connected in parallel to a source voltage(Vcc); a first and second drive transistors(T1,T2) which are respectively connected to a ground voltage(GND) and output terminals of the pull-up transistors; the first access transistor(T5) for applying a signal of a bit line(B/L) to gates of the second pull-up transistor and the second drive transistor, and to a common node of the first pull-up transistor and the first drive transistor in response to a first word line(W/L); and a second access transistor(T6) for applying a signal of an inverted bit line(/B/L) to gates of the first pull-up transistor and the first drive transistor, and to a common node of the second pull-up transistor and the second drive transistor in response to a second word line(W/L). A PNPN diode consisting of a two bipolar transistor(BTr1,BTr and BTr3,BTr4) is provided between the bit line and the first access transistor, and between the inverted bit line and the second access transistor.

Description

Memory cell structure of SRAM device having VRN diode and method of forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to static random access memory (SRAM), and more particularly, to a memory cell structure of a SRAM device having a pnpn diode capable of improving the current driving capability of an access transistor connected to a bit line, and a method of forming the same.

As a semiconductor memory device, SRAM is widely used in the medium and small-capacity memory field because of its high speed and ease of use, although it is lower in memory capacity than DRAM (Dynamic Random Access Memory). The memory cell of the SRAM consists of two flip-flop circuits consisting of two access transistors, two driving transistors, and two load elements, a pull-up transistor, and memory information is stored between the input and output terminals of the flip-flop. It is preserved by the voltage difference, i.e., the charge accumulated in the stray capacitance at the node. This charge is always replenished from the power supply voltage supply line (V _CC line) through a load MOS transistor or a load resistor, which is a load element, so that a refresh function is unnecessary as in DRAM.

1A to 1B are circuit diagrams showing a memory cell structure of a conventional SRAM device, respectively, and a vertical cross sectional view between an access transistor and a bit line in a memory cell.

As shown in FIG. 1A, a memory cell structure of a conventional SRAM device includes first and second driving transistors T1 and T2 connected in parallel to a ground voltage Vss terminal, and the transistors T1 and T2, respectively. The first and second pull-up transistors T3 and T4 connected to the power supply voltage terminal and the word line W / L are turned on to transmit a bit line B / L signal to the second driving transistor T2. Turned on by the gate of the second pull-up transistor T4 and the first access transistor T5 applied to the common node of the first driving transistor T1 and the first pull-up transistor T3 and the word line W / L. Inverted bitline ( ) The second access transistor T6 applying a signal to a gate of the first driving transistor T1 and the first pull-up transistor T3 and a common node of the second driving transistor T2 and the second pull-up transistor T4. It consists of.

The SRAM configured as described above turns on the driving transistors T1 and T2 that are complementarily connected to the respective access transistors when the access transistors T5 and T6 are turned on by a word line (W / L) signal. B / L, Data is applied to the common node of the drive and pull-up transistors connected to the source of the access transistor in the form of charge, and turns on the other complementary drive transistors to apply charge to the pull-up transistor connected to the transistor and store the same. do.

FIG. 1B is a vertical cross-sectional view between the bit line and the access transistor in the memory cell of region A shown in FIG. 1A. Referring to this, the access transistors T5 and T6 have the same semiconductor substrate 10 as the conventional transistor structure. And a source / drain 14a or 14b formed in the substrate 10 near the edge of the gate electrode 12 and the gate electrode 12 formed in the above insulating thin film, and driving pull-up and pull-up to the source 14a. The common node Nd of the transistor is connected, while the bit line B / L to inverting bit line ( ) At this time, since the access transistor uses an n-type MOS transistor, the transistor is formed in the p-substrate and the source / drain 14a, 14b is implanted with n + dopant.

In the case of the conventional SRAM having the above structure, the current transfer capability of the access transistor connected to the bit line plays an important role in order to achieve the effect of low voltage and high speed operation of the recently emerging memory.

Therefore, when the SRAM reduces the cell size of the access transistor to achieve low voltage operation, the read current is reduced and there is a limit to achieving high speed operation. There is a need to improve the memory cell structure so that the amount of current can be applied.

An object of the present invention is to form a diode of the pnpn structure between the access transistor and the bit line in order to solve the problems of the prior art as described above, a large current flows when the external power is supplied above a certain voltage, the current transfer capability of the access transistor To provide a memory cell structure and a method of forming the SRAM device having a pnpn diode to improve the.

1A to 1B are circuit diagrams showing a memory cell structure of a conventional SRAM device, respectively.

2A and 2B are circuit diagrams showing a memory cell structure of an SRAM device according to the present invention, respectively, and a vertical cross-sectional view showing a pnpn diode between a bit line and an access transistor in a memory cell;

3 is a waveform diagram showing the electrical characteristics of a conventional pnpn diode

4A-4C are manufacturing process diagrams for forming a pnpn diode of an SRAM device in accordance with the present invention.

Explanation of symbols on the main parts of the drawings

T1: first drive transistor T2: second drive transistor

T3: first pull-up transistor T4: second pull-up transistor

T5: first access transistor T6: second access transistor

105: pnpn diode

To achieve the above object, the present invention provides a first and second pull-up transistors connected in parallel to a power supply terminal, first and second drive transistors respectively connected to a ground terminal and an output terminal of the pull-up transistor, and in response to a word line. A first access transistor for applying a signal of a bit line to a gate of the first pull-up and first driving transistor and a common node of the second pull-up and second driving transistor, and a signal of an inverting bit line in response to a word line; An SRAM device having a basic memory cell structure having a gate of a second pull-up and a second drive transistor and a second access transistor applied to a common node of the first pull-up and the first drive transistor, wherein the bit line and the first access transistor are used. And pnpn diodes respectively between and between the inverting bit line and the second access transistor. It shall be.

In order to achieve the above object, a method of manufacturing a pnpn diode according to the present invention includes forming a source / drain junction layer in which a gate electrode and an n + dopant are injected into a semiconductor substrate, and performing a photo process using a pnpn diode mask. Forming a drain junction layer corresponding to the line and inverting bit line directions and a photoresist pattern for selectively opening a substrate adjacent thereto; and injecting a p + dopant into the drain junction layer and the substrate opened by the photoresist pattern to drain direction And forming a bonding layer of pnpn in the gate electrode edge lower substrate of the substrate, and removing the photoresist pattern.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same parts as in the drawings for describing the related art.

2A and 2B are circuit diagrams showing a memory cell structure of an SRAM device according to the present invention, respectively, and a vertical cross-sectional view showing a pnpn diode between a bit line and an access transistor in a memory cell, wherein the unit cell of the memory has a ground voltage (Vss). First and second driving transistors T1 and T2 connected in parallel to a terminal, the transistors T1 and T2, respectively, and first and second pull-up transistors T3 and T4 connected to a power supply voltage terminal, Bit line (B / L) and inverting bit line ( Pnpn diode 106 composed of two bipolar transistors BTr1 and BTr2 (BTr3 and BTr4) connected to each other, and a bit line turned on by a word line W / L and applied through the diode 104b. And a B / L signal to a gate of the second driving transistor T2 and the second pull-up transistor T4, and to a common node Nd of the first driving transistor T1 and the first pull-up transistor T3. Inverted bit line (turned on by one access transistor T5 and word line W / L and applied through diode 104b) ) A second access transistor which transmits a signal to a gate of the first driving transistor T1 and the first pull-up transistor T3 and to a common node Nd of the second driving transistor T2 and the second pull-up transistor T4. It consists of (T6).

FIG. 2A is a vertical cross-sectional view illustrating a pnpn diode between a bit line and an access transistor in a memory cell of region B shown in FIG. 1A. Referring to this, the access transistors T5 and T6 have the same semiconductor structure as the conventional transistor structure. A gate electrode 102 formed on an insulating thin film on the substrate 100 and connected to a word line W / L and a source 104a and a drain formed in the substrate 10 near an edge of the gate electrode 102. The pnpn diode 106 is comprised. At this time, the source 104a is connected to the common node Nd of the driving transistor and the pull-up transistor, while the pnpn diode 106 is formed of the bit line B / L to the inverting bit line ( ) Again, since the access transistor uses an n-type MOS transistor, this transistor is formed in the p-substrate, and the diode 106 is composed of a region in which p + / n + / p + / n + dopants are implanted in the substrate 100 in series.

3 is a waveform diagram illustrating electrical characteristics of a conventional pnpn diode, and the diode is driven in the same manner as a diode having a general pnpn structure. When the voltage is higher than a predetermined voltage Vp, the current is greatly increased, where Vp is an impurity of the pnpn diode. Determined by concentration and depletion of deficient areas.

As described above, the SRAM according to the present invention has a low voltage of less than Vp. ), It belongs to the blocking region of the pnpn diode 106 so that almost no current flows to the access transistors T5 and T6.

However, when a voltage of Vp or higher is applied, the pnpn diode 106 is operated in the forward direction, amplified by the structures of the access transistors T5 and T6 so that a large amount of current flows to the node Nd.

4A to 4C are manufacturing process diagrams for forming a pnpn diode of an SRAM device according to the present invention, wherein the pnpn diode is formed by the following process sequence.

First, as shown in FIG. 4A, a gate electrode 102 constituting an SRAM is formed on a p− semiconductor substrate 100 through a conventional manufacturing process, and an ion implantation process is performed to inject an n + dopant into a source / Drain junction layers 104a and 104b are formed.

Next, as shown in FIG. 4B, a photoresist pattern using a pnpn diode mask is performed to selectively open the drain junction layer corresponding to the bit line and inverted bit line directions and a substrate adjacent thereto on the resultant. ). Then, a p + impurity ion implantation process is performed to inject a p + dopant into the drain junction layer 104b opened by the photoresist pattern 105 and the substrate to form a junction of pnpn in the lower substrate of the edge of the gate electrode 102 in the drain direction. Form layer 106.

As shown in FIG. 4C, the photoresist pattern 105 is removed, and although not shown in the drawing, a wiring process is performed to the gate electrode 102, the source / drain junction layer 104a, and the pnpn diode 106. To form a wire to be connected.

Therefore, as described above, in the present invention, when a voltage of a predetermined level or more is applied by connecting a pnpn diode between a bit line and an access transistor of the SRAM, the diode of the pnpn structure is operated in the forward direction to apply a large amount of current to the low voltage of the SRAM. , Implements high speed operation.

In addition, since the pnpn diode manufacturing process of the present invention is performed in a memory process using a general CMOS process, the manufacturing process can be simplified.

Claims (2)

First and second pull-up transistors connected in parallel to a power supply terminal, first and second drive transistors respectively connected to a ground terminal and an output terminal of the pull-up transistor, and a bit line signal in response to a word line; And a first access transistor applied to a gate of the first driving transistor, a common node of the second pull-up and the second driving transistor, and a signal of an inverting bit line in response to a word line. An SRAM device having a basic memory cell structure having a gate and a second access transistor applied to a common node of the first pull-up and the first driving transistor. And a pnpn diode between the bit line and the first access transistor and between the inverted bit line and the second access transistor, respectively. The method of claim 1, wherein the manufacturing method of the pnpn diode is Forming a source / drain junction layer in which the gate electrode of the SRAM and the n + dopant are implanted in the semiconductor substrate; Performing a photolithography process using the pnpn diode mask to form a photoresist pattern for selectively opening a drain junction layer corresponding to a bit line and an inverted bit line direction and a substrate adjacent thereto; Implanting a p + dopant into the substrate and the drain junction layer opened by the photoresist pattern to form a junction layer of pnpn in the substrate under the gate electrode edge in the drain direction; And Removing the photoresist pattern; and forming a pnpn diode in a memory cell of an SRAM device.