JPS5922359A - Integrated semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve holding characteristics by separately forming second conduction type wells to a first conduction type semiconductor substrate and the surface layer section of the substrate, forming a memory cell matrix to the surface in one well and a memory cell drive circuit to the inside and surface of the other well and each providing terminals for biassing the matrix and the circuit at different voltage. CONSTITUTION:One word line selected by an X decoder 5 activates a memory cell 4, memory informations are read to a z line and selected to a Y decoder 6, and informations are read by an input/output control circuit 7. When informations are stored previously in the drain 10 of an MOSFET constituting the memory cell, junction capacitance between the drain 10 and the well 2 increases because a low dope extension is biassed at 0V, and recombination currents also decrease, thus increasing the holding time of the memory cell. On the other hand, a small number of carriers are not implanted to the second well 3 even when negative surge voltage is applied to an input terminal from an external circuit because the well 3 is biassed at load voltage in MOSFETs 12-14 constituting the memory cell drive circuit.

Description

[Detailed description of the invention] The present invention relates to an integrated semiconductor memory device.

Conventionally, among integrated semiconductor memory devices configured using MOSFETs, in memories configured only with n-channel MOS and FETs, the MOS constituting the memory cell
M of the FET substrate and the peripheral circuit that drives the memory cell.
The same bias voltage was applied to the semiconductor substrate of the OSFET. For example, currently large-capacity dynamic R
In a one-transistor type dynamic RAM using an n-channel MO8FET, which is the mainstream of AM, the substrate is biased to a negative voltage. This is because by increasing the width of the depletion layer formed between the diffusion layer that stores information and the substrate, the junction capacitance between the diffusion layer and the substrate can be reduced and high-speed operation can be achieved. , the MOSFET threshold voltage does not vary greatly depending on the substrate voltage.
This is to ensure stable operation of the SFET.

On the other hand, recently, in large-capacity dynamic RAMs using a single 5V power supply, a method has been used in which the substrate voltage is maintained at 0. The advantages of this method are that a bias voltage generation circuit is not required, and that the width of the depletion layer between the diffusion layer and the substrate is narrowed, increasing the storage capacity. There are advantages such as a reduction in coupling current and a longer storage charge retention time. However, the disadvantage of this method is that since the substrate voltage is the ground voltage, when a surge voltage (negative voltage) is applied to the input terminal, a forward bias is created between the diffusion layer of the input terminal and the substrate. This is the point at which minority carriers (electrons) are injected into the substrate and the stored charge in the memory cell is destroyed. However, the above drawback is that in large-scale integrated circuit memory (hereinafter referred to as LSI memory), the substrate voltage of MOSFET in the memory cell area is reduced to 0.
(2) It can be removed by insulating the substrate voltage of the MOSFET in the peripheral circuit to a negative voltage.

Recently, a highly integrated and high-density LSI memory using a ternary level clock has been proposed, unlike the conventional memory cell which has a binary voltage level. That-
For example, the 1978 IEEE International Solid State Circuits Conference held in February 1978
B) LNATIONAL SOLII)-8TATE
CIRCUITS C0N-Le Papers (ISS
CCDIGEST 0FTECHNICAL PAPB
R8) pages 24-25 (distributed at the same time as the February 1978 conference)
There is a paper by Mr. Erb (D, M:, Erb) entitled "Fied Charge Me-mory") J. The memory cell described in this paper has a charge storage region and a current readout region integrated vertically. The memory cell has a small area and is suitable for large-capacity LSI memory.The memory cell operates using a p-channel MOSFE during write operation.
By making T conductive, either binary information is written depending on whether the charge is injected from the substrate (OV voltage) or swept to the substrate. During read operation, % n-channel MOS-
Current reading is performed using FET i. In this case, 2
Since the read current changes depending on the amount of stored charge of the value,
By detecting the difference between these two current values, the binary storage information is discriminated. However, to drive this cell, a p-channel MO8-FET and an n-channel MO8F are used.
In order to drive the MOSFET with the opposite polarity to the ET, the reference voltage is a voltage (positive voltage) higher than the threshold voltage of the n-channel MO8FET.

A clock is required that sets a voltage (negative voltage) below the threshold voltage of the p-channel MO8FET to a three-value level.

Therefore, in order to make the MO8'FET of the peripheral circuit that generates these clocks with an n-channel MOSFET, it is necessary to bias the substrate voltage to a voltage lower than the negative voltage of the ternary level clock. In an LSI memory using this memory cell, the substrate voltage in the memory cell area is set to O■.

It is necessary to bias the substrate voltage of the MOSFET in the peripheral circuit to a negative voltage. When the memory cell is biased to a negative voltage, the junction capacitance between the diffusion layer and the substrate is small;
This has the drawback that the recombination current, which is the basis of leakage current, also increases, and the retention time of the memory cell becomes shorter. Furthermore, in a one-try DEG transistor type dynamic RAM using an n-channel MO8FET, the diffusion layer for storing information is not surrounded by a well at all, so there is a drawback that it is vulnerable to information destruction due to the incidence of α particles. Even in the layered charge memory proposed by Mr. Arp, since either the p-channel or n-channel MOSFET is not surrounded by a well, there is a drawback that it is vulnerable to information destruction by α particles.

The present invention provides an integrated semiconductor memory device that eliminates the above-mentioned drawbacks, has good retention characteristics, has strong resistance to information destruction due to the incidence of α particles, and is suitable for large-capacity and high-integration. .

An integrated semiconductor memory device of the present invention includes a semiconductor substrate of a first conductivity type, first and second wells of a second conductivity type separately provided in a surface layer portion of the semiconductor substrate, and A memory cell matrix formed on the surface in the first well, a memory cell drive circuit formed in the well and on the surface of the fs2, and a memory cell drive circuit provided in the first and second wells, respectively, and each connected to a different voltage. and a terminal for biasing.

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 shows the first and second wells shown in FIG. 1 and the Mo8 wells formed therein.
FIG. 3 is a cross-sectional view showing an extracted FET.

In the following description, - conductivity type will be explained as p type.

- When the conductivity type is n-type, the sign may be reversed.

As shown in FIG. 1, a p-type semiconductor substrate 1 is provided with an n-type first well 2 and a second well 3. As shown in FIG.

In the first well 2, a memory cell matrix 4 is formed in which memory cells are arranged in a lix shape. X decoder 5 in second well 3. Memory cell drive circuits such as an X decoder 6 and an input/output control circuit 7 are formed. The input/output control circuit includes an address inverter circuit, an input/output data buffer circuit, and a control clock generation circuit.

As shown in FIG. 2, the first well 2. 2nd well 3
A gate insulating film 8 is provided on each side, and p-type source and drain regions 9°, 10, 12, and 13 are provided on both sides of the gate insulating film 8, respectively. Gate electrodes 11 and 14 are respectively provided on the gate insulating film 8 to form a Mo8-FET. Although only one Mo8FET is shown in each well in Figure 2,
This is typical.

In reality, a large number of them are formed.

First well 2. Bias terminals 15 and 16 are provided in each of the second wells 3. Terminals 15 and 16 are respectively connected to the first . It is connected to a power source that biases the second wells 2 and 3. One of the features of the present invention is that the first well 2 and the second well 3 are provided, and the structure is such that they can be connected to bias sources with different voltages. By adopting this structure, the drawbacks of the prior art are eliminated. The bias voltage can be determined arbitrarily.

For example, when operating with a single 5V power supply, the board 1 is
Connect the terminal 15 to the ground voltage source and the terminal 16 to the negative voltage source. A commonly used substrate bias generation circuit can be used as the bias power supply, and this circuit can also be incorporated into the same substrate. These things are optional. In the following explanation, the substrate voltage is 5V, the first well 2 is set to the ground voltage, and the second well is set to the negative voltage (-2 to -
3V).

The operating method of the integrated semiconductor memory device according to the present invention is exactly the same as that of the conventional one. Tsuma υ, X decoder 5
One word line selected by activates the memory cell 4 coupled to the word line, and further, memory information is read to the bit line coupled to the memory cell. This bit line is selected by the X decoder 6, and the input/output control circuit 7 reads out information as an output signal to the outside.

Source 9° and drain 10 of the Mo8FET that constitutes the memory cell. Assuming that information is stored in the drain 10 of the gate 11, the first well 2, which is the substrate of this Mo8-FET, is connected to Ov (earthed, so it becomes a negative voltage) (earthed). Drain 1 compared to case
The retention time of the memory cell increases because the junction capacitance between well 2 and well 2 increases, and the recombination current that causes leakage current also decreases. On the other hand, the Mo8FETs 12, 13, and 14 constituting the memory cell drive circuit have the second well 3, which is the substrate, set to a negative voltage.
Even if a negative surge voltage is applied to the input terminal from an external circuit, minority carriers will not be injected into the well 3. Moreover, Mo 8 in the memory cell drive circuit
By shortening the channel of the FE, minority carriers in the well 3 generated by ion collision etc. are absorbed into the substrate 1 and do not destroy the memory cell. Therefore, the retention characteristics of the memory cell will not deteriorate due to minority carriers generated in the memory cell drive circuit as seen in the conventional one-transistor type MO8RAM.
The retention characteristics of the memory cells of the semiconductor memory device of this embodiment are significantly longer.

Furthermore, in the memory cell of this device, since the diffusion layer 10 for storing information is surrounded by the well 2, there is an advantage that information destruction by α particles is less likely to occur. Tsum-shi, α
Among the charges generated by particles, the charges that contribute to information destruction are only those generated in the diffusion layer 1° and the well 2, so if the depth of the well 2 is made shallow, α
The amount of charge flowing in due to particles is reduced, and information destruction becomes less likely to occur.

The integrated semiconductor memory device of the present invention can also be applied to a MO8RAM constituted by memory cells using a ternary level clock in the same manner as described above. In this case as well, the memory cell and the memory cell drive circuit have the structure shown in FIGS. 1 and 2 of the above-described embodiment.
The well 2 is biased to 0■, and the second well 3 in which the memory cell drive circuits 5, 6.7 are formed is biased to -2 to -3■.

In the case of a 5V single power supply, as a three-level level clock,
For example, t, +3V, ov, -1,5V (7) and 0 are generated in the input/output control circuit 7 to drive the memory cell 4. Also in such MO8RAM, since the memory cell and the memory cell drive circuit are formed in separate wells, the minority carriers generated in the memory cell drive circuit will not destroy the memory cell. Further, as mentioned above, since the memory cell is surrounded by a well, resistance to α particles is enhanced.

As explained in detail above, the present invention is applicable not only to the conventional one-transistor type dynamic RAM but also to a large-capacity, highly integrated LRAM using a high-density memory cell using a ternary level clock.
It can also be applied to SI memory, and as a result, it is resistant to external noise.
Moreover, it has the effect that the retention characteristic becomes longer and furthermore, it is possible to obtain an integrated semiconductor memory device that is resistant to α particles.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 shows the first and second wells shown in FIG. 1 and the MOS formed therein.
FIG. 3 is a cross-sectional view showing an extracted FET. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First well, 3... Second well, 4... Memory cell matrix, 5...・・X decoder, 6・
...X decoder, 7... Input/output control circuit, 8... Gate insulating film, 9...-': Source, 10... Drain, 11...Gate, 12...Source, 13...Drain, 14...River/Kate, 15.16...Terminal.

Claims (1)

[Claims] A semiconductor substrate of a first conductivity type, first and second wells of a second conductivity type provided separately on the surface layer of the semiconductor substrate, and a memory formed on the surface inside the first well. A cell matrix, a memory cell drive circuit formed on the surface of the second well, and terminals provided in each of the first and second wells and biased to different voltages. An integrated semiconductor memory device.