JPS60246671A - Semiconductor memory cell - Google Patents
Semiconductor memory cellInfo
- Publication number
- JPS60246671A JPS60246671A JP59102882A JP10288284A JPS60246671A JP S60246671 A JPS60246671 A JP S60246671A JP 59102882 A JP59102882 A JP 59102882A JP 10288284 A JP10288284 A JP 10288284A JP S60246671 A JPS60246671 A JP S60246671A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- type
- film
- fet
- word line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は小型化してもアルファ粒子γjどの放射性粒子
によって引き起されるソフトエラーの発生が少ない半導
体メモリセルに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory cell in which soft errors caused by radioactive particles such as alpha particles γj are less likely to occur even when miniaturized.
(従来技術とその問題点)
アルファ粒子などの放射性粒子が半導体内に入射すると
、半導体内部1こは多米の電荷が生成される。これらの
電荷が半導体メモリセル内部の電極船こ流入すると、そ
の電極の電位を変化させ、その結果ソフトエラーを起す
。半導体メモリセル内の電極が取り扱う電荷量が大きい
時(J、このような内部生成電荷の流入の影善は小さく
、このメモリセルがソフトエラーを起すことは少1jい
、しかし、半導体メモリセルが小型化されると、メモリ
セル内電極の取り扱う電荷量が減少T6ため、ソフトエ
ラーの問題が小太となる。(Prior art and its problems) When radioactive particles such as alpha particles enter a semiconductor, a large amount of electric charge is generated inside the semiconductor. When these charges flow into the electrodes inside the semiconductor memory cell, they change the potential of the electrodes, resulting in soft errors. When the amount of charge handled by the electrodes in a semiconductor memory cell is large (J), the effect of such an influx of internally generated charges is small, and this memory cell is unlikely to cause soft errors. When miniaturized, the amount of charge handled by the electrodes in the memory cell decreases T6, which makes the problem of soft errors a little greater.
従来の半導体メモリセルでは、メモリセル内を極の構造
を改良し、放射性粒子によって生成される電荷のこの電
極への流入を少なくすること、この電極の取り扱う電荷
iを流入雷、荷取以上に保っこdlこよってソフトコラ
−を防いでいた。しかし、メモリセル内′を極へ流入す
る電荷量ヲ減らすことlこは限界があるため、その電極
で取り扱う電荷量をある値以上lこ保たなければならな
い。そのため、従来の半導体メモリセルではその大きさ
も、その消費電力もある値以上lこ保たなければならな
かった。このことは、この半導体メモリセルの小型化お
よびこの半導体メモリセルを使ったメモl装置の集積化
にとって大きな嘩護となっていた。In conventional semiconductor memory cells, the structure of the poles inside the memory cell is improved to reduce the inflow of charges generated by radioactive particles into these electrodes, and to reduce the charge i handled by these electrodes by more than the inflow lightning and cargo. I was preventing soft collage by using DL. However, since there is a limit to reducing the amount of charge flowing into the electrode in the memory cell, the amount of charge handled by the electrode must be kept above a certain value. Therefore, in the conventional semiconductor memory cell, both its size and its power consumption had to be kept above a certain value. This has been a major obstacle to the miniaturization of semiconductor memory cells and the integration of memory devices using these semiconductor memory cells.
(発明の目的)
本発明の目的はアルファ粒子などの放射性粒子lこよっ
て引き起されるソフトエラーの発生が極めて少なく、ソ
フトエラ一対策のためlこ小型化、集積化が制トυされ
ることの少ない半導体メモリセルを提供することである
。(Objective of the Invention) The object of the present invention is to minimize the occurrence of soft errors caused by radioactive particles such as alpha particles, and to suppress miniaturization and integration in order to prevent soft errors. An object of the present invention is to provide a semiconductor memory cell with a small number of semiconductor memory cells.
(発明の栖取)
本発明憂こよる半導体メモリセルは、第1のワード線に
接続されたゲート電極、第1のビット線に接続された第
1通電電極、第2通電電極、を有する第1導電型の第1
FB’l”、:、第2のワード線に接続さtまたゲート
電極、第2のヒツト酬1こ接続された第1通電電極、第
2連亀、電極、を弔する第2導電型の第21!” E
’1’と、前記第1 PETの第2通電電極と前記第2
FETの第2ii1’lI電極との間1こ接続された容
量と、を含む半導体メモリセルlこ於て、第1 FET
は半導体結晶基板lこ形H,され、第2 F B ’I
’は前記半2に体結晶基板上Cc形敢された半導体膜ζ
こ形成されることを特徴とする。(Summary of the Invention) A semiconductor memory cell according to the present invention has a gate electrode connected to a first word line, a first current-carrying electrode connected to a first bit line, and a second current-carrying electrode. 1 conductivity type 1st
FB'l'': a gate electrode connected to a second word line; a first current-carrying electrode connected to a second word line; 21st!”E
'1', the second current-carrying electrode of the first PET and the second
A semiconductor memory cell including a capacitor connected between the second ii1'lI electrode of the FET, and the first FET.
is a semiconductor crystal substrate L-shaped H, and the second F B 'I
' is a semiconductor film ζ shaped like Cc on the crystal substrate in the above-mentioned half 2
It is characterized by the formation of
(実施例:構成)
次憂こ本発明の実施例を用いて、本発明の半導体メモリ
セルの動作原理および効果を説明する。第1図は本発明
の半導体メモリセルの一実施例の構造を示したものであ
り、本図(a)i1平面図、(b) 、 (C)はそイ
1ぞれ(a)のBB’およびCO2で切り開いた場合の
断面図を示す。同図101に第1のワード線とN型チャ
ネル第1M08FETのゲート電極を兼ねる導電体膜、
102は第1 M OS F Ei’の通電電極となる
N型頭域、103は第1M08FETの通電電極と容量
(以後セル容量と呼ぶ)の一方の電極を兼ねるN型領域
、104は第2のワード線とP型チャネル第2M08F
ETのゲートを極を兼ねる導電体膜、105は第2M0
8FETの通電電極となるP型領域、106)ば第2
M O8F ETの通電電極とセリ容量の一方の′tf
L極F!−兼ねるP型領域、107はセル容量を形成す
る絶縁体膜、108は第1のビット線(!:なる導電体
膜、]09は第2のビット線となる導電体膜、110は
P型シリコン結晶基板、111はN型領域、112はN
型チャネル第IMO8PETのゲート絶縁体膜、113
il P型チャネル第2M08F’BTのゲート絶縁
体膜、114 、115は1間絶縁体膜、116は10
2と108間を接続する為のコンタクト孔、117は1
05と109間を接続するコンタクト孔、をそれぞれ示
す。(Example: Configuration) Next, the operating principle and effects of the semiconductor memory cell of the present invention will be explained using an example of the present invention. FIG. 1 shows the structure of an embodiment of a semiconductor memory cell according to the present invention, and FIG. ' and shows a cross-sectional view when cut with CO2. 101 in the same figure shows a conductive film that also serves as a first word line and a gate electrode of the first N-type channel M08FET;
Reference numeral 102 denotes an N-type head region that serves as the current-carrying electrode of the first MOS F Ei', 103 an N-type region that serves as the current-carrying electrode of the first M08FET and one electrode of the capacitor (hereinafter referred to as cell capacitance), and 104 the second Word line and P type channel 2nd M08F
105 is the second M0, which is a conductive film that also serves as the gate of ET and a pole.
8 P-type region which becomes the current-carrying electrode of FET, 106)
'tf of one of the current-carrying electrode and the soldering capacitance of M
L pole F! 107 is an insulating film that forms a cell capacitor; 108 is a conductive film that serves as the first bit line (!: conductive film; ]09 is a conductive film that serves as a second bit line; 110 is a P-type region) Silicon crystal substrate, 111 is an N type region, 112 is an N
Type channel No. IMO8PET gate insulator film, 113
il P-type channel 2nd M08F'BT gate insulator film, 114 and 115 are 1 insulator films, 116 is 10
Contact hole for connecting between 2 and 108, 117 is 1
Contact holes connecting between 05 and 109 are shown, respectively.
第1図に示されるように、N型チャネル第1M08FE
Tは、P型シリコン結晶基板110 V基板領域、該P
型シリコン結晶基板110 iこ拡散やイオン注入など
−こよって形成された2つのN型頒域102 、103
を通電tfM、として構成される。−万、P型チャネル
第2M(J8FETは、/シコン1fdlこ形成さむた
N型領域]11を基板領域、P型領域105 、106
を通I!電極として構成される。以後、第1図の実施例
を用いた本発明の説明では、このシリ:I 7Pja1
05 、106 、111をレーサーアニール等の方法
によって再結晶化された多結晶シリコン膜と想定する。As shown in FIG. 1, N-type channel 1M08FE
T is the P-type silicon crystal substrate 110 V substrate region;
type silicon crystal substrate 110. Two N type regions 102, 103 are formed by diffusion, ion implantation, etc.
is configured as energized tfM. - 10,000, P-type channel 2M (J8FET is /Silicon 1fdl) N-type region] 11 is the substrate region, P-type region 105, 106
Through I! Configured as an electrode. Hereinafter, in the description of the present invention using the embodiment shown in FIG. 1, this series: I 7Pja1
It is assumed that 05, 106, and 111 are polycrystalline silicon films recrystallized by a method such as laser annealing.
もちろん、第2 M OS F E ’1’が以下で記
す性質を満足すれは、ct’t、■他のノリコン膜例え
ば水素プラズマアニールしたポリンリコンp或いは/リ
フン以外の半導体膜であっても構わない。Of course, as long as the second MOS F E '1' satisfies the properties described below, it may be a semiconductor film other than ct't, or other Noricon films, such as hydrogen plasma annealed Polyrecon p or / Rifun. .
(実施例、動作原fM>
第2図は第1図の実施例の等価[c!I略である。この
図を用いて本発明の半導体メモリセルの動作原理を説明
する。201はノリコン結晶基板齋こ形成されたN型チ
ャネルM OS P E T、202は再結晶化多結晶
ソリコン膜に形成されたP型チャネルMO8FET、2
03 G’!セル答量を示しておりその漬汁]Sとする
う、204 、205はそれぞれ第1.M2のワード線
、206 、207はそれぞれ第1.第2のビット線、
208と209は本案施例のメモリセルを用いた半導体
装#lこおいて使用される電源のうち低い電位(値をO
V亡する)を与えを電源線と高い電位(債をVDD亡す
る)を与える電源線、21O1211はそれぞれ節点N
l 、N2に寄生する容量(値を01,02とする)を
示す。(Example, operation principle fM> FIG. 2 is equivalent to the embodiment shown in FIG. 1 [c!I omitted. The operation principle of the semiconductor memory cell of the present invention will be explained using this diagram. 201 is a Noricon crystal. The N-type channel MOSFET 202 formed on the substrate is a P-type channel MO8FET formed on the recrystallized polycrystalline silicon film.
03 G'! 204 and 205 indicate the amount of pickled juice] S, 204 and 205 respectively. The word lines 206 and 207 of M2 are the first . a second bit line,
208 and 209 are lower potentials (values are O
21O1211 is the node N, respectively.
l indicates the parasitic capacitance of N2 (values are 01 and 02).
第2図のメモリセルは、第1のワード線204を高電位
に、第2のワード線205を低電位にし、両刀のMO8
FET2(11、202をオン状態をこすることにより
選択され、ビット線からのデータの書き込み読み出しが
可能になる。また第1のワード線204を低電位に、第
2のワード線205を尚電位にし、両方のM(J8FE
T201.202をオフ状態にするCと憂こより、本メ
モリセルは保持状態となる。The memory cell in FIG. 2 has a first word line 204 at a high potential, a second word line 205 at a low potential, and a double-edged MO8.
It is selected by turning on FET2 (11, 202), and it becomes possible to write and read data from the bit line.Also, the first word line 204 is set to a low potential, and the second word line 205 is set to a low potential. and both M (J8FE
By turning off T201 and T202, this memory cell enters the holding state.
以後、保持時−こ節点N1の電位か節点N2の電位より
も高い状態を”ド情報の保持状態と、節点N 1 (0
111:位が節点N2の電位よりも低い状態を”0°情
報の保持状態と、対応させることとする。Hereafter, when holding - the state where the potential of node N1 is higher than the potential of node N2 will be referred to as the "holding state of information" and the state of node N1 (0
111: The state where the potential is lower than the potential of the node N2 is made to correspond to the "0° information retention state."
また前記高い電源電位VDD、と低い電源電位(JV。Furthermore, the high power supply potential VDD and the low power supply potential (JV).
低電位が、それぞれ次実施例のメモリセルを用い・た半
導体装置において使用される最高電源電位とi&低電源
電位に等しい場合を想定する。It is assumed that the low potential is equal to the highest power supply potential and i&low power supply potential used in a semiconductor device using the memory cell of the next embodiment.
半導体Z+Cアルファ粒子粒子数射性粒子が入射すると
、半導体内に(ば多数の電荷が生成されると、および前
記生by、電荷が半導体内の電極に流入すると、該電極
の電位は該ML極とその周囲の半導体との間の電位差を
減らす方向に変化すること、は良く知られている。When a semiconductor Z+C alpha particle particle is incident, a large number of charges are generated within the semiconductor, and when the charge flows into an electrode within the semiconductor, the potential of the electrode changes to the ML pole. It is well known that changes occur in the direction of reducing the potential difference between the semiconductor and the surrounding semiconductor.
“1”情報保持状態の本半導体メモリセルの節点N1を
こアルファ粒子等の入射の影ゆがあった場合を考える。Let us consider a case where the node N1 of the present semiconductor memory cell in the "1" information retention state is affected by the incidence of alpha particles or the like.
アルファ粒子等が入射する直前の節点Nl 、N2の電
位(1簡単のためそれぞれVl)D。Potentials of nodes Nl and N2 immediately before alpha particles etc. are incident (1, each Vl for simplicity)D.
V D D /2であったと仮定する。奇生容量に1
。Assume that V D D /2. 1 for paranormal capacity
.
C2が小さく、
(CI+02)・Vl)D/2
で与えられる電荷量が節点N1+こ影響を及ぼすアルフ
ァ粒子等によって生成された電荷量よりも小さい場合、
節点Nl(第1図のN型領域103iご対応)の電位は
VDDからその周囲半導体の電位0■付近まで低下する
。このとき節点N2の電位はセル容11203の容量カ
ップリンクlこまってで表わさ右る値伺亡談でへ下’v
る。この(+Nは、本実施例のメモリセルを用いた半導
体装Pfjこおいて使われる最低の電源電位Ov以下で
あるが、節点N2(第1図の1061こ対応)は孤立し
たP型領域であるため、該P型領域と周囲領域との間の
PN接合逆バイアスを大きくするたけで、問題そ生じな
い。When C2 is small and the amount of charge given by (CI+02)・Vl)D/2 is smaller than the amount of charge generated by alpha particles etc. that affect node N1+,
The potential of the node Nl (corresponding to the N-type region 103i in FIG. 1) decreases from VDD to the potential of the surrounding semiconductor near 0■. At this time, the potential at the node N2 is expressed by the capacitance cup link l of the cell capacitor 11203.
Ru. Although this +N is less than the lowest power supply potential Ov used in the semiconductor device Pfj using the memory cell of this embodiment, the node N2 (corresponding to 1061 in FIG. 1) is an isolated P-type region. Therefore, no problem arises simply by increasing the PN junction reverse bias between the P-type region and the surrounding region.
アルファ粒子等によって半導体内1こ生bj、された電
荷(ま拡散にまって散逸する1こめ、そのiwi五、ア
ルファ粒子等の入射後ある時間か経つとほとんどすくす
ってしまう。例えばマイクロメータオーダの寸法で本実
施例のメモリセルかくり返し並べられた半導体装置では
、隣接するメモリセルのN領域(第1図の102に対応
)などに生成゛電荷が少しずつ吸収されたりして、約百
ナノ秒後にはその影響がほとんどすくする。Charges generated in a semiconductor by alpha particles, etc. (or charges that are dissipated due to diffusion, and after a certain period of time after the alpha particles, etc. are incident, almost all of them disappear.For example, on the order of micrometers) In the semiconductor device in which the memory cells of this embodiment are repeatedly arranged with dimensions of After a nanosecond, the effect is almost gone.
このよう−こアルファ粒子等の影響がほとんどなくMっ
た暗IC1Nす点N2の′I株位を、仮籾的に、再びO
V+こ戻すと節点N1の′「1℃位けはばls+c:1
) (C8+02 )
となる。このこと(Jアルファ粒子等の入射によって、
セル容量203に貯められてい1こ′−伺量或い(は電
位差が比にしてC8/(C8+01 )(O8+02)
に減ったことを意味す6゜この1[1J例えはCI=Q
2 = O8/1n亡すれはP、26Φξ1jる。In this way, the stock position of the dark IC1N point N2, which is almost unaffected by alpha particles, etc., is re-opened again.
When V+ is returned, node N1's deflection is approximately 1℃ ls+c:1
) (C8+02). This (due to the incidence of J alpha particles, etc.)
The amount of electricity stored in the cell capacitor 203 or the potential difference is C8/(C8+01)(O8+02)
6゜ This means that it has decreased to 1[1J For example, CI=Q
2 = O8/1n death is P, 26Φξ1j.
本実施例のメモリセルの断、み出し動作は、両MO8F
ET201.202をオン状態にし1ことき生じる第1
のビット線206と第2のど、ト@2o7間の電位差変
化を感知して、行なう。本メモリセルが”0”、1”情
報のうちどちらを保持してい1こかの判断は、例えは読
み出し前に節点Nlの電位が節点N2の電位よりも品い
か囚いかにまって生じろビット線市1位差の変化を感知
する、などの方法で行なう。そのため、上記のアルファ
粒子等の入射したメモリセルでは、節点N1と節点N2
の間の電位差が小さくなったものの、その高低関係Cま
変らないため、“1″情報が保持されていると判断され
る。すなわち保持されている“1”情報が破壊されずに
残ることになる。さらに上記の例では、節点Nl(!:
節点N2の間の電位差はアルファ粒子等が入射しなかっ
た場合の80%以上も残っているため、感知動作Iこ要
求される性能もそれほどきびしくない。0110S 0
210Sの比をもっa小さく1λるように本実施例のメ
モリセルを設計すれば、感知動作tこ要求される性能は
さらlこゆるくなる、
本実施例のメモリセルでは、P型チャネル第2M(JS
FETが再結晶化多結晶ソリコン膜fこ形成されている
。一般lここのようr、(MO8FBTf;!単結晶ノ
リコン基板上tこ形成されたMOSFETに比べてもれ
電流が大きい。本メモリセルが上記のアルファ粒子等1
こ耐える性質をもつためには、本メモリセルを構成する
MOSFETのもれ電流によってセル容量に貯められて
いた電荷が失われるのに必要な時間が、アルファ粒子等
によって生成された電荷が散逸しほとんど影響を及ぼさ
すくするまでの時間よりも、f分大きいことが必要であ
る。ところが、辿常のマイクロメークオーダの寸法をも
つ本実施例のメモリセルでは、上記のセル容量に貯y)
られていた電荷が失われるのlこ必要な時間はマイクロ
抄オーダ以上であり、問題ない。The disconnection and protrusion operation of the memory cell in this embodiment is performed on both MO8F.
The first one that occurs when ET201.202 is turned on.
This is done by sensing the potential difference change between the bit line 206 and the second line 2o7. The judgment as to whether this memory cell holds "0" or "1" information can be made, for example, by determining whether the potential at node Nl is higher than the potential at node N2 before reading the bit. This is done by a method such as sensing a change in the line-to-center difference.Therefore, in the memory cell where the alpha particles etc. have entered, the nodes N1 and N2 are
Although the potential difference between them has become smaller, the height relationship C remains unchanged, so it is determined that "1" information is held. In other words, the held "1" information remains without being destroyed. Furthermore, in the above example, the node Nl(!:
Since the potential difference between the nodes N2 remains more than 80% of the potential difference when alpha particles etc. were not incident, the performance required for the sensing operation is not so severe. 0110S 0
If the memory cell of this example is designed so that the ratio of (J.S.
The FET is formed using a recrystallized polycrystalline silicon film. In general, the leakage current is larger than that of a MOSFET formed on a single crystal Noricon substrate.
In order to withstand this, the time required for the charge stored in the cell capacitance to be lost due to the leakage current of the MOSFET that makes up this memory cell is the time required for the charge generated by alpha particles etc. to dissipate. It is necessary that the time is f minutes longer than the time it takes to have almost any influence. However, in the memory cell of this embodiment, which has the dimensions of a typical micro make order, the above cell capacity is
The time required for the charge to be lost is on the order of a micro-sheet or more, so there is no problem.
以上、本実施例のメモリセルの動作原理をル9明するの
に、本メモリセルが“ド情報保持状態のとき節点NUこ
アルファ粒子等の影響が生じた場合を例にdっ1こが、
これ(ゴ他の場合、”0”情報保持状態や節点N2にア
ルファ粒子等の影響が及んだときも同様である。ぎ0点
N2にアルファ粒子等の影響が及ぶ場合、節点N2は薄
いンリフン膜にあるため、ソリコン基板にある頁屹つ、
Nliこアルファ粒子寺の影響が及ぶ場合よりも、その
影・赫のllj度が小さい。In order to explain the operating principle of the memory cell of this embodiment, we will use the example of the case where the memory cell is in the "do information holding state and the influence of alpha particles etc. occurs at the node NU" as an example. ,
In the case of Go et al., the same is true when the "0" information is retained or when the influence of alpha particles etc. is exerted on the node N2.If the influence of alpha particles etc. is exerted on the 0 point N2, the node N2 is Because it is in the film, the pages on the solicon board,
The degree of its shadow/light is smaller than when it is affected by the alpha particle temple.
また以上の実施例dこおいてはnチャネルMUSFET
を基板上に、pチャネルM OS I” h2 Tを半
導体膜上に形成したが、この逆で5よいことはもちろん
である。またへ108に限らす一般のMISF E T
等を用いてもよい。In addition, in the above embodiment d, an n-channel MUSFET is used.
is formed on the substrate, and the p-channel MOS I''h2T is formed on the semiconductor film, but it goes without saying that the reverse may also be used.
etc. may also be used.
(発明の効果)
以上説明したようfこ本発明のメモリセルはアルファ粒
子等の放射性粒子が人身1しても、保もγしている情報
が破壊されない、
一般に、F、N両チャネルのMISFETを同一ソリコ
ン結晶基板上に形Jllkすると、両MISFET間の
絶縁のため、両MI 5FET間かくを大きくする必要
がある。そのため、P、N両チャンネルのM I S
ト’ E Tを集積したテバイスの寸法は大きくなる傾
向がある、ところが本発明のメモリセルでは一万のMI
5FETをソリコン結晶基板から絶縁され1こシリコ
ン膜土1こ形成されるため、P、NチャンネルのMIS
FETをいくらで5近づけることかでさ、高集積化にと
って極めて好ましい。(Effects of the Invention) As explained above, the memory cell of the present invention is generally a MISFET of both F and N channels, in which the stored information is not destroyed even if radioactive particles such as alpha particles are injected into the body. If these are mounted on the same soric crystal substrate, it is necessary to increase the distance between both MISFETs in order to insulate them. Therefore, the M I S of both P and N channels
The dimensions of devices with integrated memory cells tend to be large; however, the memory cell of the present invention
Since the 5FET is insulated from the silicon crystal substrate and one silicon film is formed, P and N channel MIS
The number of FETs close to 5 is extremely desirable for high integration.
第1図は本発明の半導体メモリセルの構造の一例を示す
図で、(a)は平面図、(bJ 、 (CJはそれぞれ
(a)のHB’ 、00’で切り開いた場合の#T面図
である。第2回目第1図の実施f11の等価1r31路
の図である。
+01・・・・・・導電体N1ξ 】02・・・・・・
N州領域、103 °゛・・・N型領域、 ]U4・・
・・・導電体腔、105・・・・・・P型領域、106
・・・・・P型舶域、]07・・・・絶縁体膜、108
・・・・・・$隼、体験、109・・・・・・導電体膜
、11O・・・PZtll/llコン結晶基板、1]1
・・・・・・N型領域(105、106、111iばシ
リコン膜tこ形成さねてい6)、
112・・・・N型チャネルlMOS F E Tのケ
ート絶縁体験、113・=−Pi(リナ−不ルMすSF
Ei’ (1)メr−1−絶縁体膜、201−= 1
01 、102.103 、112で構成すれ6N型チ
ヤネルへ4 (J 8 P E ’I’、202・・・
・・104 、105 、106 、 Illで構成さ
れるP型チャネルMO8FET。
203・・・・・103.106.107で構成される
セル容量、204・・・・・・101で構成される第1
のワード線、2tJ5・・・・・・104で構成される
第2のワード線、206・・・・・108で構成さイす
る第1のヒツト線、207・・・・・・109で構成さ
れる第2のヒツト線。
第1図
オ 2 図FIG. 1 is a diagram showing an example of the structure of a semiconductor memory cell of the present invention, where (a) is a plan view, (bJ and (CJ) are #T planes when cut at HB' and 00' in (a), respectively. It is a diagram of the equivalent 1r31 path of the second implementation f11 in Figure 1. +01...Conductor N1ξ ]02...
N-state region, 103°...N-type region, ]U4...
...Conductor cavity, 105...P-type region, 106
...P-type ship area,]07...Insulator film, 108
......$Hayabusa, experience, 109...conductor film, 11O...PZtll/ll crystal substrate, 1]1
......N-type region (105, 106, 111i, silicon film t is formed 6), 112...N-type channel IMOS FET insulation experience, 113 = -Pi ( Lina Furu MS SF
Ei' (1) Mer-1-insulator film, 201-=1
01, 102.103, 112 to 6N type channel 4 (J 8 P E 'I', 202...
... P-type channel MO8FET consisting of 104, 105, 106, Ill. The cell capacity consists of 203...103.106.107, and the first cell capacity consists of 204...101.
The second word line consists of 2tJ5...104, the first word line consists of 206...108, and the first word line consists of 207...109. The second hit line. Figure 1 O Figure 2
Claims (1)
ト線に接続された第1通電電極、第2通電電極、を有す
る第1導電型の第1 FETと、第2のワード線に接続
されたゲート電極、第2のビット線に接続された第1通
電電極、第2通電電極、を有する第2導電型の第2FE
Tと、前記第1FETの第2通電電極と前記第2FET
の第2通電電極との間に接続された容量と、を含む半導
体メモリセルに於て、第1FETは半導体結晶基板憂こ
形成され、第2FETは前記半導体結晶基板上に形成さ
れた半導体族に形成されることを特徴とする半導体メモ
リセル。A first FET of a first conductivity type having a gate electrode connected to the first word line ζ, a first conductive electrode connected to the first bit line, and a second conductive electrode connected to the second word line; a second FE of a second conductivity type having a connected gate electrode, a first current-carrying electrode connected to a second bit line, and a second current-carrying electrode;
T, a second current-carrying electrode of the first FET, and the second FET.
A first FET is formed on a semiconductor crystal substrate, and a second FET is formed on a semiconductor group formed on the semiconductor crystal substrate. A semiconductor memory cell characterized by being formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59102882A JPS60246671A (en) | 1984-05-22 | 1984-05-22 | Semiconductor memory cell |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59102882A JPS60246671A (en) | 1984-05-22 | 1984-05-22 | Semiconductor memory cell |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60246671A true JPS60246671A (en) | 1985-12-06 |
Family
ID=14339236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59102882A Pending JPS60246671A (en) | 1984-05-22 | 1984-05-22 | Semiconductor memory cell |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60246671A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4771323A (en) * | 1986-07-14 | 1988-09-13 | Oki Electric Industry Co., Ltd. | Semiconductor memory device |
JPH03259565A (en) * | 1989-06-30 | 1991-11-19 | Texas Instr Inc <Ti> | Transistor cell |
US5219779A (en) * | 1989-05-11 | 1993-06-15 | Sharp Kabushiki Kaisha | Memory cell for dynamic random access memory |
US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
US5299155A (en) * | 1991-03-01 | 1994-03-29 | Sharp Kabushiki Kaisha | Dynamic random access memory device with capacitor between vertically aligned FETs |
-
1984
- 1984-05-22 JP JP59102882A patent/JPS60246671A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4771323A (en) * | 1986-07-14 | 1988-09-13 | Oki Electric Industry Co., Ltd. | Semiconductor memory device |
US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
US5219779A (en) * | 1989-05-11 | 1993-06-15 | Sharp Kabushiki Kaisha | Memory cell for dynamic random access memory |
JPH03259565A (en) * | 1989-06-30 | 1991-11-19 | Texas Instr Inc <Ti> | Transistor cell |
US5299155A (en) * | 1991-03-01 | 1994-03-29 | Sharp Kabushiki Kaisha | Dynamic random access memory device with capacitor between vertically aligned FETs |
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