JPS60246671A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To reduce the limitation for the miniaturization and integration in a countermeasure against a soft-error caused by radioactive particles by forming a first FET to a semicondutor crystal substrate and a second FET to a semicoductor film shaped onto the substrate. CONSTITUTION:An N type channel first MOSFET201 is constituted while a P type silicon crystal substrate 110 is used as a subsrate region, a conductor film 101 as a first word line and a gate electrode and N type regions 102, 103 as conductive electrodes, and a P type channel second MOSFET202 is constituted while an N type region 111 formed to a silicon film is employed as a substrate region, a conductor film 104 as a socond word line and a gate electrode and P type regions as conductive electrodes. Conductor films 108, 109 function as first and second bit lines 206, 207. An insulator film 107 shapes a cell capacitance 203. The P, N channel MISFETs can be brought near to any extent, and the degree of integration can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory cell in which soft errors caused by radioactive particles such as alpha particles γj are less likely to occur even when miniaturized.

(Prior art and its problems) When radioactive particles such as alpha particles enter a semiconductor, a large amount of electric charge is generated inside the semiconductor. When these charges flow into the electrodes inside the semiconductor memory cell, they change the potential of the electrodes, resulting in soft errors. When the amount of charge handled by the electrodes in a semiconductor memory cell is large (J), the effect of such an influx of internally generated charges is small, and this memory cell is unlikely to cause soft errors. When miniaturized, the amount of charge handled by the electrodes in the memory cell decreases T6, which makes the problem of soft errors a little greater.

In conventional semiconductor memory cells, the structure of the poles inside the memory cell is improved to reduce the inflow of charges generated by radioactive particles into these electrodes, and to reduce the charge i handled by these electrodes by more than the inflow lightning and cargo. I was preventing soft collage by using DL. However, since there is a limit to reducing the amount of charge flowing into the electrode in the memory cell, the amount of charge handled by the electrode must be kept above a certain value. Therefore, in the conventional semiconductor memory cell, both its size and its power consumption had to be kept above a certain value. This has been a major obstacle to the miniaturization of semiconductor memory cells and the integration of memory devices using these semiconductor memory cells.

(Objective of the Invention) The object of the present invention is to minimize the occurrence of soft errors caused by radioactive particles such as alpha particles, and to suppress miniaturization and integration in order to prevent soft errors. An object of the present invention is to provide a semiconductor memory cell with a small number of semiconductor memory cells.

(Summary of the Invention) A semiconductor memory cell according to the present invention has a gate electrode connected to a first word line, a first current-carrying electrode connected to a first bit line, and a second current-carrying electrode. 1 conductivity type 1st
FB'l'': a gate electrode connected to a second word line; a first current-carrying electrode connected to a second word line; 21st!”E
'1', the second current-carrying electrode of the first PET and the second
A semiconductor memory cell including a capacitor connected between the second ii1'lI electrode of the FET, and the first FET.
is a semiconductor crystal substrate L-shaped H, and the second F B 'I
' is a semiconductor film ζ shaped like Cc on the crystal substrate in the above-mentioned half 2
It is characterized by the formation of

(Example: Configuration) Next, the operating principle and effects of the semiconductor memory cell of the present invention will be explained using an example of the present invention. FIG. 1 shows the structure of an embodiment of a semiconductor memory cell according to the present invention, and FIG. ' and shows a cross-sectional view when cut with CO2. 101 in the same figure shows a conductive film that also serves as a first word line and a gate electrode of the first N-type channel M08FET;
Reference numeral 102 denotes an N-type head region that serves as the current-carrying electrode of the first MOS F Ei', 103 an N-type region that serves as the current-carrying electrode of the first M08FET and one electrode of the capacitor (hereinafter referred to as cell capacitance), and 104 the second Word line and P type channel 2nd M08F
105 is the second M0, which is a conductive film that also serves as the gate of ET and a pole.
8 P-type region which becomes the current-carrying electrode of FET, 106)
'tf of one of the current-carrying electrode and the soldering capacitance of M
L pole F! 107 is an insulating film that forms a cell capacitor; 108 is a conductive film that serves as the first bit line (!: conductive film; ]09 is a conductive film that serves as a second bit line; 110 is a P-type region) Silicon crystal substrate, 111 is an N type region, 112 is an N
Type channel No. IMO8PET gate insulator film, 113
il P-type channel 2nd M08F'BT gate insulator film, 114 and 115 are 1 insulator films, 116 is 10
Contact hole for connecting between 2 and 108, 117 is 1
Contact holes connecting between 05 and 109 are shown, respectively.

As shown in FIG. 1, N-type channel 1M08FE
T is the P-type silicon crystal substrate 110 V substrate region;
type silicon crystal substrate 110. Two N type regions 102, 103 are formed by diffusion, ion implantation, etc.
is configured as energized tfM. - 10,000, P-type channel 2M (J8FET is /Silicon 1fdl) N-type region] 11 is the substrate region, P-type region 105, 106
Through I! Configured as an electrode. Hereinafter, in the description of the present invention using the embodiment shown in FIG. 1, this series: I 7Pja1
It is assumed that 05, 106, and 111 are polycrystalline silicon films recrystallized by a method such as laser annealing.

Of course, as long as the second MOS F E '1' satisfies the properties described below, it may be a semiconductor film other than ct't, or other Noricon films, such as hydrogen plasma annealed Polyrecon p or / Rifun. .

(Example, operation principle fM> FIG. 2 is equivalent to the embodiment shown in FIG. 1 [c!I omitted. The operation principle of the semiconductor memory cell of the present invention will be explained using this diagram. 201 is a Noricon crystal. The N-type channel MOSFET 202 formed on the substrate is a P-type channel MO8FET formed on the recrystallized polycrystalline silicon film.
03 G'! 204 and 205 indicate the amount of pickled juice] S, 204 and 205 respectively. The word lines 206 and 207 of M2 are the first . a second bit line,
208 and 209 are lower potentials (values are O
21O1211 is the node N, respectively.
l indicates the parasitic capacitance of N2 (values are 01 and 02).

The memory cell in FIG. 2 has a first word line 204 at a high potential, a second word line 205 at a low potential, and a double-edged MO8.
It is selected by turning on FET2 (11, 202), and it becomes possible to write and read data from the bit line.Also, the first word line 204 is set to a low potential, and the second word line 205 is set to a low potential. and both M (J8FE
By turning off T201 and T202, this memory cell enters the holding state.

Hereafter, when holding - the state where the potential of node N1 is higher than the potential of node N2 will be referred to as the "holding state of information" and the state of node N1 (0
111: The state where the potential is lower than the potential of the node N2 is made to correspond to the "0° information retention state."

Furthermore, the high power supply potential VDD and the low power supply potential (JV).

It is assumed that the low potential is equal to the highest power supply potential and i&low power supply potential used in a semiconductor device using the memory cell of the next embodiment.

When a semiconductor Z+C alpha particle particle is incident, a large number of charges are generated within the semiconductor, and when the charge flows into an electrode within the semiconductor, the potential of the electrode changes to the ML pole. It is well known that changes occur in the direction of reducing the potential difference between the semiconductor and the surrounding semiconductor.

Let us consider a case where the node N1 of the present semiconductor memory cell in the "1" information retention state is affected by the incidence of alpha particles or the like.

Potentials of nodes Nl and N2 immediately before alpha particles etc. are incident (1, each Vl for simplicity)D.

Assume that V D D /2. 1 for paranormal capacity
.

When C2 is small and the amount of charge given by (CI+02)・Vl)D/2 is smaller than the amount of charge generated by alpha particles etc. that affect node N1+,
The potential of the node Nl (corresponding to the N-type region 103i in FIG. 1) decreases from VDD to the potential of the surrounding semiconductor near 0■. At this time, the potential at the node N2 is expressed by the capacitance cup link l of the cell capacitor 11203.
Ru. Although this +N is less than the lowest power supply potential Ov used in the semiconductor device Pfj using the memory cell of this embodiment, the node N2 (corresponding to 1061 in FIG. 1) is an isolated P-type region. Therefore, no problem arises simply by increasing the PN junction reverse bias between the P-type region and the surrounding region.

Charges generated in a semiconductor by alpha particles, etc. (or charges that are dissipated due to diffusion, and after a certain period of time after the alpha particles, etc. are incident, almost all of them disappear.For example, on the order of micrometers) In the semiconductor device in which the memory cells of this embodiment are repeatedly arranged with dimensions of After a nanosecond, the effect is almost gone.

In this way, the stock position of the dark IC1N point N2, which is almost unaffected by alpha particles, etc., is re-opened again.
When V+ is returned, node N1's deflection is approximately 1℃ ls+c:1
) (C8+02). This (due to the incidence of J alpha particles, etc.)
The amount of electricity stored in the cell capacitor 203 or the potential difference is C8/(C8+01)(O8+02)
6゜ This means that it has decreased to 1[1J For example, CI=Q
2 = O8/1n death is P, 26Φξ1j.

The disconnection and protrusion operation of the memory cell in this embodiment is performed on both MO8F.
The first one that occurs when ET201.202 is turned on.
This is done by sensing the potential difference change between the bit line 206 and the second line 2o7. The judgment as to whether this memory cell holds "0" or "1" information can be made, for example, by determining whether the potential at node Nl is higher than the potential at node N2 before reading the bit. This is done by a method such as sensing a change in the line-to-center difference.Therefore, in the memory cell where the alpha particles etc. have entered, the nodes N1 and N2 are
Although the potential difference between them has become smaller, the height relationship C remains unchanged, so it is determined that "1" information is held. In other words, the held "1" information remains without being destroyed. Furthermore, in the above example, the node Nl(!:
Since the potential difference between the nodes N2 remains more than 80% of the potential difference when alpha particles etc. were not incident, the performance required for the sensing operation is not so severe. 0110S 0
If the memory cell of this example is designed so that the ratio of (J.S.
The FET is formed using a recrystallized polycrystalline silicon film. In general, the leakage current is larger than that of a MOSFET formed on a single crystal Noricon substrate.
In order to withstand this, the time required for the charge stored in the cell capacitance to be lost due to the leakage current of the MOSFET that makes up this memory cell is the time required for the charge generated by alpha particles etc. to dissipate. It is necessary that the time is f minutes longer than the time it takes to have almost any influence. However, in the memory cell of this embodiment, which has the dimensions of a typical micro make order, the above cell capacity is
The time required for the charge to be lost is on the order of a micro-sheet or more, so there is no problem.

In order to explain the operating principle of the memory cell of this embodiment, we will use the example of the case where the memory cell is in the "do information holding state and the influence of alpha particles etc. occurs at the node NU" as an example. ,
In the case of Go et al., the same is true when the "0" information is retained or when the influence of alpha particles etc. is exerted on the node N2.If the influence of alpha particles etc. is exerted on the 0 point N2, the node N2 is Because it is in the film, the pages on the solicon board,
The degree of its shadow/light is smaller than when it is affected by the alpha particle temple.

In addition, in the above embodiment d, an n-channel MUSFET is used.
is formed on the substrate, and the p-channel MOS I''h2T is formed on the semiconductor film, but it goes without saying that the reverse may also be used.
etc. may also be used.

(Effects of the Invention) As explained above, the memory cell of the present invention is generally a MISFET of both F and N channels, in which the stored information is not destroyed even if radioactive particles such as alpha particles are injected into the body. If these are mounted on the same soric crystal substrate, it is necessary to increase the distance between both MISFETs in order to insulate them. Therefore, the M I S of both P and N channels
The dimensions of devices with integrated memory cells tend to be large; however, the memory cell of the present invention
Since the 5FET is insulated from the silicon crystal substrate and one silicon film is formed, P and N channel MIS
The number of FETs close to 5 is extremely desirable for high integration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the structure of a semiconductor memory cell of the present invention, where (a) is a plan view, (bJ and (CJ) are #T planes when cut at HB' and 00' in (a), respectively. It is a diagram of the equivalent 1r31 path of the second implementation f11 in Figure 1. +01...Conductor N1ξ ]02...
N-state region, 103°...N-type region, ]U4...
...Conductor cavity, 105...P-type region, 106
...P-type ship area,]07...Insulator film, 108
......$Hayabusa, experience, 109...conductor film, 11O...PZtll/ll crystal substrate, 1]1
......N-type region (105, 106, 111i, silicon film t is formed 6), 112...N-type channel IMOS FET insulation experience, 113 = -Pi ( Lina Furu MS SF
Ei' (1) Mer-1-insulator film, 201-=1
01, 102.103, 112 to 6N type channel 4 (J 8 P E 'I', 202...
... P-type channel MO8FET consisting of 104, 105, 106, Ill. The cell capacity consists of 203...103.106.107, and the first cell capacity consists of 204...101.
The second word line consists of 2tJ5...104, the first word line consists of 206...108, and the first word line consists of 207...109. The second hit line. Figure 1 O Figure 2

Claims (1)

[Claims] A first FET of a first conductivity type having a gate electrode connected to the first word line ζ, a first conductive electrode connected to the first bit line, and a second conductive electrode connected to the second word line; a second FE of a second conductivity type having a connected gate electrode, a first current-carrying electrode connected to a second bit line, and a second current-carrying electrode;
T, a second current-carrying electrode of the first FET, and the second FET.
A first FET is formed on a semiconductor crystal substrate, and a second FET is formed on a semiconductor group formed on the semiconductor crystal substrate. A semiconductor memory cell characterized by being formed.