JPH0740433B2 - Semiconductor memory cell - Google Patents

Description

The present invention relates to a static semiconductor memory cell in which soft errors caused by radioactive particles such as alpha particles are less likely to occur even when miniaturized.

When radioactive particles such as alpha particles enter a semiconductor, a large amount of charges are generated inside the semiconductor. When these charges flow into the electrode inside the semiconductor memory cell, the potential of the electrode is changed, resulting in a soft error.
When the amount of charges handled by the electrodes in the semiconductor memory cell is large, the influence of such inflow of internally generated charges is small, and this memory cell rarely causes a soft error. However, when the semiconductor memory cell is miniaturized, the amount of charge handled by the electrodes in the memory cell is reduced, and the problem of soft error becomes serious.

In the conventional semiconductor memory cell, by improving the structure of the electrode inside the memory cell to reduce the inflow of charges generated by radioactive particles into this electrode, and to keep the amount of charge handled by this electrode above the amount of inflow charges. It was preventing soft errors. However, since there is a limit to reducing the amount of charge flowing into the electrode in the memory cell, it is necessary to keep the amount of charge handled by the electrode above a certain value. Therefore, in the conventional semiconductor memory cell, its size and its power consumption have to be kept above a certain value. This has been a major obstacle to miniaturization of this semiconductor memory cell and integration of a memory device using this semiconductor memory cell.

An object of the present invention is to provide a semiconductor memory cell in which generation of soft error caused by radioactive particles such as alpha particles is extremely small, and miniaturization and integration are not limited as a countermeasure for soft error. is there.

The semiconductor memory cell according to the present invention includes a first conducting electrode, a second
A first FET of a first conductivity type having a current-carrying electrode and a gate electrode;
The first conducting electrode connected to the first conducting electrode of the first FET, the first F
A first conductive type second FET having a second conducting electrode connected to the ET gate electrode and a gate electrode connected to the second conducting electrode of the first FET; a first conducting electrode, a second conducting electrode, and a gate electrode. A second FET of the second conductivity type, a first current-carrying electrode connected to the first current-carrying electrode of the third FET, a second current-carrying electrode connected to the gate electrode of the third FET, and a second current-carrying electrode of the third FET. Second conductive type fourth FET having a gate electrode, a first diode connected between the second conducting electrode of the first FET and the second conducting electrode of the third FET, the second conducting electrode of the second FET and the fourth FET And a second diode connected between the second current-carrying electrodes.

Next, the operating principle and effect of the semiconductor memory cell of the present invention will be described with reference to the drawings.

FIG. 1 shows an example in which the memory cell of the present invention is constructed by using a MOSFET and a silicon junction diode. In this figure
101 and 102 are P-type channel MOSFETs 103 and 104 are N-type channel MO.
SFETs, 105 and 106 are silicon junction diodes connected in the forward direction, 107 and 108 are N-type channel MOSFETs used as select gates, 109 and 110 are power supply lines, 111 and 112 are word lines,
Reference numerals 113 and 114 denote bit lines, respectively.

In the example of this figure, the threshold voltage of the N-type channel MOSFETs 103, 104, 107 and 108 is 1V, and the threshold voltage of the P-type channel MOSFETs 101 and 102 is -1V. Is assumed to be able to flow. Further, a constant potential of 5 V and 0 V is supplied to the power supply lines 109 and 110, respectively, and the silicon junction diode 105,
106 is assumed to have a forward current-voltage characteristic as shown in FIG.

Now, consider writing to this cell. N
Consider a case where the potentials of the node N2 and the node N4 are 5V and 4.4V, respectively, in the off state of the type channel MOSFETs 107 and 108. At this time, the N-type channel MOSFET 103 turns on and the P-type channel MOSFET 1
01 is off. Therefore, the potential of node N3 quickly
The potential at node N1 becomes 0 V, and if the potential at node N1 is 1 V or higher at the beginning, it gradually decreases due to the current flowing through the diode.
Assuming that the capacitance of 1, N2, N3, N4 is about 10 ^-14 F, it will be about 0.6 V after 10 nanosecond order. This 0.6 V corresponds to the applied voltage when the diode current shown in FIG. 2 is on the order of 1 μA. After that, the potential of the node N1 gradually decreases due to the diode current with the passage of time, and becomes about 0.4 V after, for example, 10 microseconds. on the other hand,
Since the potential of the node N1 and the potential of the node N3 are 0.6 V or less and 0 V, respectively, the P-type channel MOSFET 102 is on and the N-type channel MOSFET 104 is off. Therefore, the potential of the node N2 is maintained at 5V, the potential of the node N4 gradually rises due to the current flowing through the diode 106, and is about 10 nanoseconds later.
4.4V, rises about 4.6V after 10 microsecond order.

In this way, the state in which the nodes N2 and N4 are at high potential and the nodes N1 and N3 are at low potential is stable and held forever. Also, as this memory cell is symmetrical, it is easy to see that
The opposite situation where nodes N1 and N3 are at high potential and nodes N2 and N4 are at low potential is also stable. The present memory cell functions as a memory cell by relating these two stable states to binary information.

Writing and reading operations are performed through the bit lines 113 and 114 with the word lines 111 and 112 set to a high potential and the N-type channel MOSFETs 107 and 108 turned on.

When the charge generated in the semiconductor by the incidence of radioactive particles such as alpha particles flows into the electrode inside the semiconductor, the electric potential of the electrode changes so as to reduce the potential difference between the electrode and the surrounding semiconductor. To do. Therefore, when the semiconductor internal electrode and the surrounding semiconductor are originally at the same potential, the electrode potential is not affected by alpha particles or the like.

In the example of the memory cell of FIG. 1, the semiconductor regions forming the nodes N1 and N2 can be limited to the P-type semiconductor, and the semiconductor regions adjacent to the nodes can be limited to the N-type semiconductor kept at the potential of 5V. Because nodes N1 and N2 are P-type channel MOSFETs 101 and 102.
Connected to the drain region of the diode and the P-side regions of the diodes 105 and 106. These regions are usually P-type semiconductors,
Further, since MOSFETs having different conductivity types are formed on the same semiconductor substrate, these regions are formed in an N-type semiconductor called an N well to which a 5V potential is supplied.
Similarly, the semiconductor regions forming the nodes N3 and N4 can be limited to N-type semiconductors, and the semiconductor regions adjacent thereto can be limited to P-type semiconductors maintained at the potential of 0V.

Α when the nodes N2 and N4 are at high potential and the nodes N1 and N3 are at low potential
Consider a case where radioactive particles such as particles are incident. Node N2, N
Since the potential of 3 is the same as that of the surrounding semiconductor region, the state of the present memory cell is not destroyed even if the α-particles enter here because of the above reason. Incidentally, since it is extremely unlikely that the incidence of α particles affects two or more nodes at the same time, it will not be considered here.

Next, in this state, consider the case where an α particle or the like is incident on the node N1. In this case, holes generated by α particles or the like flow into the P-type semiconductor region forming the node N1, and the potential thereof sharply rises to 5V, which is the same as the potential of the surrounding N-type region.
In this way, when the P-type region becomes 5 V, the potential near the P-type region becomes constant, so that the inflow of holes is stopped.

Therefore, the flow of holes generated by α-particles etc. flowing into the node N1 is large for the first few nanoseconds but becomes smaller thereafter, and in general, the MOSF composing this memory cell is
It becomes negligible compared to the on-current of ET.

In this way, when the potential of the node N1 becomes 5V, the diode 10
A current flows through 5, and the potential of the node N3 rises to about 4.4V after 1 nanosecond order. On the other hand, the incidence of α particles and the like, after the writing operation to the memory cell is performed,
Assuming that this occurred when the order of 10 microseconds or more had passed, the potential of the node N4 was 4.6V or more. As mentioned above, after a few nanoseconds have passed since the α particles etc. are incident,
Since the current generated by particles etc. can be almost ignored,
After that, it is not necessary to consider the current that flows through the diode 105 and raises the potential of the node N3. Then, in a few nanoseconds, the potentials of the nodes N3 and N4 are 4.4 V and 4.6 V or higher, respectively, and a slight potential difference (0.2 V or higher) remains between the N3 and N4, which are subsequently MOSFETs 103 and 104. It is amplified by the differential amplifier composed of. That is, the potential of node N3 is
Since it is lower than N4, it drops to 0 V, and the potential of node N4 is the node
Since the MOSFET 102 is turned on by the decrease in the potentials of N3 and N1, the potential is pulled up to a high potential.

In this way, even if radioactive particles such as α particles enter the node N1, the state of the memory cell is not destroyed. This is true even when α particles enter the node N4 when the memory cell is in the other state, that is, when the nodes N1 and N3 are at high potential and the nodes N2 and N4 are at low potential. To do. The case where α rays are incident on N4 will be described below. It is assumed that the power supply voltage is 5V, the voltages of the nodes N1 and N2 are 0.4 and 5V, and that the voltages of N3 and N4 are 0 and 4.6V, respectively, as in the above-mentioned embodiment, which is a stable state. If α rays enter N4 in this state, electrons flow in from the surroundings and the potential drops to the same potential as 0V of the p-type region surrounding N4 (the p-type region is connected to 0V). In short, information is destroyed. Since the time for the current to flow by the α-ray is several nanoseconds, the current flows through the diode 106 during this several nanoseconds, and N2 drops to about 0.6V. On the other hand, N1 is 0.4V, so the potential difference with N2 is 0.
2V remains. Information is destroyed in N3 and N4, but N
Information remains between 1 and N2. It's a transistor 10
It is amplified by 1 and 102 and returns to the original state. That is, since the potential of N2 is higher than N1, 102 is turned on and 101 is turned off, and the original state is restored.
Therefore, the present memory cell is a memory cell whose storage state is less likely to be destroyed by the incidence of α particles or the like.

In order to explain the operation of this memory cell, a silicon junction diode is used as the diode in the embodiment of FIG. 1, but the present invention is not limited to this.

Other diodes may be used as long as their current-voltage characteristics are exponential, as shown in FIG. For example, a potassium arsenic junction diode may be used, or two or more silicon junction diodes may be connected in parallel or in series. As shown in the embodiment of FIG. It may be a diode.

FIG. 3 shows another embodiment of the memory cell of the present invention. Instead of the silicon junction diodes 105 and 106 of FIG. 1, a diode composed of an N-type channel MOSFET in which one current-carrying electrode and gate electrode are combined is used.
This is the same as the illustrated embodiment. First digit and 2 of the number indicating each part
The digit corresponds to that in FIG. This embodiment is characterized in that the current-voltage characteristic of the diode can be freely changed by changing the threshold voltage and the gain constant of the MOSFET.

In the description of the operation of the memory cell of the present invention, it is considered that α particles or the like are incident after a time of 10 microseconds or more has passed after the writing operation. However, the effect of the memory cell of the present invention does not disappear even if the incidence of α particles or the like is earlier than this. If the incidence of α particles etc. is earlier, the potential difference between nodes N3 and N4 will be smaller than 0.2 V in the above example, but if the sensitivity of the above differential amplifier is correspondingly high, the memory state will not be destroyed. is there.

Furthermore, if the characteristics of the diode are changed, it is possible to further increase the potential difference between the nodes N3 and N4 when an α particle or the like is incident. For example, as the diodes 105 and 106 in FIG. 1, if two silicon junction diodes having the current-voltage characteristics shown in FIG.
Contact points N3, N when α particles etc. are incident after microsecond order
The potential difference between 4 can be doubled to about 0.4V. This is because the slope of the current-voltage characteristic of the diode in which two silicon junction diodes are connected in series is half of that in FIG.

In the description of the operation of the memory cell of the present invention, the node N1 is α
It was stated that the potential of the node N1 becomes 5V, which is the same as that of the surrounding N-type semiconductor region, when a particle or the like is incident, but it may exceed 5V in a short time in reality. Even in this case, there is no problem if the threshold voltage at which the diode 105 passes a current of 1 μA order is lower than the threshold voltage at which the P-type channel MOSFET 101 passes a current of 1 μA order. Because the gate voltage of the P-type channel MOSFET 101 is 5V, when the potential of the node N1 becomes 5V or more minus the threshold voltage of the P-type channel MOSFET 101, the P-type channel MOSFET 101 turns on. This is because the potential of does not exceed this value.

As described above, the maximum value of the potential of the node N1 is not only the potential of the N-type semiconductor region around it but also the P-type channel MOSF.
It is also determined by the threshold voltage of ET101.

Therefore, it is not necessary to limit the substrate potential of the MOSFETs constituting this memory cell to 5V for the P-type channel MOSFET and 0V for the N-type channel MOSFET as shown in the example of FIG.

The operation of the semiconductor memory cell according to the present invention has been described above with reference to the embodiment shown in FIG. 1, particularly focusing on the potential at the node N1, but the present invention is not limited to this.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example in which a memory cell of the present invention is configured by using a MOSFET and a silicon junction diode. FIG. 2 is a diagram showing the forward current-voltage characteristics of the silicon junction diode used in FIG. FIG. 3 is a circuit diagram showing another embodiment of the memory cell of the present invention. In the figure, 101, 301, 102, 302 ... P-type channel MOSFE
T, 103,303,104,304,107,307,108,308 ... N type channel
MOSFET, 105,106 ... Silicon junction diode, 305,306
...... Diode composed by combining one current-carrying electrode and gate electrode, 109,309,110,310 …… Power supply line, 111,311,112,3
12 …… Word line, 113,313,114,314 …… Bit line

Claims (1)

[Claims] 1. A first FET of a first conductivity type having a first conducting electrode, a second conducting electrode, and a gate electrode, a first conducting electrode connected to the first conducting electrode of the first FET, and a gate electrode of the first FET. A second conductive type having a second conductive electrode connected thereto and a gate electrode connected to the second conductive electrode of the first FET, and a second conductive type having a first conductive electrode, a second conductive electrode and a gate electrode The third FET, the first conducting electrode connected to the first conducting electrode of the third FET, the second conducting electrode connected to the gate electrode of the third FET,
A second conductive type fourth FET having a gate electrode connected to the second conducting electrode of the third FET, a second conducting electrode of the first FET and a third FET
A first diode connected between the second conducting electrodes of
A semiconductor memory cell, comprising: a second conducting electrode of a 2FET and a second diode connected between a second conducting electrode of a fourth FET.