JPS6038864A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To reduce the generation of a soft error induced by radioactive particles such as alpha particles extremely by using currents flowing through an MOSFET as ON currents for the MOSFET. CONSTITUTION:Currents flowing through an MOSFET101 are considerably large because they are used as ON currents for the MOSFET. Consequently, generated currents from alpha particles, etc. are brought to the ON currents or higher, potential at a node N1 elevates at considerably fast speed in order to rise up to 1V order, and its speed is at 0.1 nano sec order. As a result, potential at a node N3 does not drop and reach to potential (approximately 0V) or lower at a node N4 during that time. Accordingly, the nodes N1, N3 return to SV and nodes N2, N4 to 0V, and the state before the projection of alpha particles, etc. is kept. Since a time constant T3 as the product of the capacitance of the node N3 and a resistor 105 and a time constant T4 as the product of the capacitance of the node N4 and a resistor 106 are larger than a time constant Talpha until a recovery by ON currents for the MOSFET after potential at the node N1 or N2 is changed by generated currents from alpha particles, etc., the state of a memory cell is kept, and a soft error is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static semiconductor memory cell in which soft errors caused by radioactive particles such as alpha particles are less likely to occur even when miniaturized.

When a radioactive particle such as an alpha particle enters a semiconductor, multi-11 charges are generated inside the semiconductor. When these charges flow into the electrodes inside the semiconductor memory cell, they change the potential of the electrodes, resulting in soft errors. When the amount of charge handled by the electrodes in a semiconductor memory cell is large, the influence of this inflow of internally generated charges is small;
This memory cell rarely causes soft errors. However, as semiconductor memory cells become smaller, the amount of charge handled by electrodes within the memory cells decreases, so the problem of soft errors becomes more serious.

In conventional semiconductor memory cells, the structure of the electrode in the memory cell is improved to reduce the inflow of charges generated by radioactive particles into this electrode, by keeping the amount of charge handled by this electrode greater than the amount of inflowing charge. This prevented soft errors. However, there is a limit to reducing the amount of charge flowing into the negative electrode within the memory cell, so the amount of charge handled by that electrode must be kept above a certain value. Therefore, in conventional semiconductor memory cells, both their size and power consumption must be kept above a certain value. This has been a major obstacle to miniaturization of semiconductor memory cells and integration of memory devices using these semiconductor memory cells.

An object of the present invention is to provide a semiconductor memory cell in which the occurrence of soft errors caused by radioactive particles such as alpha particles is extremely low, and miniaturization and integration are not limited in order to prevent soft errors. It is.

The semiconductor memory cell according to the present invention includes a first current-carrying electrode, a second current-carrying electrode, and a second current-carrying electrode.
A first FET of a first conductive type having a current-carrying electrode and a gate electrode.
and a second transistor of the first conductivity type, which has a first quadrupole connected to the first quadrupole of the first FET, a first current-carrying electrode, and a gate electrode.
FET, a first current-carrying electrode, a second current-carrying electrode connected to the second conductive electrode of the first FET, a gate 'rs connected to the gate electrode of the first FET, and a second conductive type electrode having a pole. 31! ``1.; 'r and the first current-carrying electrode connected to the first current-carrying electrode of the third FET, the second electrode 1 (L) of the second F'BT
a second current-carrying electrode connected to the polarization, a fourth conductive electrode having a gate electrode connected to the gate electrode of the second FET;
, E' ET and the gate of the 1st F'ET and the 2nd F
a first resistor connected between the second current-carrying electrodes of ET;
2+' 2 F L! : T gate electrode and first FET
A second resistor connected to [1■ of Ii],
It is characterized by having the following.

Next, the operating principle and effects of the semiconductor memory cell of the present invention will be explained with reference to the drawings. FIG. 1 shows an example of a memory cell of the present invention constructed using a tVOS FET. In this figure, 101.1024″l: P-type channel MO8FET, 103.104 is N-type channel MO8
FETs 105 and 106 are resistors, and 107 and 108 are connected to N-type channels used as selection gates.
', 109 and 110 are power supply lines, 111 and 112 are word lines, and 113 and 114 are bit lines, respectively. In the example in this figure, the NJM channel - MO8FET 103.1
04.107.108 CDH value voltage i't, I V
.

The threshold voltage of the P-type channel MO8FET 101.102 is -IV, the time constant T3 which is the product of the capacitance of node N3 and the resistance 105-, and the time constant T4 which is the product of the capacitance of node N4 and the resistance 106 are both 1 nanosecond. It is an og, power line 109
, 110 are supplied with constant potentials of 5V and oV, respectively.

Naka, the potential of nodes Nl and Na is 5V, and fflj point N2. N
Consider the case where the potential of 4 is Ov. In this case 1vlO8P
ET101, 104 are on, ET102, 103 are off, and node N1. N3's 11th place 5V and N1 point N2. N
4 (D potential OV is held. In this way, the node Nl
, Na is still at potential, node N2. The state where N4 is at a low potential is stable and is maintained indefinitely. Furthermore, since this memory cell is symmetrical, it can be easily seen that the node N2. N4
In the opposite situation, where N1 and N3 are at a high potential and nodes Nl and N3 are at a low potential, the cap is similarly stable. This memory cell functions as a t memory cell that corresponds to binary information between these two stable states.

Write/read operations are performed on word line 111. This is done through the bit lines 113 and 114 by bringing i12 to a high potential and turning on the N-type channel MO8FETs 107 and 108.

When charges generated within a semiconductor due to the incidence of radioactive particles such as alpha particles flow into an electrode inside the semiconductor, the potential of the electrode changes in a direction that reduces the potential difference between the electrode and the surrounding semiconductor. . In the case of the memory cell of FIG. 1, both nodes Nl and N2 have P
P) inscribed in the substrate region of M channel MO8li'BT
type semiconductor and N, 1 channel MO8FET kept at 0■
consists of an N-type semiconductor amphitheater conductor adjacent to the substrate region.

Therefore, due to the incidence of α particles etc. at both nodes Nl and N2, 5
(2) Or it may fluctuate in either direction until the power supply voltage of Ov approaches.

Node N1. When N3 is at a drunken potential, N constituting node N1
Suppose a case 1 in which α particles or the like are incident on a P-type semiconductor region and a P-type semiconductor region that is kept in contact with the P-type semiconductor region. In this case, electrons generated by α particles etc. flow into the N-type region constituting the node N1, and the potential of the surrounding P,! ! l!
! It rapidly drops to OV, which is the same as the potential of the region. More precisely, the potential at the node Nu decreases to a voltage at which a certain amount of forward current flows through the PN junction diode formed between the N-type region constituting the node N1 and the surrounding P-type region.

Here, this value is assumed to be 10.7V. Like this N
) When the potential of the M region reaches 1 higher than the potential of the surrounding P-type region, the influx of electrons generated by α particles and the like stops.

Therefore, although the flow of quadruplets generated by α particles flowing into node N1 is large on the order of 0.1 nanoseconds at the beginning, it becomes smaller after that, and is generally compared to the on-state current of the MOSFET that constitutes this memory cell. It becomes possible to ignore it.

As described above, since the influence of the current generated by α particles and the like is short, on the order of 0.1 nanoseconds, a potential change at the node N1 is hardly transmitted to the node N3 within this short time. Therefore, the potential of node N2 remains near Ov, and the potential of node N4 drops slightly from OV due to the influence of the parasitic capacitance of MO8F]1iliT, and MO8F'ETIOI is in the on state and MO8li"ET 10314 is in the off state. does not change.Therefore, MO8FET is installed at node N1.
Current continues to flow through 101. This MO8FE
'i1 flowing through T101! viu tries to raise the potential at the node N1 to 5V, while the current generated by the α particle tries to lower the potential at the node Nl to below O■.

In the semiconductor memory cell of the present invention, the above MO8F-IB
Since the current flowing through 'L' 101 is the on-current of the T connected to the MOS, it is quite large. Therefore, the α particle generation current becomes less than this on-state current, and the rJfi point N1 check 1 rises to 1 og fairly quickly, on the order of 0.01 nanoseconds. Therefore, during this time, the potential of node N3 does not fall below the potential of node N4 (approximately OV),
After all, nodes Nl and N3 are 879 nodes N2. N4 returns to OV, and the state before the incidence of α particles etc. is maintained.

In the memory cell of the present invention, the capacitance of the node N3 and the resistance 105
The product of time constant &T3 and flfj point N4 capacitance and resistance 1
The time constant T4, which is the product of
Time constant T until the on-current of FET rises and recovers
Since it is larger than α, the state of the memory cell is maintained and soft errors are prevented.

Therefore, the time constant T3. The value of T4 does not need to be on the order of 1 nanosecond as described in the above example, and may be larger than the time constant Tα to some extent. However, the time constant T3. Since the values of qr and i determine the writing time of this semiconductor memory cell, they cannot be made too large.

FIG. 2 shows another embodiment of the semiconductor memory cell of the present invention. Node N1. The embodiment is the same as the embodiment shown in FIG. 1, except that capacitors i 215 and 216 are inserted between 'N4' and between nodes N2ζN3', respectively. The first digit of the number indicating each part corresponds to that in FIG. In this embodiment, for example, when the potential at the node N 1 / drops from 5V due to the incidence of α particles, the change is transmitted to the node N4', and the potential at the node N 4
The value of / becomes less than O■, so MO8FE'v20
The on-current of No. 1 is larger than that of the embodiment shown in FIG. 1, and the time constant Tα for recovering the potential of the node Nl' is smaller. This is the time constant T3. This is convenient for reducing T4 and shortening the writing time of this memory cell.

In order to explain the operation of the semiconductor memory cell of the present invention, i.
ij The explanation has focused on the case where the source voltage is OV, 5V, and the potential at the node N1 drops from 5V due to the α particle generation current in the embodiment of FIG. 1, but the effect of the semiconductor memory cell of the present invention is The same applies to other cases.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a semiconductor memory cell of the present invention configured using MOSFETs. FIG. 2 is a circuit diagram showing another 1m example of the semiconductor memory cell of the present invention.

Claims (1)

[Claims] A first conductive electrode having a first conductive electrode, a second conductive electrode, and a gate electrode.
A 4-type first PET, a first conductive type second FET having a first conductive electrode connected to the first conductive electrode of the first FET, a second conductive electrode, and a gate electrode;
．． The second t connected to the second energized electrode of F hi T
- to pole 1. [a F I of the second conductivity type having a gate electrode connected to the gate electrode of the IFET]'r, a first current-carrying electrode connected to the first current-carrying electrode of the third Ii''ET, and a first current-carrying electrode connected to the first current-carrying electrode of the second FET. a fourth FET of the second conductivity type having a second conductive four electrode connected to the second conductive electrode, a gate electrode connected to the gate/electrode of the second FET;
A first resistor connected between the gate electrode of the ET and the second current-carrying electrode of the second FET, the gate electrode of the second FET, and the first FE
a second resistor connected between the second current-carrying electrodes of the semiconductor memory cell.