JPS6233393A - Semiconductor non-volatile memory device - Google Patents

Abstract

PURPOSE:To constitute a non-volatile memory part without using many capacitors by connecting a drain and a gate to the other gate and the other drain in two terminals and connecting respective drains of a pair of MOS transistors having floating gates in a gate insulating film to commonly connect a source. CONSTITUTION:A non-volatile memory part 20 consists of a pair of MOS transistors 21, 22 in which one gate is connected to the other drain respectively and a thin film floating gate for holding an electric charge in a gate insulating film is provided. The drains of the pair of MOS transistors 21, 22 are connected to writing and reading lines of a memory cell 10 for RAM through high voltage- proof connecting MOS transistors 23, 24. The MOS transistors 21, 22 are high potential proof so as to endure high potential, respectively. Thereby, the constitution of the circuit can be simplified without requiring many capacitors.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor R'AM including a nonvolatile memory section.
The present invention relates to a memory device.

[Technical background of the invention and its problems]

A conventional semiconductor RAM memory device equipped with a nonvolatile memory section is described in Japanese Patent Application Laid-open No. 101192/1983. This conventional semiconductor non-volatile memory device is
A static RAM memory cell with a bistable flip 70-tube (F, F,) circuit is provided with a nonvolatile memory section including pass transistors for reading and writing and several capacitors. Then turn off the power
Sometimes, the equivalent voltage VTR of the pass transistor is changed by word division of the capacitor, and the contents of the RAM memory cell are written to the non-volatile memory section, and conversely, when the power is turned on, data is restored from this non-volatile memory section to the RAM memory cell. It is configured to do this.

However, in the case of such conventional semiconductor non-volatile memory devices, data is written into the memory section by determining the potential by dividing the capacitance of a large number of capacitors, and reading when the power is turned on is performed depending on the magnitude of the capacitance connected to the node. Because of this, designing various capacitors is complicated.
Furthermore, the design of a static RAM memory cell is difficult because it takes into account the unbalance of capacitance, and since it includes a large number of capacitors, it is difficult to reduce the area of the memory cell.

(Object of the Invention) The present invention has been made in view of the above-mentioned conventional problems, and includes a pair of thin film floating devices having one drain and the other gate connected to the terminals of a static RAM memory cell. Gate type MOS transistors are connected, and this pair of thin film floating gate type MOS
The contents of the RAM memory cell are written to the non-volatile memory section by changing the threshold voltage of the transistor, and the contents of the non-volatile memory section are written to the static type RA based on this threshold voltage.
The purpose of this invention is to configure a non-volatile memory section without using a large number of capacitors by reading data into an M memory cell.

[Structure of the invention]

This invention has two high voltage levels and two low voltage levels.
For a static RAM memory cell that latches to two terminals, the drain and gate of one are connected to the gate and drain of the other, respectively, and a This is a semiconductor non-volatile memory device in which the drains of a pair of MoS transistors each having a switching gate are connected, and the sources of these two MOS I-transistors are connected in common.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be explained in detail based on the drawings. 1st
As shown in the figure, a static RAM memory cell 10
is constituted by bistables F, F and circuits with high voltage resistance, and has a pair of depletion type MOS transistors 11 and 12 and a pair of enhancement type MOS transistors 13 and 14. Also, the read/write high voltage pass transistors 15 and 16 of this RAM Tamori cell 10 are connected to the bit lines BL, BL and this memory cell 1.
0. The gates of each of the pass transistors 15 and 16 are connected to the word line WL.

The nonvolatile memory section 20 is composed of a pair of MoS transistors 21 and 22, each having a gate of one connected to a drain of the other (cross-coupled) and a thin film floating gate for retaining charge in a gate insulating film. The pair of MOS transistors 21 and 22
The trains are respectively connected to the write and read lines of the RAM memory cell 10 via high-voltage connection MOS transistors 23 and 24. Here, each of the MOS transistors 21 and 22 has a high breakdown voltage so that it can withstand a high potential.

Further, the RAM memory cell 10 is connected to a power supply line 31, the gates of the connection MOS transistors 23 and 24 of the nonvolatile memory section 20 are connected to a control line 32,
Thin film floating gate type MOS transistor 21.
22 sources are both connected to a control line 33.

The operation of the semiconductor nonvolatile memory device having the above configuration will be described next.

As shown in FIG. 2, in the ON state where the normal voltage VCC is applied to the power supply line 31, by setting the potential of the control line 32 to 0, the nonvolatile memory section 20 is connected to the static RAM memory cell 10. The memory cell 10 continues to operate as a normal bistable circuit.

When the power is turned off, data is written to the nonvolatile memory section 2o. To do this, first, the potentials of the power supply line 31 and the control line 32 are set to a high potential V1)l)(18 to 25
V), and by setting the potential of the control line 33 to a floating state, the node N1 (N1') is set according to the data stored in the static RAM memory cell 1o.
, N2 (N2N potential is determined, i.e. normally R
In AM operation, for example, when N1 is VC01 and N2 is OV, Nl" becomes Vpp and N2- becomes OV. As a result, VOp is applied to the Ov1 drain at the gate of the MOS transistor 21, and electrons are transferred from the floating gate and through the thin film. The voltage flows through the drain, and the threshold voltage VT)I of this MOS transistor 21 decreases.

On the other hand, as for the outside MOS transistor 22, Vpp is applied to its gate and OV is applied to its drain, electrons are injected into the floating gate, and the threshold potential VTH increases.

In this way, the memory contents of the RAM memory cell 10 are stored in the nonvolatile memory section 2Of, -MOS transistor 21
−． 22 threshold voltages.

Next, when the power to the RAM memory cell 10 is restored,
The potential of the power line 31 and control lines 32 and 33 is set to Vcc.
(The control line 32 becomes ○V after a predetermined time), the MOS transistor 22 whose threshold voltage VTH has become high is turned off, and the MOS transistor 21 whose VTH is low is turned on, setting the node N1 to VCC and the node N2 to OV. , and the original data can be restored to the RAM memory cell 10.

Therefore, in this nonvolatile memory device, when the power is ON, the RAM memory cell 10 statically performs the RAM operation, and when the power is OFF, the nonvolatile memory section 20 is in the R
The memory contents of the AM memory cell 10 can be written and held as a nonvolatile memory.

Note that it is of course within the technical scope of the present invention to change the channels of the elements used in the embodiments of the present invention.

Also, static type RA rVI Mesememory Hill 10
It is also possible to configure it with a normal F, F circuit consisting of a resistive element and an enhancement type M○S transistor, and is not limited thereto.

(Effects of the Invention) This invention connects a nonvolatile memory section to a static RAM memory cell, so static RAM
Not only can it be used as an IFII, but it can also hold data as a non-volatile memory when the power is turned off. Moreover, since a pair of MOS transistors are used, the drain and gate of one are connected to the gate and drain stone of the other, respectively, and the floating gate is used to retain charge in the gate insulating film. As such, a large number of capacitors are not required, the circuit configuration can be simplified, the area of the memory cell can be reduced, and reliability can be reduced against manufacturing variations.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a voltage waveform diagram showing the operation of the above circuit. 10... Static RAM memory cell 11.1
2...Depletion type MOS transistor 13.14...Enhancement type MOS transistor 15.16...High voltage pass transistor 20...Nonvolatile memory section 21.22...M having a thin film floating gate
OS transistor 23.24...High voltage pass transistor 31...Power supply line 32.33...Control line Figure 1 Figure 2 ONn

Claims (1)

[Claims] For a static RAM memory cell that latches a high voltage level and a low voltage level to two terminals each, one drain and gate are connected to the other gate and drain, respectively, and gate insulation is applied to the two terminals. A semiconductor nonvolatile memory device comprising a pair of MOS transistors each having a floating gate for retaining charge in the film, each drain of which is connected, and the sources of these two MOS transistors are commonly connected.