JPS6233392A - Semiconductor non-volatile memory device - Google Patents

Abstract

PURPOSE:To constitute a non-volatile memory part without using many capacitors by connecting gates of a MOS transistor to two terminals respectively, and connecting all sources and drains of the MOS transistor to a common control line. CONSTITUTION:A non-volatile memory part 20 is constituted by a pair of MOS transistors 21, 22 having floating gates for holding an electric charge in an insulating film of the gate, the respective gates are connected to a reading and a writing terminals of a memory cell 10 for RAM and all sources and drains of both the MOS transistors 21, 22 are connected to a common control line 23. When an ordinary voltage Vcc is impressed to a power source line 17, the memory cell 10 for RAM performs statically an ordinary RAM operation as a bistable F.F. circuit. The floating gates of the MOS transistors 21, 22 at this time discharge electrons and have a low threshold voltage VTH and nodes A, B have substantially the same capacity. Thereby, the circuit constitution can be simplified without requiring many capacitors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor RAM memory device including a nonvolatile memory section.

[Technical Background of the Invention and Problems Thereof] A conventional semiconductor RAM memory device including a nonvolatile memory section is described in Japanese Patent Application Laid-open No. 101192/1983. This conventional semiconductor non-volatile memory device
A static RAM memory cell using a bistable flip-flop (F) circuit is provided with a nonvolatile memory section including pass transistors for reading and writing and several capacitors. And power off
At F, the threshold voltage VTH of the pass transistor is changed by capacitance division of the capacitor, and the contents of the RAM memory cell are written to the non-volatile memory section.On the other hand, at power & iON, data is written from this non-volatile memory section to the RAM memory cell. It is configured to recover.

However, in the case of such conventional semiconductor nonvolatile memory devices, writing is performed by determining the potential by dividing the capacitance of a large number of capacitors, and reading is performed when the power is turned on depending on the magnitude of the capacitance connected to the node. It is complicated to design various types of capacitors, and static type RA
The design of the memory cell for M is also difficult because it takes into account the unbalance of capacity, and furthermore, it is difficult to reduce the area of the memory cell because it includes a large number of Q17 capacitors.

``Object of the Invention'' The present invention was made in view of the above-mentioned conventional problems. By connecting MOS transistors with floating gates and changing the threshold voltage of both MOS transistors, the memory contents of the RAM memory building can be read and written and retained as non-volatile memory, without using a large number of capacitors. The purpose is to enable the configuration of a nonvolatile memory section.

``Structure of the invention This invention has two high potential levels and two low potential levels.
For a static RAM memory cell that latches on two terminals, an M
This is a semiconductor nonvolatile memory device in which the gates of oS transistors are connected, and the sources and drains of the MOS transistors are all connected to a common control line.

[Embodiments of the invention] Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

As shown in FIG. 1, the static RAM memory cell 10 is composed of a bistable F, which has a high breakdown voltage, and a circuit, and includes a pair of depletion type Mo8
It has I-transistors 11 and 12, and a pair of enhancement type MO8l-transistors 13 and 14. Also RAM
High voltage pass transistors 15 and 16 for reading and writing the memory cell 10 are connected between the bit lines BL and 8m and the memory cell 10. The gates of the pass transistors 15 and 16 are connected to the word line W +-
It is connected to the. The RAM memory rail 10 is connected to a power supply line 17 and supplied with a power supply voltage.

The nonvolatile memory section 20 is composed of a pair of MOS transistors 21 and 22 having floating gates for retaining charges in a gate insulating film, and each gate of the MOS transistors 21 and 22 is connected to the RAM memory cell 1.
Connected to the 0 read and write terminals. The sources and drains of both MOS transistors 21 and 22 are all connected to a common control line 23.

The operation of the semiconductor nonvolatile memory device having the above configuration will be explained below.

As shown in FIG. 2, when the normal voltage VCC is applied to the power supply line 17, the RAM memory cell 10 is statically connected to the bistable F, F, and the normal RA as a circuit.
M-move. At this time, MOS transistors 21 and 22
The floating gate has a low threshold voltage VT it in a state in which electrons are emitted, and nodes A and B are almost the same.

When the power is turned off, it enters write mode and the power line 1
7, high voltage Vpp (1 s to 2
5v) is applied. At this time, control l1Q23
is grounded. Therefore, if, for example, the node A is at Vcc and the node B is at OV during static RAM operation, the gate of the MOS transistor 21 becomes MDI) and the gate of the Mo8t transistor 22 becomes OV in this write mode.

Therefore, no change occurs in MOS transistor 22, but electrons are injected into the floating gate of MOS transistor 21, and its threshold voltage VTH increases. In other words, the contents of the RAM memory cell 10 are written into the nonvolatile memory section 20 as a change in the threshold voltage VTH of the MOS transistors 21 and 22.

Next time the power is restored and turned on, the power line 17
becomes the voltage Vcc. By applying this voltage, the threshold voltage VTI+ of the MOS I to transistor 2 is increased.
Since a channel is difficult to form in case of MOS capacitor 1, the gate voltage t suddenly rises to Vcc first, and the gate voltage of the other MOS capacitor 22 does not rise easily. As a result, the node A is latched to Vcc and the node B is latched to OV by the RAM memory cell 10, and the original stored data is restored to the RAM memory cell 10.

Then, before entering normal RAM operation, the control line 23
By setting MOS capacitor 2 to high voltage Vpp,
1. The state of the floating gate of 22 is reset and kept in the same state. In this way, when the power is turned off in normal RAM operation at J3, the non-volatile memory section 2
0 in the RAM memory cell 10, and when the power is restored, the original data can be read from the nonvolatile memory section 20, realizing nonvolatile RAM operation.

It should be noted that a circuit constructed using a channel element opposite to that of the element of the above embodiment is, of course, included within the technical scope of the present invention. Furthermore, for the static type RAM memory cell 10, it is also possible to configure the bistables F and F circuits each consisting of an enhancement type MOS transistor and a resistance element.

[Effects of the Invention] In the present invention, since a nonvolatile memory section is connected to a RAM memory cell, nonvolatile RAM operation is possible. Moreover, since the non-N-generating memory section is composed of a pair of MOS I-transistors that serve as a 70-channel gate for holding charge in the gate insulating film, there is no need for a large number of capacitors as in the past. First, the design and circuit configuration can be simplified, the area of the memory hill can be reduced, and since the same MOS transistor is used, reliability against manufacturing variations can be improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a voltage waveform diagram showing the operation of the same. 10... Static RAM memory cell 11.1
2...Depletion type OS transistor 13.14...Enhancement type MOS transistor 15.16...High voltage pass transistor 17...Power line 20...Nonvolatile memory section 21.22...・Thin film floating gate type MOS capacitor 23... Control line Patent applicant Nissan Motor Co., Ltd. Figure 1, No. 10 cwn

Claims (1)

[Claims] For a static RAM memory cell that latches a high potential level and a low potential level in two terminals each, a MOS transistor has a floating gate in each of the two terminals to retain charge in the gate insulating film. 1. A semiconductor nonvolatile memory device comprising a gate connected to the MOS transistor, and a source and a drain of the MOS transistor all connected to a common control line.