JPH0137854B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a nonvolatile memory transistor having a floating gate electrode.

In recent years, MOS type semiconductor devices having floating gate electrodes have been used as nonvolatile memory elements, and in particular, ultraviolet erasable nonvolatile memory (EPROM) has become widely popular due to its simple structure, which has increased its capacity and integration.

A cross-sectional view of the structure of this element is shown in FIG. 1 is a semiconductor substrate, 2 and 3 are source/drain regions,
4 is a channel region doped with impurities and has a threshold value V _T . 5 is a floating gate electrode, 6 is a control gate electrode, 7 is a capacitance between the floating gate 5 and the substrate 1 (hereinafter referred to as C _fb ), 8 is a capacitance between the floating gate 5 and the drain region 2 (hereinafter referred to as C fd ), and 9 is a capacitance between the floating gate 5 and the drain region 2 (hereinafter referred to as C _fd ). The capacitance between the floating gate 5 and the source region 3 (hereinafter C _fs ), 10 is the capacitance between the floating gate 5 and the control gate 6 (hereinafter C _cf )
It is. This memory element performs "writing" by injecting high-energy carriers generated in the channel into the floating gate electrode 5, retains memory, and energetically excites the accumulated charges by irradiating ultraviolet rays to the substrate. 1 and is released to the control gate electrode 6 to perform "erasing". After the charge is discharged, the memory cell transistor becomes equal to the threshold value before writing, and "erasing" is completed. Therefore, in an N-channel transistor, if the threshold voltage before writing is set positive, the threshold voltage of the memory transistor changes only within the range of positive values. Therefore, when a cell array is constructed using these memory transistors, a memory matrix can be conventionally constructed with a 1-bit-1 transistor configuration as shown in FIG. X ₁ , X _{2 .} . . Xm is a common connection line for the control gate electrodes of memory transistors, and these are the address lines Y ₁ , Y ₂ . . .
...Ym is a common connection line for the drain electrodes of the memory transistors and is referred to as a bit line.

However, such conventional memory matrices have the following drawbacks. FIG. 3 shows capacitive coupling in a memory transistor. G is a control gate electrode,
S is the source, D is the drain, C _ub is the substrate, V _CG is the control gate electrode potential, V _F is the floating gate electrode potential, Q _F is the amount of charge accumulated in the floating gate electrode,
C _fs , C _fb , C _fd , and C _cf are the capacities shown in FIG. 1, respectively. As integration becomes higher, the channel length of memory transistors is being reduced. As a result, the "lifting phenomenon" described below became a problem. In the conventional cell matrix shown in Fig. 2, when T _r11 is selected during writing, T _r21 , T _r31 ,
………T _rn1 , all V _CG are at L _OW level,
A write voltage V _r1 is applied to the drain, and writing is performed only to the memory transistor T _r11 . As mentioned above, when writing one transistor in bit line Y ₁ , other transistors in the same bit line
All T _r are in the capacitively coupled state shown in FIG.
Now, suppose that the transistor in Figure 4 is unwritten.
Since Q _F = O, V _F = C _cd /C _cf +C _fb +C _fs +C _cd・V _D =1/1+C _fs +C _cf /C _cd +C _fb /C _cd・V _D, and V _F becomes V _D Proportional. If the channel length of the memory transistor is reduced, C _fb /C _cd in the above equation
term becomes smaller, resulting in a floating gate potential of
V _F increases. When V _F rises and becomes larger than the threshold voltage V _T of the channel portion, an inversion layer is formed and a channel current I _D flows. This I _D is the “floating current” and the drain voltage that flows from it is
V _DF is determined by the channel length and the capacitance between the drain and floating gate electrodes. Furthermore, the current value increases as the drain voltage increases beyond V _DF (see Figure 5). Note that in a fully written memory transistor, V _F is low due to the charge Q _F , so the floating problem does not occur.

In a memory transistor such as a general EPROM, if the ON current is sufficient during erasing, the drain voltage V _DF at which this "floating current" flows will be lower than the voltage that should be applied to the drain during writing, so All unselected, unwritten transistors in the bit line become in a state where a "floating current" flows. Therefore, in the conventional cell matrix as shown in FIG. 2, the floating current I _D flows through the bit line in a superimposed manner equal to the number of unselected unwritten transistors in the bit line. In other words, as shown in Figure 5, 1
If the floating current in one T _r is I _Y11 , the number of memory transistors in the bit line is m, and the number of transistors written in the bit line is x, then at the time of writing, (m-1-x) x I _Y12 current will flow through the bit line. Therefore, as shown in FIG. 6, the current during writing is the sum of the writing current I _Y11 and the floating current, resulting in a large current flowing. Also, as shown above, the floating current varies depending on the number of write transistors in the bit line. Therefore, the write current changes depending on the number of write transistors in the bit line, and the write state of the transistors in the bit line differs depending on the position in the line. Also, as the number of address lines m increases, the floating current increases. Increasingly, the above drawbacks become even more problematic.

In order to solve these drawbacks, there is an example of using a circuit that biases the source side potential of the memory cell transistor only during writing, but this is because the bias potential is not constant due to variations in the transistors in the bias circuit, and the bias circuit This method cannot be said to be an appropriate method because it requires a large amount of space and has the disadvantages of slow writing speed and adversely affecting "writing".

An object of the present invention is to provide a semiconductor integrated circuit device having a memory matrix free from the above-mentioned drawbacks.

A feature of the present invention is that in a semiconductor integrated circuit device including a plurality of stacked gate field effect nonvolatile memory transistors, the drains or sources of each of the plurality of stacked gate field effect nonvolatile memory transistors are connected to each other, and the respective sources or the drains are connected to the drains or sources of insulated gate field effect transistors respectively corresponding to the memory transistors, the gates of the memory transistors are connected to the gates of the insulated gate field effect transistors corresponding to the respective memory transistors; A semiconductor integrated circuit device characterized in that the source or drain of an insulated gate field effect transistor is all grounded.

For example, the channel region is formed on a predetermined semiconductor substrate and is in contact with a channel region consisting of a source region and a drain region of the opposite conductivity type to the substrate, and the main surface of the substrate sandwiched between the source region and the drain region. a first insulating film provided to cover the surface of the floating gate electrode; a floating gate electrode formed on the insulating film to be electrically insulated from other parts; and a second insulating film formed to cover at least the surface of the floating gate electrode. In a semiconductor integrated circuit device in which at least four stacked gate MOS type nonvolatile memory transistors each having an insulating film and a control gate electrode provided in contact with the insulating film are two-dimensionally arranged, the nonvolatile The common line of the control gate electrode of the memory transistor is X ₁ ,
_{X 2 , ...... _}
The gate electrodes are the control gate electrode common connection lines X ₁ , X ₂ , . . . of the nonvolatile memory transistors.
. _{. .} A semiconductor integrated circuit device comprising at least m MOS type transistors formed in the same substrate as a memory transistor.

The present invention will be explained in detail below based on examples.

FIG. 7 shows a memory cell matrix to which the present invention is applied. The sources of all memory transistors are single-layer gate transistors T _r01 , T _r02 , ... whose gates are connected to each address line.
…Connected to ground via _Trpn . now
When writing is performed by selecting T _r11 , a write voltage is applied only to each address and bit line of X ₁ and Y ₁ . At this time, T _r01 is turned on and the source of T _r11 is grounded. However, in other memory transistors T _r21 T _rn1 in the same bit line, one layer gate transistor in each address line
T _r02 ,...T _r0n is in the OFF state, so the source is open. Therefore, the above-mentioned floating current does not flow. Therefore, the write current is equal to the write current of T _r11 , and the write current can be made smaller than that of the conventional memory cell matrix. Further, since writing is performed with the same write voltage and write current for every memory transistor in the cell matrix, there is no variation in the write level depending on the bit.

During reading, read voltages are applied to the address and bit lines, respectively. If the selected memory transistor is in the write state, it will be in the OFF state and no current will flow. Conversely, if it is in an unwritten state, the memory transistor is turned on and current flows through the single-layer gate transistor connected to the source side. Now T _r22
Consider the case where is selected. A read voltage is applied to the gates of T _r22 and T _r02 , respectively. T _r02 and T _r22
When compared, the ON resistance of T _r22 is much higher than that of T _r02 due to the high concentration of channel doping for writing and the double-layer gate structure. Therefore, the rise in the source potential of the memory transistor is small. Moreover, if the ratio of T _r01 , T _r02 ......T _rpn is made large, and the channel doping is made low concentration, the difference in ON resistance becomes even larger, and the increase in the source potential of the memory transistor can be ignored, and the readout is No deterioration of characteristics occurs compared to the matrix.

FIG. 8 shows a memory cell array designed by applying the present invention. In the case of Figure 8, Z ₁ shown in Figure 7
, Z ₂ , Z ₃ and Z ₄ , Z _2i-1 and Z _2i are used in common to achieve high density. Memory transistors 11a and 11b have floating gates 16a and 16b, respectively. 12a and 12b are single layer gate transistors between the source of the memory transistor and ground; 13a and 13b are bit lines; 14
a, 14b, 14c, 14d are address lines,
15 is a ground line. In the case of Figure 8, 1
When writing to the transistor 1a, the floating current of the memory transistor 11b flows through the transistor 12a, but the floating current for one transistor is smaller than the write current, and the improvement over the conventional example is not impaired. do not have.

FIG. 9 is a design example of a conventional memory cell array. Since FIG. 8 is exactly the same size as FIG. 9, it has the advantages of the present invention but is the same as the conventional one in terms of integration. If this design example is adopted, no problem will occur even when higher integration is achieved.

When a 64K-bit EPROM was prototyped using the cell arrays shown in FIGS. 8 and 9, the write current of the cell array to which the present invention was applied was 60% of that of the conventional cell array. Furthermore, there was little variation between bits in the writing level during writing, and the yield was about 30% better.

Although this embodiment describes an ultraviolet erasable memory transistor, the present invention is not limited thereto, and the nonvolatile memory transistor described in the claims may be an electrically erasable transistor. It doesn't matter if there is. In this case, it has the characteristics that decoding during reading can be easily performed and that the cell matrix area can be reduced.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the structure of a stacked gate MOS type semiconductor device, and FIG. 2 is a conventional cell matrix array, which has m×n bits, with X ₁ , X ₂ ,
......Xm is a common connection line (address line) for control gate electrodes, Y ₁ , Y ₂ , ...... Yn is a common connection line (bit line) for drain electrodes, T _r11 ,
T _r12 , ......, T _rn1 ......... are each memory transistor, Fig. 3 is a capacitive coupling diagram of the memory transistor, Fig. 4 is a capacitive coupling diagram of the memory transistor that is not selected during writing, Figs. 5, 6 The figure shows the write current and floating current of the memory transistor, where I _r11 is the write current of the memory transistor,
I _r12 is the floating current of one memory transistor, I _r1 is the combined current flowing through the bit line,
Fig. 7 is a circuit diagram of a cell matrix embodiment to which the present invention is applied, Fig. 8 is a diagram showing a design example of a cell matrix to which the present invention is applied, and Fig. 9 is designed to have the same size as Fig. 8. 1 is a diagram showing an example of a conventional matrix design. In the figure, 1...semiconductor substrate, 2, 3...
...Source, drain region, 4...Channel region, 5...Floating gate electrode, 6...Control gate electrode, 7...Capacitance C _fb between floating gate and substrate,
8...Capacitance between floating gate and drain region
C _fd , 9... Capacity between floating gate and source region C _fs , 10... Capacitance between floating gate and control gate C _cf , G... Control gate electrode, S...
Source, D...Drain, S _ub ...Substrate, V _CG ...
Control gate electrode potential, V _F ...Floating gate electrode potential, Q _F ... Charge accumulated in floating gate,
11a, 11b...Memory transistor, 16
a, 16b... floating gate, 12a, 12b...
MOS type transistors, 13a, 13b...Bit line, 14a, 14b, 14c, 14d...
Address line 15 . . . ground line.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device including a plurality of nonvolatile memory transistors, a selection signal is supplied to each memory transistor between one end of each of the plurality of nonvolatile memory transistors connected in parallel to a write line and a constant potential supply end. 1. A semiconductor integrated circuit device comprising a switching transistor that is turned on by a signal.