JP2697638B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor device having a floating gate electrode such as a flash memory.

[0002]

2. Description of the Related Art A non-volatile semiconductor device having a floating gate electrode such as a flash memory has a high potential for non-volatility, low power consumption, high integration, and low cost per bit.
Prospects are expected as replacement candidates for magnetic storage media such as hard disks and floppy disks.

Each memory cell of this type of nonvolatile semiconductor memory device is composed of one memory cell transistor, and each transistor is formed on a P-type silicon substrate 301 as shown in FIG. Oxide film 302 formed by thin film forming technology using photolithography technology and dry etching technology for thin film, and floating gate 303 made of polycrystalline silicon
, An interlayer insulating film 304, a polycrystalline silicon two-layer gate including a polycrystalline silicon control gate 305, a source diffusion layer 307 formed using a phosphorus or arsenic ion implantation technique or the like, and a drain diffusion layer 306. It is composed of

The floating gate 303 is a gate for changing the threshold value of the memory cell transistor as viewed from the control gate 305. When hot electrons are accumulated in the floating gate 303, a positive potential applied to the control gate 305 is provided. Is canceled out by the hot electrons accumulated in the floating gate 303, so that the threshold value of the memory cell transistor as viewed from the control gate 305 is higher than in a state where hot electrons are not accumulated.

The injection of hot electrons into the floating gate 303 is performed by applying 10 V, 5 V, and 0 V to the control gate 305, the drain 306, and the source 307, respectively. As a result, some of the electrons moving through the channel of the memory cell transistor reach the floating gate 303 through the tunnel oxide film 302 and are accumulated. The state in which hot electrons are accumulated in the floating gate 303 is referred to as a data write state. Conversely, hot electrons can be discharged from the floating gate 303 by setting the drain 306 to an electrically open state (floating state), and
V, by applying -16 V to the control gate 305. As a result, the tunnel oxide film 302 in the overlap region between the source diffusion layer 307 and the floating gate 303 is formed.
Fowler-Nheim (Fowl)
er Nordheim) current is generated, and electrons are removed from the floating gate 103 via the tunnel oxide film 102. Thus, a state where hot electrons are not accumulated in the floating gate 303 is defined as a data erase state.

The data is read out from the control gate 3
05, 5 for drain 306 and source 307, respectively.
V, 1 V and 0 V are applied. At this time, if the memory cell transistor is in a write state, that is, a state in which hot electrons are accumulated in the floating gate 303, the voltage of 5 V applied to the control gate 305 is canceled by the hot electrons, so that the memory cell transistor is turned on. And the memory cell transistor is in the erased state, that is, the floating gate 3
If no hot extron is stored in the memory cell 03, the memory cell transistor is turned on by the voltage applied to the control gate 305. Therefore, by detecting such conduction / non-conduction, data is read from the memory cell transistor.

FIG. 5 shows an example of a conventional nonvolatile semiconductor memory device. For the sake of convenience, the nonvolatile semiconductor memory device shown in this figure has blocks 401 and 402 obtained by dividing memory cells M11 to M43 arranged in a matrix of 4 rows and 3 columns in units of batch erasure of data, and memory cells M11 and M11. M2
1, M31, M41 and memory cells M12, M22, M3
2, M42 and memory cells MM13, M23, M3
3, bit lines B1 to B3 commonly connected to the respective drain electrodes of M43 and M43, and memory cells M11 and M1.
2, M13, memory cells M21, M22, M23, memory cells M31, M32, M33 and memory cell M4
1, word lines W1 to W4 commonly connected to control gate electrodes of memory cells M1, M42 and M43, respectively.
1, M12, M13 and memory cells M21, M22, M2
3, the source lines S1 to S4 commonly connected to the source electrodes of the memory cells M31, M32, M33 and the memory cells M41, M42, M43, respectively, and the column address AC decoded in response to the write control signal C. A column selection circuit 403 for controlling selection of any one of the lines B1 to B3;
Row decoder 404 for controlling selection of any one of 1 to W4, and source line control for controlling the voltages of source lines S1, S2 and S3, S4 of blocks 1 and 2 corresponding to writing and erasing, respectively. And a circuit 405.

Next, the operation will be described. At the time of writing to the memory cell M11 to be written, 10V, 5V and 0V are applied to the word line W1, the bit line B1, and the source line S1 connected to the memory cell M11. The other word lines W2 to W4 and the other source lines S2 to S4 are set to 0V, and the other bit lines B2 and B3 are set to the open state.

As a result, 10 V, 5 V and 0 V are applied to the control gate, drain and source of the memory cell transistor M11 to be written, respectively, so that hot electrons are injected into the floating gate of the memory cell transistor M11. That is, writing is performed.

[0010]

However, if the memory cell transistors M21, M31 or M41 which share the bit line with the memory cell M11 to be written among the memory cell transistors not to be written are already in the written state. , Memory cell transistor M1
At the time of writing process 1, since a voltage is applied to the drain diffusion layer by the bit line B1, a strong electric field is generated between the floating gate in which electrons are accumulated and the drain diffusion layer.

The electric field bends the energy band in the overlap region between the floating gate and the drain diffusion layer,
Of the electron-hole pairs generated by this, a drain disturb phenomenon occurs in which electrons are injected into the drain diffusion layer and holes are injected into the floating gate. (Aniban Roy, 1992, 30th Reliability Physics Annual Proceedings (ReliabilityPhysics)
30th annual Proceedings) pages 68-75). When the drain disturb phenomenon occurs, the amount of charge stored in the floating gate changes, so that data changes from a written state to an erased state.

As described above, the memory cell transistor in the written state is subjected to the drain disturb phenomenon every time data is written to the memory cell transistor having a common bit line. It is represented by the number of times of data writing to the memory cell transistor on the common bit line × the data writing time. However, since the number of times data of the memory cell transistor on the common bit line is actually rewritten is about 100,000 to 1,000,000 times,
It is impossible to hold write data.

The suppression of the drain disturbance can be realized by setting the voltage applied to the bit line B1 for driving the memory cell transistor M11 to be lower than 5V. Further, by optimizing the drain structure, it is possible to improve the drain disturb resistance of the memory cell while maintaining the data write speed (Akinori Kodama, Technical Digest of International Electron Device Meeting (Tec)
hnickal Digest of Internet
ionical Electron Devices Me
et al., 1991, pp. 30-306).

However, when the voltage applied to the bit line B1 for driving the memory cell transistor M11 is set low, for example, at 4 V in order to suppress the drain disturbance, the data writing speed to the memory cell transistor M11 is reduced by the applied voltage of the bit B1. Is about one order of magnitude slower than in the case of 5V, and the writing efficiency is significantly reduced.

When the drain structure is optimized for the purpose of suppressing the drain disturbance, the drain structure becomes very complicated, that is, the manufacturing process becomes complicated and long.

Accordingly, it is an object of the present invention to reduce the voltage applied to the bit line at the time of writing and to make the memory cell transistor a complicated structure.
Here, the drain disturb phenomenon is suppressed, and thereby the write data is reliably held.

[0017]

According to the nonvolatile semiconductor memory device of the present invention, at the time of writing, the voltage of a word line other than the word line corresponding to the memory cell transistor to be written is changed to the word corresponding to the memory cell transistor. Means are provided for setting the voltage of a word line other than the line lower than the threshold voltage of the memory cell transistor and higher than the source voltage of the memory cell transistor to be written.

[0018]

Therefore, even if another memory cell transistor sharing a bit line with a memory cell transistor to be written is in a write state, the above-mentioned voltage is applied to the control gate of the other memory cell transistor. The electric field generated between the floating gate and the drain diffusion layer is reduced by the capacitive coupling with the floating gate of the other memory cell transistor. As a result, the drain disturb phenomenon is less likely to occur.

[0019]

1 shows an entire nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIG. 2 shows details of a cell array region. Nonvolatile semiconductor memory device 100 according to the present embodiment
As shown in FIG. 1, a cell array region 101 composed of a plurality of memory cell transistors each having a floating gate, a row decoder 103 that decodes a row address AR and selects one of a plurality of word lines, and a column address AC A column decoder 104 for decoding and selecting one of the plurality of column selection lines and a row address AR
Has a source line control circuit 105 that decodes an address AR ′, which is a part of the above, and controls the potentials of a plurality of source lines, a power supply voltage (V _PP , V _CC , V _SS ), a chip enable signal (CE), It has a control circuit 107 that receives the output enable signal (OE) and the erase signal (EE) and generates various control signals and write power supply voltages V1 and V2. The cell array region 101 is composed of memory cell transistors arranged in a matrix of x × (i + 1) rows × (y + 1) × (m + 1) columns as shown in FIG. That is, each word line is commonly connected to the control gates of (y + 1) × (m + 1) memory cell transistors, and each bit line is connected to the drain diffusion layer of xx (i + 1) memory cell transistors. Connected in common. In addition, the cell array region 101 is composed of a memory cell transistor group connected to x word lines as one unit, and i + 1
Blocks 101-0 to 101-i, and the source potentials of the memory cell transistors in each block are collectively controlled by corresponding source lines. As a result, the data written in the memory cell transistor is erased collectively in block units.

Further, the nonvolatile semiconductor memory device 100 includes:
The control circuit 107 distinguishes between writing, reading and erasing.
Are distinguished by detecting the voltage of the power supply voltage (V _PP ), the logic levels of the chip enable signal (CE), the output enable signal (OE), and the erase signal (EE). It is the power supply voltage (V _PP ) high voltage (12 V) that instructs the write operation, the chip enable signal (CE) is active, and the output enable signal (OE) and the erase signal (EE) are inactive. Is the case. When a write operation is instructed under the above conditions, the control circuit 107 sets the write control signal C to a high level and sets the voltages to 2 V and 1 V, respectively.
It generates write power supply voltages V1 and V2 of 0V. Note that the control circuit 107 sets the erase control signal E to a high level when the erase operation is instructed.

The nonvolatile semiconductor memory device according to the present embodiment is characterized by the operations of the row decoder 103 and the source line control circuit 105 at the time of a write operation, and the read operation and the erase operation perform known operations. Hereinafter, the operation at the time of writing will be described.

During a write operation, the row decoder 103
That is, the write control signal C, the write power supply voltage V1,
When V2 is supplied, the address buffer 10
2. The row address AR supplied from 2 is decoded, and the potential V1 is supplied to the word line. In addition, the column decoder 1
Reference numeral 06 decodes the column address AC supplied from the address buffer 102, selects one of the plurality of column selection lines, and sets the selected column selection line to the active level. On the other hand, when the write control signal C is supplied, the source line control circuit 105 decodes a part of the row address supplied from the address buffer 102 into AR ′, and outputs one of the source lines S0 to Si. Line to the V _SS potential,
Supply the _Vcc potential to the remaining source lines. When the write control signal C is supplied, the write circuit 106 outputs the tristate buffers 110-0 to 110-110.
Based on the write data supplied via m, the output corresponding to the bit to be written is set to the _Vcc potential, and the output corresponding to the bit not to be written is set to the high impedance. 109-0 to 109-m are sense amplifiers and tri-state buffers used at the time of reading.

Next, the memory cell transistors M0-00
A specific write operation will be described with an example where M1 and M1-00 are written. As shown, the memory cell transistor M0-00 is connected to the word line W0 and the bit line B0.
0, and the memory cell transistor M1-00 is a memory cell connected to the word line W1 and the bit line B00. First, in order to write data to the memory cell transistors M0-00, the row decoder 10 is controlled based on the address from the address buffer 102.
3. Column decoder 104 and source line control circuit 10
5, the word line W0, the bit line B00,
The source lines select S0 respectively. Therefore, the word line W0 has the potential V2, ie, 10V, and the other word lines have the potential V1, ie, 2V. The bit line B00 is at the VCC potential, that is, 5V, and the other bit lines are in a floating state. The source line S0 has the VSS potential, that is, 0V, and the other source lines have the _Vcc potential, that is, 5V. As a result, the potentials of the control gate, the drain diffusion layer and the source diffusion layer of the memory cell transistor M0-00 are 10V and 5V, respectively.
V and 0 V are written. At this time, the potentials of the control gate, drain diffusion layer and source diffusion layer of the memory cell transistor M1-00 having a common bit line are 2V, 5V and 0V, respectively. Next, in order to write to the memory cell transistor M1-00, the word line is W1, the bit line is B00, and the source line is S0.
Select each. Therefore, word line W1 is connected to V2
Potential, ie, 10 V, and the other word lines are at V1
Potential, that is, 2V. The bit line B00 is at V
_It becomes the _CC potential, that is, 5 V, and the other bit lines are in a floating state. The source line S0 has the V _SS potential, that is, 0 V, and the other source lines have the V _CC potential, that is, 5 V. Thereby, the potentials of the control gate, the drain diffusion layer and the source diffusion layer of memory cell transistor M1-00 are 10V, 5V and 0V, respectively.
V is written. At this time, the memory cell transistor M having a common bit line and
The potentials of the control gate, the drain diffusion layer and the source diffusion layer of 0-00 are 2V, 5V and 0V, respectively. Focusing on such memory cell transistors M0-00,
Since hot electrons are injected into the floating gate, the potential of the floating gate is usually about -2.5 V. However, when a potential of 2 V is applied to the control gate as described above, the capacitance between the control gate and the floating gate is increased. Due to the coupling, the potential of the floating gate decreases only while the potential is applied to the control gate, and becomes about -1V. Therefore, the potential of the floating gate and
Electric field generated between the drain diffusion layer potential of 5V is applied, it is greatly relaxed as compared with the case where the control gate not applied potential of 2V.

Here, the threshold value of the memory cell transistor in the written state becomes 8 due to the drain disturb phenomenon.
The time until the voltage changes from V to 7 V is defined as the drain disturb resistance, and FIG. 3 shows an example of the drain disturb resistance of the memory cell transistor when a positive low voltage is applied to the control gate. Indicates that the control gate voltage connected to the word line is 1
Each time V increases, it is improved by about one digit. That is, by applying 2 V to the word line corresponding to the memory cell to be non-written, the drain disturb resistance can be improved by about two digits.

Therefore, while performing normal writing to the memory cell transistor M1-00 to be written,
Memory cell transistor M0 already in the written state
The write data of -00 is not performed.

In addition, of the memory cell transistors M1-00 to be written and the memory cell transistors having a common bit line, the block 101-
1 to 101-i, for example, the memory cell transistor M (x + 1) -00 includes source lines S1 to S1 corresponding to blocks 101-1 to 101-i which are not to be written.
Since all the potentials of Si are 5 V, the potentials of the source and the drain become equal, and no channel current occurs.

In this embodiment, the potential of the unselected word line is set at 2 V. This is because the potential applied to the control gate can be increased to improve the drain disturb resistance, but the potential is too high. , There is a possibility that the memory cell transistor in the erased state may be turned on. In such a case, it is considered that the power consumption is increased. There is no possibility that the transistor is turned on, and the drain disturb phenomenon can be effectively suppressed.

As another embodiment of the present invention, among the word lines of the block including the memory cell transistor to be written, the potential of the word lines other than the word line corresponding to the memory cell transistor to be written is set to 0 V, The word line potential of a block that does not include a memory cell transistor to be written to can be 2 V. In this case, among the memory cell transistors in the block including the memory cell transistor to be written, the potentials applied to the control gate, the drain diffusion layer, and the source diffusion layer of the memory cell transistor that shares a bit line with the memory cell transistor to be written. Are 0 V, 5 V and 0 V, respectively, so that the channel current caused by the potential difference between the source and the drain can be almost zero. In the present embodiment, among the memory cell transistors in the block including the memory cell transistor to be written, the memory cell transistor sharing the bit line with the memory cell transistor to be written is affected by the drain disturb phenomenon. According to the present invention, since the source lines are controlled collectively for each block, the memory cell transistors affected by the drain disturb phenomenon are limited to the memory cell transistors in one block as described above, and the influence is small. That is, the time during which the drain disturb phenomenon occurs is shortened in inverse proportion to the number of blocks, so that the influence of the drain disturb phenomenon can be minimized.

Although a silicon film is used as a semiconductor film constituting a memory cell transistor, a silicon oxide film is used as an insulating film, and a silicon substrate is used as a semiconductor substrate, other types of semiconductor films and semiconductor substrate materials may be used. A silicon nitride film, a phosphorus glass film, or a silicon oxynitride film may be used as the insulating film. Although a memory cell having a floating gate is used as a memory cell, another type of memory cell may be used. In addition, 10 V, 5 V, and 2 V are used as the supply potential of each electrode of the memory cell.
Other suitable potentials may be supplied.

That is, the potential supplied to the non-selected word lines is set to 2 V. However, if it is particularly required to suppress the drain disturb phenomenon rather than to reduce the power consumption, the potential may be set higher than 2 V. Conversely, if the reduction of power consumption is the highest priority, it may be lower than 2V. That is, it can be conveniently set within the range from the _Vss potential to the _Vcc potential.

[0031]

As described above, in the nonvolatile semiconductor memory device of the present invention, at the time of writing, the floating gate of another memory cell transistor sharing a bit line with the memory cell transistor to be written is accumulated. There is no reduction in stored charge and no increase in power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a cell array region in detail.

FIG. 3 is a characteristic diagram showing an example of improvement in drake disturb resistance of the embodiment.

FIG. 4 is a schematic sectional view of a memory cell transistor of the nonvolatile semiconductor memory device.

FIG. 5 is a block diagram showing an example of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 100 nonvolatile semiconductor memory device 101 cell array region 101-0 to 101-i block 103 row decoder 104 column decoder 105 source line control circuit 106 write circuit 107 control circuit M memory cell transistor W word line B bit line S source line C write control signal

Claims (4)

(57) [Claims] An a word line, a b bit line, a set of source lines corresponding to the word lines one-to-one, and a common connection; a word line and the bit line; C memory blocks each including a × b memory cell transistors disposed at the intersection of the above, a row decoder for selecting one word line based on a row address, and one bit line based on a column address. And a source line control circuit for selecting a set of source lines based on a part of the row address. Each of the memory cell transistors has a floating gate and a control gate connected to a corresponding word line. An electrode, a drain electrode connected to a corresponding bit line, and a source electrode connected to a corresponding source line.
At the time of the write operation, the first voltage is supplied to the selected one word line, and the second voltage lower than the first voltage is supplied to the other word lines. A nonvolatile semiconductor memory device in which a third voltage lower than the second voltage is supplied to one set of source lines, and voltages of other source lines are made equal to voltages of bit lines selected by the column decoder. 2. The method according to claim 1, wherein the row decoder applies the first voltage to a selected one word line during a write operation, and applies the third voltage to an unselected word line in a block including the selected word line. 3. The nonvolatile semiconductor memory device according to claim 2, wherein the second voltage is supplied to other word lines. 3. A plurality of word lines, a plurality of bit lines orthogonal to the plurality of word lines, a plurality of source lines arranged in parallel with the plurality of word lines, a floating gate, and a control gate electrode, respectively. , Comprising a drain electrode and a source electrode, arranged at intersections of the plurality of word lines and the plurality of bit lines, a corresponding word line is connected to each control gate electrode, and a corresponding drain electrode is provided. And a corresponding source line is connected to each source electrode. In a write state, the threshold voltage is a fourth voltage, and in an erase state, the threshold voltage is the fourth voltage. 5th lower than voltage
A plurality of memory cell transistors is a voltage, the memory
A plurality of cells are arranged in a matrix, and
In, the source lines were connected so that they were electrically at the same potential
A memory block and, when a request to write data to the memory cell transistor is detected, a control signal set to an active level, and a sixth voltage higher than the fourth voltage and a seventh voltage lower than the fifth voltage first means for generating said control signal, receiving said sixth voltage and the seventh voltage, the word line selected and the control signal based on the input address is an active level 6 A second means for supplying a seventh voltage to the other word lines; and a second means for receiving the control signal and applying a voltage lower than the fourth voltage to a bit line selected based on an input address. supplying a high voltage eighth than 5 voltage, and a third means for the high impedance state the other bit line, based on an input address receiving said control signal It is connected to the-option memory block
A ninth voltage lower than the seventh voltage to the source line,
A fourth means for supplying the sixth voltage to source lines connected to other memory blocks . 4. The sixth voltage is 10V, and the sixth voltage is
7 is 2V, the eighth voltage is 5V,
4. The nonvolatile semiconductor memory device according to claim 3 , wherein said ninth voltage is 0V.