JPS5828875A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate ununiformity of writing levels different by bits by a method wherein, in a semiconductor integrated circuit including nonvolatile-memory transistors which have floating gate terminals respectively, writing can be performed on the same writing voltage and writing current for any memory transistor in cell matrices as well as electric current for writing is maintained at a lower value. CONSTITUTION:Common interconnection lines X1, X2...Xm are provided for the control gate terminals of nonvolatile-memory transistors; common interconnection lines Y1, Y2...Ym for the drain terminals of the same; and common interconnection lines Z1, Z2...Zm for the source terminals of the same. The gate terminals are connected to one of the common interconnection lines X1, X2...Xm for the control gate terminals of the said nonvolatile-memory transistors; the drain regions are connected to at least one of the common interconnection lines Z1, Z2...Zm for the source terminals of the said nonvolatile-memory transistors, and the source regions are provided with at least m units of MOS transistors which are formed on the same wafer as the said grounded nonvolatile-memory transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including all nonvolatile memory transistors having floating gate electrodes.

In recent years, MO8 type semiconductor devices with floating gate electrodes have been used as non-volatile memory elements, and in particular, ultraviolet erasable non-volatile memory IJ-(EFROM) has become widely popular due to its simple structure, with large capacity and high integration. There is.

A cross-sectional view of the structure of this element is shown in FIG. 1 is a semiconductor substrate, 2 and 3 are source/drain regions, and 4 is a channel region doped with impurities and has a threshold value VT.

5 is a floating gate electrode, 6 is a control gate electrode, 7 is a capacitance between the floating gate 5 and the substrate 1 (hereinafter referred to as Cfb), 8 is a capacitance between the floating gate 5 and the drain region 2 (hereinafter referred to as Cfd), 9 is a floating gate 5 and source region 3 (hereinafter referred to as Cf5),
10 is the capacitance between the floating gate 5 and the control gate 6 (hereinafter referred to as
Cof). This memory element injects the λ stone energy carriers generated in the channel into the floating gate electrode 5 to perform "one-win injection", retains memory, and excites the accumulated charge energetically by total ultraviolet radiation. The charge is discharged to the substrate 1 and the control gate electrode 6, and 7 erasing is performed. After the charge is released, the memory cell transistor becomes equal to the threshold value before writing, and 6 erasing is completed. Therefore, in an N-channel transistor, if the threshold voltage before writing is set positive, the threshold voltage of the memory transistor changes only within the range of positive values.

Therefore, when a cell array is constructed using this memory cell transistor, a memory matrix can be conventionally constructed with a 1 bit-1 transistor configuration as shown in FIG. XI, X2...Xm are the common connection lines for the control gate electrodes and poles of the memory transistors, and these are all bit lines. Line.

However, in such a conventional memory matrix (ri), it has the following deficiencies:
The figure shows capacitive coupling in a memory transistor. () is the control gate Yoi 1 (Hama).

S is the source, D is the drain, Sub is the substrate I, VOG is the control gate electrode potential, and ■F is the floating gate electrode potential t.
Qp is the charge Mle ” accumulated in the floating gate electrode
f S, C, fb, Cf 'L "f is the first
The capacity [d] shown in the figure is .Due to increased integration, the channel length of memory transistors has been reduced.

As a result, the phenomenon of "1 rising" described below has become a problem.In the conventional cell matrix shown in FIG. 2, when Trll'e is selected at the time of writing, T, 2, Tr31.
...Trml are all ■. 0 gari. The level becomes W level, a write pressure ■r1 is applied to the drain, and writing is performed only in the memory transistor Tr1□. '% to one transistor in bit line ¥1 as above
When the bit line is loaded with f, all other transistors in the same bit line are in a capacitively coupled state as shown in FIG. Now, if the transistor in FIG. 4 is unwritten, QF=0, so = 3- and is proportional to V and UV. When the channel length of the memory transistor is reduced, the CJI〆Ccd term in the above equation becomes smaller, and as a result, the floating game voltage VF increases. When (2) increases to a value greater than the threshold voltage (1) of the channel portion, an inversion layer is formed and a channel current (2) flows. This ID is a floating current, and its flow and output drain voltage VDF are determined by the capacitance between the channel ridge and the drain floating gate electrode. Also, the current value increases as the drain voltage increases beyond VrlF. (See FIG. 5). Note that in the case of a sufficiently written memo I] + transistor, the problem of floating does not occur because the charge QF lowers ■.

In a memory transistor such as a general EFROM,
If a sufficient ON current is used during erasing, this floating current will flow out of the drain, and the voltage DF will be lower than the voltage that should be applied to the drain at the appropriate time. All the built-in transistors are in a state where 6" floating current flows.

Therefore, the conventional cell matrix 4 as shown in Figure 2
- In the bit line, the floating y7 stream ID is superimposed by the number of unselected unwritten transistors in the bit line and flows through the bit line. One T1. If the floating current kI711 is the number of memory transistors in the bit line f m and the number of transistors written in the bit line is kX, then when writing (m-1-X)
A current of XIY12 will flow through the bit line.

Therefore, as shown in FIG. 6, the current at the time of writing is the sum of the write current Y1 and the floating current, resulting in a large current flowing. Also, as shown above, the floating current varies depending on the number of write transistors in the bit line. Therefore, the current during writing changes depending on the number of write transistors in the bit line, and the write state of the transistors in the bit line differs depending on the position in the line.
As the number m of address lines increases, the floating current increases and the above-mentioned drawbacks become even more problematic.

In order to solve these drawbacks, there is an example of using a circuit that applies bias only when the source side potential of the memory cell transistor is fully written, but this is because the bias is not constant due to variations in the transistors in the via circuit. This method has disadvantages such as the need for space outside the bias circuit, the slow writing speed, and the negative effects of ``writing'', so it cannot be said to be a suitable method.

SUMMARY OF THE INVENTION The object of the present invention is to provide a complete half-quadruple Toshiba circuit arrangement with a memory matrix that does not have the drawbacks mentioned above.

A feature of the present invention is that in a semiconductor integrated circuit device including a plurality of stacked gate field effect nonvolatile memory transistors, the drains or sources of each of the plurality of stacked gate field effect nonvolatile memory transistors are connected to each other. , each source or drain is connected to the drain or source of an insulated gate field effect transistor corresponding to the memory transistor, respectively, and the gate of the memory transistor is connected to the respective '/-1(-
The corresponding insulated gate field effect transistor is connected to the gate of the insulated gate field effect transistor. - A semiconductor integrated circuit device characterized in that the sources or drains of transistors are all grounded.

For example, the channel region is formed on a predetermined semiconductor substrate and is in contact with a channel region consisting of a source region and a drain region of the opposite conductivity type to the substrate, and the main surface of the substrate sandwiched between the source region and the drain region. a first insulating film provided to cover the surface of the floating gate electrode; a floating gate electrode formed on the insulating film to be electrically insulated from other parts; and a second insulating film formed to cover at least the surface of the floating gate electrode. A stacked gate comprising an insulating film and a control gate electrode provided in contact with the insulating film.
In the dimensionally arranged semiconductor integrated circuit device, a common line iX1 . of the control gate electrodes of the nonvolatile memory transistors. X2゜...Xm, the common connection line of the drain region is Y1, Y2゜...Y
n, a common connection line of the source electrodes as Zl, Z2°...Zm, and a gate electrode that is a common absorption line of the control gate electrodes of the nonvolatile memory transistors Xi, X2. .・・−
... a semi-2JY integrated circuit comprising at least 14 M08 type transistors formed in the same substrate as said non-volatile memory transistor connected to at least one of Zm and whose source region is grounded. It is a device.

The present invention will be explained in detail below based on all the embodiments.

FIG. 7 shows a memory cell matrix to which the present invention is applied. The sources of all memory transistors are single-layer gated transistors Tro1 . . . whose gates are connected to each address line. Tr02. . . . It is connected to the ground via Trom. When writing is performed by selecting Tr11, the write voltage is applied only to each address and bit line of Xl and Yl. At this time Tr
ol is turned on, and the source of Trl is grounded. However, in the other memory transistors Tr2□9-'I''r+ in the same bit line, the single-layer gate transistor Tr02...TrOm of each address line is OFF.
state, so the source is open. Therefore, the above-mentioned floating current does not flow. Therefore, the write current is equal to the write current of Trll, and it is possible to reduce the single write current compared to the conventional memory cell matrix. Also, the same write voltage is used for the memory transistors in the cell matrix and memory.

Since writing is performed using the write current, there is no variation in the write level depending on the bit.

When removing the bladder, full pressure is applied to the address and bit lines, respectively. If the selected memory transistor is not in the write state, it is in the OFF state, so no current flows. Conversely, in an unwritten state, the memory transistor is turned on, and current flows through the single-layer gate transistor connected to the source side. Now consider the case where Tr2□ is selected. Tr2
A read voltage is applied to the gates of □ and Tr02, respectively. When comparing Tr02 and TrZ□, the ON resistance of T,2□ is much higher than that of Tro2 due to the high concentration of channel doping for writing and the two-layer 10-gate structure. Therefore, the rise in the source potential of the memory transistor is small. Again, “roll.

T. 2...If the ratio of Trom is made large, the difference in ON resistance becomes even larger if the channel doping is made low concentration, and the rise in the source potential of the memory transistor is ignored. In comparison, deterioration of characteristics is less likely to occur.

FIG. 8 shows a memory cell array prepared by fully applying the present invention. In the case of FIG. 8, Zl and Z2. shown in FIG. Za
and Z4. ...Z2□-1 and Z2i are used in common to achieve high density. lla, 1ll) are memory transistors having floating gates) 16a, 16bi, respectively. 12a, 12b are single-layer gate transistors between the source of the memory transistor and ground; 13a, 13b;
is the bit line, 14a.

14b, 14c, and 14d are address lines, and 15 is a ground line. In the case shown in FIG. 8, when writing to the transistor 11a, the floating current of the memory transistor llb flows through all the transistors 12H.
The floating ttr current for one transistor is smaller than the write current, and W (improvement from the conventional example) is not impaired.

FIG. 9 is a design example of a conventional memory cell array. Since FIG. 8 is exactly the same size as FIG. 9, it has the advantages of the present invention but is the same as the conventional one in terms of integration. If all of this design example is adopted, no problem will occur even if all of the designs are highly integrated.

By adopting the cell arrays shown in Figures 8 and 9 respectively, 64cm
(When a bit EPROM'e was prototyped, the write current of the cell array to which the present invention was applied was 60 lines compared to that of the conventional cell array.

Furthermore, there was little variation between bits in the 6-program level during writing, and the yield was about 30% advantageous.

Although this embodiment describes an ultraviolet erasable memory transistor, the present invention is not limited thereto, and the nonvolatile memory transistor described in the claims may be an electrically erasable transistor. It doesn't matter if there is. In this case, it has the characteristics that it can be easily decoded when the bladder is removed, and that the area of the cell matrix can be reduced.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the structure of an MO8 type semiconductor device, and Figure 2 is a conventional cell matrix array.
It has all n bits, Xl, X2゜...X
m is a common connection line (address line) of control gate electrodes, Yl, Y2. ...Yn is the common connection line (bit line) of the drain electrode, +ll, 1□. T . . . , T . . . are each memory transistor, r t 2. rmt Figure 3 is a capacitive coupling diagram of a memory transistor, Figure 4 is a capacitive coupling diagram of a memory transistor that is not selected during writing, and Figures 5 and 6 are diagrams showing the write current and floating current of the memory transistor. So, Irl□ is the memory transistor blind i'11. Current # Ir 1□ is the floating current for one memory transistor. Ir1 is a combined bit line current current, FIG. 7 is a circuit diagram of a 13th implementation example of Selma Merix to which the present invention is applied, and FIG. 8 is a diagram showing a design example of a cell matrix to which the present invention is applied. FIG. 9 is a diagram showing an example of a conventional matrix design designed to have the same size as FIG. 8. In the figure, 1... semiconductor substrate, 2, 3... source, drain region, 4... channel region, 5...
...Floating gate electrode, 6...Control gate electrode, 7...Capacitance Cf between floating gate and substrate
b1... Capacitance Cfd between floating gate and drain region, 9... Capacitance Cf between floating gate and source region 8.10... Floating gate and control use Capacitance between gate C3f1G... Control gate electrode, S... Source, D...
Drain, Sub...Substrate%VOG...
・Control gate electrode potential, V2...Floating gate electrode potential, QP...Charge accumulated in floating gate % 11a, Ilb...Memory transistor, 16a , 16b...Floating gate, 12
a, 12b...MO8 type transistor% 1
3a, 13b...Bit line % 14a. 14b, 14C, 14d...Address line,
15...14-1.・The Grand Line. -15- Atsushi 3 Figure Y A y Y3351- Yu 4 Figure 8a157.3B h U Kasumiyu 9 Mouth

Claims (1)

[Claims] In a semiconductor integrated circuit device including a plurality of stacked-gate field-effect nonvolatile memory transistors, the drains or sources of the plurality of stacked-gate field-effect wall-effect nonvolatile memory transistors are connected to each other, and the respective sources or drains are connected to each other. are respectively connected to the drains or sources of insulated gate field effect transistors corresponding to said memory transistors, and the gates of said memory transistors are connected to the gates of said respective corresponding insulated gate field effect transistors. The source of an insulated gate field effect transistor''!
A semiconductor integrated circuit device characterized in that all drains are grounded.