JPH0149024B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device having a floating gate structure and in which data can be electrically rewritten.

[Technical background of the invention and its problems] Data erasable read-only memory (EPROM), which uses a MOS transistor with two gates, a floating gate and a control gate, as a memory cell has been well known for a long time. It is being FIG. 3 is a pattern plan view of one memory cell of a conventional EPROM, and FIG. 4 is a cross-sectional view taken along line a-a'. A drain region 11 and a source region 12 are formed separately in semiconductor substrate 10 . A floating gate 14 is provided on the channel region 13 of the substrate 10 with an insulating film interposed therebetween.
Further, a control gate 15 is provided on the floating gate 14 with an insulating film interposed therebetween.

In a memory cell with such a configuration, when writing data, a high voltage is applied to the control gate 15 and the drain region 11, and at this time, impact ionization occurs near the drain region 11. This is performed by injecting hot electrons into the floating gate 14 and setting the floating gate 14 to a negative potential. At this time, the threshold voltage of this memory cell has increased from its original value. On the other hand, erasing data from a memory cell into which electrons have been injected and data has been written is performed by emitting electrons from the floating gate 14 and returning the potential of the floating gate 14 to its original neutral state. and floating gate 14
There are two methods for removing electrons from the light: irradiation with ultraviolet rays and application of a high voltage to the control gate 15. In the method of irradiating ultraviolet rays, sufficient energy is given to the electrons in the floating gate 14 to cross the insulating film by irradiating the ultraviolet rays,
The electrons injected into the floating gate 14 are transferred to the control gate 1
5 and substrate 10. In the method of applying a high voltage to the control gate 15, by applying a high voltage, electrons in the floating gate 14 are removed by moving them to the control gate 15 through a tunnel current.

When erasing data, the former method takes time to return the floating gate 14 to a neutral state, while the latter method can be erased in a relatively short time, but has problems in controllability. When injecting electrons into the floating gate 14, the floating gate 14
It is necessary to strengthen the electric field between the floating gate 14 and the channel region 13 to make it easier for electrons to be injected into the floating gate 14, and when emitting electrons, it is necessary to strengthen the electric field between the floating gate 14 and the control gate 15. There is.
Therefore, it is extremely difficult to satisfy both requirements at the same time.

Therefore, the present applicant invented a memory cell in which data can be easily written and erased in Japanese Patent Application No. 145195/1982. A plan view of the pattern of this memory cell is shown in FIG. 5, and a cross-sectional view taken along line bb' in FIG. 5 is shown in FIG. 6, respectively. In this memory cell, another control gate 16 is provided on the floating gate 14 of the memory cell shown in FIG. 3 with an insulating film interposed therebetween.

In this memory cell, writing data is as follows:
By applying a high voltage to each of the drain region 11, the control gate 15, and another newly provided control gate 16, hot electrons are generated by impact ionization in the vicinity of the drain region 11 in the same manner as described above. , by injecting these electrons into the floating gate 14. On the other hand, to erase data, the drain region 11 and one control gate 15 are set to a low potential, for example, ground potential, and the other control gate 16 is set to a high potential, and electrons are transferred from the floating gate 14 to the control gate 16 by field emission. Let it be released. During data writing, the floating gate 14 is raised to a sufficiently high potential due to capacitive coupling with the two control gates 15 and 16, so the electric field between the floating gate 14 and the channel becomes strong, and the drain region 11 and one control gate 15 are set to ground potential, and only the other control gate 16 is set to high potential, so the electric field between the floating gate 14 and the control gate 16 becomes stronger, and data can be easily erased. It is something.

By the way, erasing of data in a memory cell having the configuration as shown in FIG. 5 is performed by emitting electrons from the floating gate 14 to the control gate 16 by field emission as described above. For this reason,
If too many electrons are emitted from the floating gate 14, the floating gate 14 may become positively charged, and the memory cell may become a depletion type transistor. That is, two control gates 15, 16
Even if both are set to ground potential, drain region 1
A current flows through the channel region 13 between the source region 1 and the source region 12 . Therefore, when a memory cell array is configured using a plurality of memory cells, a specific memory cell cannot be selected and data cannot be read. Therefore, in a memory using a memory cell as shown in FIG. 5, it is necessary to be careful about excessive emission of electrons from the floating gate, and there is a disadvantage that the data erasure margin is narrow.

Therefore, the following memory cells have been developed in the past.

FIG. 7 is a pattern plan view of a conventional memory cell provided with means for preventing over-emission of electrons from the floating gate 14, and FIG. 8 is a cross-sectional view taken along line c-c' in FIG. It is. In this memory cell, an offset gate portion is formed between the source region 12 and the floating gate 14 by extending a portion of the control gate 15. By providing the offset gate portion in this manner, even if electrons are excessively emitted from the floating gate 14 and charged to a positive polarity, this memory cell will not function unless a voltage higher than the ground voltage is applied to the control gate 15. Not turned on. That is, when the two control gates 15 and 16 are both set to the ground potential, no current flows through the channel region 13 between the drain region 11 and the source region 12. Therefore, when a memory cell array is configured using a plurality of memory cells, even if electrons are overdischarged from the floating gate 14, a specific memory cell can be selected.
Data can be read from there.

FIG. 9 is a pattern plan view of another conventional memory cell provided with means for preventing over-emission of electrons from the floating gate 14, and FIG.
FIG. This memory cell shares the drain region 11 as a source region, newly provides a drain region 17 and a control gate 18, and adds a selection MOS transistor 19. Since memory cell selection is performed by controlling the selection transistor 19, when a memory cell array is constructed using a plurality of memory cells, as in the case of FIG. A specific memory cell can be selected even if the

However, since the memory cell shown in FIG. 7 requires an offset gate section, there is a problem that the size of the cell is larger than that of FIG. 5. Furthermore, floating gate 14 and control gate 1
The distance between the offset gate portion and drain region 11 and the floating gate 14 changes due to the mask misalignment that occurs when the mask is aligned with the mask 5, which causes a problem in that data writing characteristics vary. Further, a problem arises in that the memory cell current varies due to the mask shift described above.

Since it is necessary to provide the selection MOS transistor 19 in the memory cell shown in FIG. 9, there is a problem in that the size of the cell becomes even larger than that in FIG. 7, resulting in a significant increase in manufacturing cost. Become.

[Purpose of the Invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to selectively store data even if excessive electrons are emitted from the floating gate and the floating gate is positively charged. An object of the present invention is to provide a nonvolatile semiconductor memory device that can read out data and that can sufficiently reduce the area occupied by memory cells.

[Summary of the invention] In order to achieve the above object, this invention has the following features:
Memory cells each consisting of a MOS transistor having a control gate, a floating gate, a source, and a drain region and capable of electrically writing and erasing data are arranged in row and column directions to form a memory cell array, and the memory cell array The control gates of the memory cells arranged in the same row in the memory cell array are commonly connected to one row line, and these control gates are driven by the signal of this row line. All the source regions of the cells are commonly connected to one end of the switch MOS transistor, the other end of this MOS transistor is connected to the power supply voltage application point, and the switch is controlled by the signal on the corresponding row line. Accordingly, only the source regions of the memory cells in the row selected by the row line are selectively coupled to the power supply voltage application point.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a nonvolatile semiconductor memory device according to the present invention.

In FIG. 1, 20 denotes a drain region 11 and a source region 1, respectively, as shown in FIG.
2, floating gate 14, two control gates 15,1
6, and is a memory cell consisting of a MOS transistor in which data can be electrically written and erased. These plurality of memory cells 20 are arranged in a matrix in the row direction (horizontal direction in the figure) and column direction (vertical direction in the figure) to form a memory cell array 21. Furthermore, this memory cell array 21
Among the plurality of row lines 23, one of which is selectively driven by the output of the row decoder 22, corresponds to the control gate 15 of the plurality of memory cells 20 arranged in the same row. are connected in parallel to one another. In the memory cell array 21, the source regions of the plurality of memory cells 20 arranged in one same row are commonly connected to one end between the source and drain of an enhancement type MOS transistor 24. this
The other end between the source and drain of the MOS transistor 24 is connected to the ground voltage, and the gate is connected to the corresponding row line 23. Further, those corresponding to the control gates 16 of all memory cells 20 in the memory cell array 21 are commonly connected to an erase line 25. In the memory cell array 21, the drain regions of the plurality of memory cells 20 arranged in one and the same column are commonly connected to a corresponding one of the plurality of column lines 26.

In a storage device with such a configuration, one row line 2
Only the source regions of one row of memory cells 20 selected by line 3 are connected to the MOS transistors 2 that are selectively turned on by the signal on that row line 23.
4 to ground voltage. Therefore, data can be read only from these selected memory cells 20, and the potentials of the source regions of other unselected memory cells 20 are brought into a floating state. That is, even if a memory cell whose floating gate is positively charged is connected to the column line 26, the selected column line 26 will not be discharged to the ground voltage via the unselected memory cell. Data can be read selectively.

Normal data writing and erasing in the storage device of this embodiment is performed as follows. That is, to write data, one column line 26 and one row line 23 are selected and a high voltage is applied, and a high voltage is also applied to the erase line 25. As a result, one memory cell 20 is selected, and this selected memory cell 2
Thermal electrons are generated near the drain region of 0 due to impact ionization, and when these electrons are injected into the floating gate, its threshold voltage rises and data is written.

Erasing data is performed by setting all column lines 26 and row lines 23 to ground voltage and further setting erase line 25 to a high potential. At this time, in each memory cell 20, electrons are emitted from the floating gate to the erase line 25 by field emission, and data is erased in all memory cells 20.

FIG. 2 is a partial pattern plan view when the memory device of the above embodiment is integrated into an integrated circuit. Each of the row lines 23 is branched into two and extended, and one row of memory cells 2 is provided between the two branches.
0 common source regions 12 are arranged. Further, the drain region 11 of each memory cell 20 is connected to the column line 26 made of aluminum or the like through a contact hole 27, respectively. The source region 12 of one row of memory cells 20 is shared, and this source region 12 is connected to the selection MOS transistor 24.
It also serves as the source or drain region.
The drain or source region of this MOS transistor 24 is formed separately into two regions 28A and 28B, and is formed in the region 12 and the two regions 2.
The row line 23 is provided as a control gate between each of 8A and 28B. The two regions 28A and 28B are connected to a grounding power supply line 29 made of aluminum or the like through contact holes 30A and 30B. In FIG. 2, the wiring with diagonal lines downward to the right is the erasure line 25, and the wiring with diagonal lines downward to the left is the floating gate 14.

As is clear from FIG. 2, the area occupied by each memory cell 20 is almost the same as that of FIG.
substantially one MOS transistor 24 for
All you have to do is add
The area occupied by each cell can be significantly reduced compared to the conventional device shown in the figure. Moreover, even if the floating gate is positively charged when erasing the memory cell 20, data can be reliably read out, so a wide erasing margin can be achieved.

[Effects of the Invention] As explained above, according to the present invention, electrons are excessively emitted from the floating gate, data can be selectively read even if the floating gate is positively charged, and data can be read out from the memory cell. A nonvolatile semiconductor memory device that can occupy a sufficiently small area can be provided.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the configuration of a device according to an embodiment of the present invention, Fig. 2 is a pattern plan view of a part thereof, Fig. 3 is a pattern plan view of a conventional device, and Fig. 4 is a sectional view thereof. , FIG. 5 is a pattern plan view of another conventional device, FIG. 6 is a cross-sectional view thereof, FIG. 7 is a pattern plan view of another conventional device, FIG. 8 is a cross-sectional view thereof, and FIG. 9 is yet another pattern plan view. A pattern plan view of a conventional device, and FIG. 10 is a sectional view thereof. 11...Drain region, 12...Source region,
20...Memory cell, 21...Memory cell array, 22...Row decoder, 23...Row line, 24...
...MOS transistor, 25...Erasing line, 26...
...Column line, 27, 30...Contact hole, 28
...Source area, 29...Power supply line for ground.

Claims (1)

[Claims] 1. A memory cell array in which memory cells each consisting of a MOS transistor having a control gate, a floating gate, a source, and a drain region and capable of electrically writing and erasing data are arranged in the row and column directions; The control gates of the memory cells arranged in the same row in the cell array are connected in common, and a row line that drives these control gates is connected to one end of the source of all the memory cells arranged in the same row in the memory cell array. and a MOS transistor whose other end is connected to a power supply voltage application point and whose switch is controlled by a signal from a corresponding row line in the memory cell array, and each row line is branched into two and extended. , a nonvolatile semiconductor memory device characterized in that a common source region of memory cells in the same row is arranged between the two branch portions.