JPH03101168A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To read out information with low power consumption by causing the drain region of a memory transistor to be a read line, the gate electrode of a selecting transistor connected in series to be a word line and a source region to be a reading bit line. CONSTITUTION:A CMOS floating gate type transistor Tr1 is connected in series with a selecting Tr2. The gate electrode of the Tr2 is connected to a word line 3, and the source region thereof is connected to a programming bit line 4, and the drain region of the Tr1 is connected to a reading bit line 5. Herein, the Tr1 is formed by connecting an N-type Tr 102 and a P-type Tr 101 is series and the gate electrode thereof is formed by the same floating gate electrode 100. Then, a bit line 5 is used upon read-out so that the conductance of the Tr 101 or the Tr 102 whose gate electrode is the electrode 100 is reduced. Thus, the power consumption during the red-out can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] This invention relates to a semiconductor non-volatile memory for storing information in electronic devices such as computers in a non-volatile manner.

[Summary of the invention]

This invention reduces power consumption in a floating gate semiconductor nonvolatile memory by making the memory cells that make up the semiconductor nonvolatile memory complementary, and by providing a focus line for information writing and a bit line for information retrieval. The purpose is to

[Conventional technology]

Conventionally, the equivalent circuit diagram of a memory cell, which is a component of a semiconductor nonvolatile memory, as shown in FIG. A memory cell with a configuration connected to the

[Problem to be solved by the invention]

However, conventional semiconductor nonvolatile memories have the disadvantage that when reading information, current flows through the floating gate memory transistor, making it difficult to read information with low power consumption.

Therefore, in order to solve these conventional drawbacks, the present invention aims to provide a semiconductor nonvolatile memory that can read information with low power consumption.

[Means to solve the problem]

In order to solve the above problems, the present invention connects memory cells constituting a semiconductor nonvolatile memory in series with a complementary transistor having a common floating gate electrode and a selection transistor for selecting the complementary transistor. , and even more information as a bit line! By providing a write bit line and an information read bit line, an increase in power consumption when reading information is prevented.

In particular, the present invention can be applied to a semiconductor substrate, a semiconductor substrate provided on an insulating substrate, or a semiconductor region provided within a semiconductor substrate. FIG. 3 shows an example in which it is formed on the surface of a type 1) silicon substrate 21. FIG. A first N-type region 26 and a second N-type region 30 are provided on the surface of the P-type silicon substrate 21, and a P-type transistor of a floating data 1-type memory transistor is provided on the surface of the first N-type region 26. A P-type selection transistor is formed in the surface portion of the second N-type region 30. The N-type transistor 102, which is a floating gate type memory transistor, is formed on the surface portion of the P-type substrate 21. That is, the N-type transistor of the floating gate type CMOS memory transistor is as follows.
N-type source region 22. It is composed of an N'' type drain region 23, a gate insulating film 24, and a floating gate electrode 100. Also, a P type transistor 101 + of the constituent transistors of the t-type 1-type 10s memory transistor;
l, first N-type region 2G (as a plate, P'-type sos region 28, P'-type drain region 27, gate [insulating film 29
and a floating electrode 100.

〔Example〕

Examples of the present invention will be described below based on concave surfaces.

FIG. 1 is an equivalent circuit diagram of a semiconductor nonvolatile memory cell which is a component of the semiconductor nonvolatile memory cell of the present invention. C
MO3(Complimentary-MetalOx
ide-3emiconductor) Floating gate memory I - Connect transistor 1 and selection transistor 2 in series, connect the gate electrode of transistor 2 to word line 3, and connect the source region of selection transistor 2 to programming bit line 4. However, the structure is such that the train region of the CMO3 floating gate type memory transistor 1 is connected to the read bit line 5. The CMO5 floating gate memory transistor 1 has an N-type transistor 102 and a P-type transistor 101 connected in series, and their gate electrodes are formed by the same floating gate electrode 100. FIG. 3 is a sectional view specifically showing an equivalent circuit diagram of the semiconductor nonvolatile memory cell shown in FIG.

The semiconductor nonvolatile memory of the present invention can be formed on the surface of a semiconductor region. Drain regions 23 and 27, which are semiconductor regions, are connected to a read bit line 5. In addition, the selection I transistor 3 is connected to the second N type region 3.
0 as a substrate, a p=type '2 space region 32. P" type train region 31. It is composed of a gate insulating layer 33 and a selection gate electrode 34.

The source region 28 of the P-type memory transistor 101 is electrically connected to the drain region 31 of the selection transistor 2. The selection gate electrode 34 is connected to the word line 3, and the source region 32 of the selection 1 transistor 2 is connected to the programming bit line 4.

A method of operating the semiconductor nonvolatile memory of the present invention shown in FIGS. 1 and 3 will be described. First, a method for reading information will be explained. A constant positive voltage ■□ is applied to the programming bit line 4.

The potential of the word line 3 of the line to be read is applied to Ov, and the selection transistor 2 is turned on. Therefore,
Vll is applied to the source region 28 of the floating gate type dry transistor IQ) P-type transistor 101.

Here, in the J1 selected memory cell, the selection gate transistor 2 can be turned off by setting the word line 3 to ■. In the selected memory transistor, if a large number of electrons are inside the floating gate electrode 100, the conductance of the P-type transistor 101 is much larger than the conductance of the N-type transistor 102, so that the bit line for viewing is The potential of 5 is VR
is set to a potential equal to . Conversely, the floating gate electrode 10
When no electron is injected into 0 (erasure state B), N
Since the conductance of the P-type transistor 102 is larger than the conductance of the P-type transistor 101, the read bit &? The potential at t5 is approximately Ov. As described above, reading can be performed by changing the potential of the read bit line according to the amount of electrons injected into the floating gate electrode 100. At this time, since the memory structure is complementary, information can be read out with almost no current flowing.

Next, a method of writing information into a semiconductor nonvolatile memory according to the present invention will be explained. First, erase the information. Erasing means that the drain region 2 of electrons 2 is removed from the floating gate electrode 100.
3 also becomes as high as about 10 V, channel hot electrons are generated in the vicinity of the drain region 23 of the N-type transistor 102, and a portion of them are generated in the floating gate electrode 10.
Injected into 0. The potential of the programming bit line 4 is Ov
If it is low, the channel hot select 11 will not fire and will remain in the erased state. The operating methods explained so far are summarized in the table below (Table 1).

However, ■8 is a voltage during reading, and VPP is a voltage during programming, which is a larger positive voltage than ■.

FIG. 4 shows the semiconductor nonvolatile memory of the present invention. To do this optically, the semiconductor nonvolatile memory is irradiated with ultraviolet rays for about 30 minutes to give energy to electrons inside the floating gate electrode 100, which can be extracted to the substrate side. A method for injecting electrons into the floating gate electrode 100 after erasing will be described.

First, select the line on which to write. Line selection is performed by applying a potential Ov to the selection gate electrode 3. Non-selected memories apply a voltage to the selection gate electrode 3 of the selection transistor 2 so that the selection transistor 2 is turned off. The selection transistor 2 of the memory cell of the selected line is in the ON state. Therefore,
For cells that inject electrons into the floating gate electrode 100, a positive voltage (eg, 12.
5V), the potential of the first N-type region 2G, which is the substrate of the P-type transistor, is also set to a positive potential (approximately 10V), and the potential of the floating gate electrode 100 also increases to approximately 1V.
The potential becomes 0V, and the N-type memory transistor 10
FIG. 2 is an equivalent circuit diagram of a semiconductor nonvolatile memory cell' according to a second embodiment. The equivalent circuit diagram of the memory cell shown in FIG. 4 has a configuration in which a selection I transistor is further provided in addition to the equivalent circuit diagram shown in FIG. 1, and its gate electrode is connected to the word line 7. With the configuration shown in FIG. 4, even if the potential of the read bit line is VR at the time of reading, it will not be affected by unselected memory cells. The potential of the word line 7 of the unselected memory may be set to Ov. Table 2 summarizes the operating method for the embodiment shown in FIG.

Table 2; Memory operating method In the present invention, since floating gate electrodes are formed as gate electrodes of P-type and N-type transistors, the configuration is such that almost no direct current flows when reading information. ing. Therefore, information can be read with extremely low power consumption. Further, in writing information, since writing can be performed even with a small amount of injection, high-speed writing is also possible.

〔Effect of the invention〕

As explained above, the present invention connects in series CMO3 type memo type upper memory transistor selection transistors with floating gate electrodes as gate electrodes of N-type and P-type transistors, and connects the gate electrode of the selection transistor to a word line. By configuring the source region of the selection transistor as a programming bit line and the CMO5 type memory transistor in region as a reading bit line, when reading information, an N-type memory transistor or a P-type memory transistor with a floating gate electrode as a gate electrode is configured. Since the conductance of one of the type memory 1 transistors is always very small, there is an effect of reducing the consumption type) circle during reading.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a semiconductor nonvolatile memory cell which is a component of the semiconductor nonvolatile memory according to the present invention, FIG. 2 is an equivalent circuit diagram of a conventional semiconductor nonvolatile memory cell, and FIG. 3 is an equivalent circuit diagram of a conventional semiconductor nonvolatile memory cell. FIG. 4 is a sectional view of a memory cell of a semiconductor nonvolatile memory according to the invention, and FIG. 4 is an equivalent circuit diagram of a memory cell of a semiconductor nonvolatile memory according to a second embodiment of the invention. CMO5 floating gate type memory transistor selection transistor, word line, programming bit line, reading bit line, floating gate electrode or higher

Claims (1)

[Claims] A first P-type field-effect transistor connected in series through the drain region of the first N-type field-effect transistor and directly connected through the source region of the first P-type field-effect transistor. a second type field effect transistor, and the gate electrode of the first N type field effect transistor and the gate electrode of the first P type field effect transistor are floating gate electrodes. In a semiconductor nonvolatile memory in which memory cells are arranged in a matrix, the gate electrode of the second P-type field effect transistor is connected as a word line, and the second
The source region of the first P-type field-effect transistor is connected as an information writing bit line, and the drain region of the first N-type field-effect transistor and the first P-type field-effect transistor are connected as a bit line for writing information.
A semiconductor nonvolatile memory characterized by the drain region of a field-effect transistor serving as a bit line for reading information.