JPS59135699A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain an inexpensive programmable ROM impossible for rewrite with large storage capacity by using an FAMOS transistor (TR) and omitting its erasing function, in other words, using a plastic package or the like not having an erasing window. CONSTITUTION:An MOSFETQ1 is turned on by applying a high write voltage of about 24V to an external terminal Vpp. Thus, a high voltage of about 10V is applied to a drain of an MOSFETQ2. A normal write operation control signal is applied in this state and an output of an inverter IV1 shown in Fig. 2 goes to a low level by applying a high level signal of about 8V to an external terminal A1, an MOSFETQ4 is turned off and since an output of an inverter IV2 goes to a high level, an MOSFETQ10 is turned off by the low level of a gate control signal -we. Thus, a write selecting signal from a depletion type MOSFETQ15 is applied to a dummy word line DW.

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory device.

2. Description of the Related Art Conventionally, an EPROM device using a FAMO3 (floating gate avalanche injection insulated gate field effect transistor) as a storage element (memory cell) has been known. In this EPROM device, the stored information can be erased by irradiating it with ultraviolet rays or the like. Therefore, information can be rewritten by performing the above erasing operation. For this erasing operation, an erasing window is formed in the pancage of a conventional EPROM device.

By the way, the inventor of the present application has realized that by using the above-mentioned FAMO3I-transistor and omitting its erasing function, in other words, by using a plastic cage or the like that does not have an erasing window, a large storage capacity can be achieved at low cost. I thought of obtaining a programmable ROM that cannot be rewritten.

In the memory device having the above configuration, when it is completed on a semiconductor wafer, it can be erased, so a write test can be performed by blobbing. However, the writing test after packaging cannot be erased and becomes a destructive test. Therefore, it has been found that a problem arises in that a write test cannot be performed, resulting in a poor yield in the market.

An object of the present invention is to provide a semiconductor memory device that has a large storage capacity and a low price, while improving its reliability.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

A block diagram of an embodiment of the invention is shown in the drawings.

In the semiconductor memory device of this embodiment, in its entirety, that is, in the drawing, each circuit block is a well-known MO3 (metallic)
It is constructed as a single semiconductor integrated circuit device using insulator-semiconductor (insulator-semiconductor) integrated circuit technology.

This semiconductor memory device has external terminals A1 to An.

Vcc, GND, Ilo, Vpp, PRG, OB and plane are provided.

Address signals are supplied to external terminals A1 to An, and Vc
A power supply voltage such as +5V is supplied to c. A data signal is supplied from a writing device (not shown) to the external terminal I10 during data writing, and data is output during reading. + when writing data to the external terminal Vpl).
A high voltage such as 25V is supplied, and a relatively low potential such as 0 or 5V is applied during reading. External terminal PRG
, OR, and planes are supplied with a program control signal, an output enable signal, and a chip enable signal, respectively.

In the figure, X-ADB is an X address buffer, which forms internal complementary address signals 11 to 18 to be supplied to the X decoder circuit X-DCH by receiving address signals from external terminals A1-88. do. Although not particularly limited, the operation of the X address buffer X-ADB is controlled by the control signal Ce and signal supplied from the control circuit C0NT. Only when the control signal ce and the seal are set to high level and low level, respectively,
Address buffer X-ADB is activated and forms internal complementary address signals 11-8. The above control signal c
The X address buffer X-ADH is rendered inactive when e and O are set to low level and high level, respectively.

The X-decoder circuit X-DCR receives internal complementary address signals 1 to 18 to
A word line selection signal for selecting word lines W1 to W256 of RY is formed.

In addition, in the write operation, about 21
A high-level word line selection signal is formed by a high voltage Vl)p' of about V.

The memory array MARY is composed of a plurality of FAMO transistors F1 to F256, word lines W1 to W256, and digit lines D1 to Dn arranged in a matrix.

In memory array MARY, F arranged in the same row
The control gates of the AMOS transistors F are commonly connected to the corresponding word lines W1 to W256, and the drains of the FAMost transistors F arranged in the same column are commonly connected to the corresponding digit lines D1 to Dn, respectively. There is.

In this embodiment, although not particularly limited, the sources of the FAMO transistors F arranged in adjacent rows are integrally formed by a common semiconductor region.
A switch MO3FET that constitutes a common source line SL and receives the voltage of the word line of the row between it and the circuit ground potential.
SI~5256 is provided. These MO3FETS
1-3256, only the selected word line is turned off, reducing the leakage current during writing in the selected row, and also reducing the leakage current in the unselected row.
The OS FET is turned off to prevent leakage current from occurring.

Y-ADB is a Y address buffer, and external terminal A
By receiving address signals from 9 to An, Y
Internal complementary address signals 19-an to be supplied to the decoder circuit Y-DCR are formed. The Y-decoder circuit Y-DCR receiving internal complementary address signals a9 to an has a column switch circuit l? a selection signal for supplying to 8csw;
For example, CS1 to C532 are formed.

Column switch circuit C8W, Y decoder circuit Y-DC
Digit lines corresponding to selection signals CSt to C532 supplied from R are coupled to common digit line CD.

Although not particularly limited, in this embodiment, the number of digit lines is 32, and the common digit line CD is provided for these 32 digit lines.

The common deciso 1-lines CD are coupled to respective corresponding read/write circuits R/W. and,
It is connected to the input/output terminal I10 via the input/output buffer B.

If the control signal we is at a high level, the read/write circuit R/W is put into a write operation state, and the cover sofa B'
4c, the manually inputted data signal and the corresponding write signal are transmitted to the common digit line CD.

When the control signal we is at a low level, the read/N input circuit R/W is put into a read operation state, amplifies the signal read out to the common digit line CD, and sends it to the input/output buffer B.
and sends it out from the external terminal I10.

In this embodiment, dummy arrays DXAR and DYAR are provided to perform a write test after parsing. The dummy array D
and FAMO3I transistors DF to DF', and their gates and control gates are commonly connected to the tammy word line DW. Also, dummy array D
YAR is not particularly limited to F
It is composed of AMOS transistors DF1 to DF256.

The following circuit is provided to select the dummy arrays DXAR and DYAR.

Although not particularly limited, a first level detection circuit LVX that receives a signal from the external terminal AI and a second level detection circuit LVY that receives a signal from the external terminal A9 are provided.

These level detection circuits LVX and LVY each detect, for example, a high level of approximately 6 cm higher than the power supply voltage Vcc. This detection output is, on the other hand, a dummy word line DW,
Selection circuit DXS, D for selecting dummy digit line DD
Each O3 is informed and makes its selection. Further, the above detection output is transmitted from the above X address decoder X- on the other hand.
DCR and Y-address decoder Y-DCR are respectively rendered inactive.

FIG. 2 shows a circuit diagram of an embodiment of each circuit for selecting the dummy array DXAR.

The level detection circuit LVX is composed of the following circuit elements. The signal at external terminal AI is applied to the gate of MO3FETQ2. A MO3F with a high threshold voltage is connected between the drain of this MO3FETQ2 and the high power supply voltage vpp.
ETQ1 is provided. This MO5FETQI is
The gate edge film is formed by the feed insulating film and has a high threshold voltage of about 15V. ”The source of MO3FETQ2 has voltage dividing resistors R1 and R2.
M is connected at one end and receives control signal ce at the other end.
A ground potential is applied via O3FETQ3. The divided voltage outputs of the voltage dividing resistors R1 and R2 are input to the inverter IVI.

For example, when a high signal level of about 8■ is supplied to the external terminal, the divided voltage output becomes higher than the rosin threshold voltage of the inverter rv1, and when a normal logic high level (5■) is supplied, The resistance ratio of the resistors R1 and R2 is set so that the divided voltage output is lower than the inverter IVIO logic threshold voltage.

Further, the dummy word line selection circuit is constituted by the following circuit elements. The output of the above inverter IVI is MO
It is transmitted to the gate of 3FETQ4, and its drain is
An inverted signal is supplied through inverter IV2. A depletion type MO3FET QIO that receives a control signal is provided between the drain of this MO3FET Q4 and the dummy word line DW. Further, a high voltage vpp'' of about 21 V is supplied to the dummy word line DW via the depletion type MO3FET QI5.

Note that the X-address decoder X-DCR includes drive MO3FETs Q7 . Q8, a depletion type load MO3FETQ6 provided on the common drain of the NOR gate circuit, and a power switch MO3FETQ5 that receives the control signal CG and supplies the power supply voltage Vcc to the NOR gate circuit. Complementary decoded output co-c7 of 8il\l is generated by the address decoder of the first stage (not shown) based on the 3-bit signals of the address decoder and the address signals a1 to a3. It is composed of a MOS FET that receives These MOSFETs use the output of the NOR gate circuit as eight selection signals corresponding to word lines W1 to W8.

These eight selection signals are transmitted to each word line W1-w8 via depletion type MO3FETs Q11-Q14 similar to those described above. In addition, each word line W1 to W8
is a depression type MOS FET similar to the above.
Q16 to Q19 are provided.

In this embodiment, the NOR gate circuit is provided with a drive MO3FETQ9 that receives an inverted signal formed by the inverter IV3 that receives the output of the inverter IVI, and inhibits the word line selection operation of the memory array when selecting the dummy word line DW.

Note that the selection circuit DO3 for selecting the dummy digit line DD, the level detection circuit LVY, and the Y address decoder Y-DCR are also constituted by the same circuits as described above.

Although the packaging of the semiconductor memory device of this embodiment is not particularly limited, it is sealed with plastic or the like so that it does not have an erasing function.

In the semiconductor memory device of this embodiment, even after packaging, the dummy arrays DXAR, DYAR
A writing test can be conducted using the following.

By supplying a high write voltage of about 25 V to the external terminal (Vpl), the MO3FETQI is turned on. Therefore, approximately 1
A high voltage of about 0V will be supplied. In this state, by supplying a normal write operation control signal and a high level signal of approximately 8V to external terminal A1, the output of inverter IVI in FIG. 2 becomes low level, turning MO3FET Q4 into an OFF state. , and the output of inverter IV2 becomes high level, so the MO3FET
QI O is turned off. Therefore, the write selection signal from the depletion type MO3FETQ15 is supplied to the dummy word line DW. At this time, the output of the inverter IV3 becomes high level and turns on MO3FETQ9 of the X address decoder X-DCH, so all words IJWI to W256 are set to a low level non-selected state.

2. Therefore, by selecting an arbitrary digit line and setting write data, writing to the dummy cell DXAR can be performed.

Also, select the dummy digit line DD in the same way!
: allows writing to the dummy cell DYAR.

Further, in the read operation after writing, the control signal we goes high/bell, so the MO3FET QIO is turned on, and the high level output of the inverter IV2 is supplied to the dummy word line DW.

Furthermore, in the write operation to the memory array MARY, since the signals at the external terminals AI and A9 are at a high level and the logic level is about 5V, the output of the inverter IVI becomes a high level, and the dummy word line DW is selected. There isn't. This also applies to dummy digit line DD.

In this embodiment, since a write test can be performed after packaging, the reliability can be increased. Furthermore, in the write test, the operation modes are distinguished using three-value levels, so there is no need to increase the number of external terminals. Furthermore, since it is configured with an MO8 built-in circuit, it is possible to achieve a large storage capacity, low power consumption, and low cost.

The invention is not limited to the above embodiments.

The above three-level level is, for example, depression type MO3F.
Numerous embodiments can be adopted, such as one in which negative voltage is detected by using ET. The external terminal for manually inputting the three-value levels may be any terminal as long as it does not affect the normal operation as described above.

Furthermore, if the number of external terminals is sufficient, a control terminal for switching to the dummy array may be added.

Further, when configuring a semiconductor memory device having a ×n bit configuration, n sets of the above-mentioned memory array, dummy array, read/write circuit, and input/output circuit may be provided.

[Brief explanation of the drawing]

5. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a specific embodiment thereof. MARY...Memory array, X-ADB...X address buffer, Y-ADB...Y address buffer, X-D
CR...X decoder circuit, Y-DCR...Y decoder circuit, C8W...column switch circuit, R/W...read/write circuit, B...population cover sofa, C0NT...
Control circuit, DXAR, DYAR...dummy array, LV
X, LVY: level detection circuit, DXS: dummy word line selection circuit, DC3: -dummy digit line selection circuit 6

Claims (1)

[Claims] (1) A memory array and a dummy array whose memory cells are composed of FAMO3I transistors, a memory cell selection circuit that selects a memory cell of the memory array, and a dummy cell selection circuit that selects a dummy cell of the dummy array. It is characterized by comprising a circuit and a level detection circuit that detects the level of its external terminal and selectively operates the memory cell selection circuit or the dummy cell selection circuit, and is sealed in a non-erasable package. A semiconductor storage device. 2. The semiconductor memory according to claim 1, wherein the external terminal is an address signal terminal, and the input level for activating the dummy cell selection circuit is a high level higher than a logic high level. Device.