JPS6267798A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6267798A
JPS6267798A JP20648385A JP20648385A JPS6267798A JP S6267798 A JPS6267798 A JP S6267798A JP 20648385 A JP20648385 A JP 20648385A JP 20648385 A JP20648385 A JP 20648385A JP S6267798 A JPS6267798 A JP S6267798A
Authority
JP
Japan
Prior art keywords
turned
mosfet
external terminal
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20648385A
Other languages
Japanese (ja)
Other versions
JPH0766672B2 (en
Inventor
Yoshinori Suzuki
Isamu Kobayashi
Yasuhiro Sakakibara
Original Assignee
Hitachi Micro Comput Eng Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Micro Comput Eng Ltd, Hitachi Ltd filed Critical Hitachi Micro Comput Eng Ltd
Priority to JP20648385A priority Critical patent/JPH0766672B2/en
Publication of JPS6267798A publication Critical patent/JPS6267798A/en
Publication of JPH0766672B2 publication Critical patent/JPH0766672B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a semiconductor integrated circuit device suppressing the generation of an input leak current and including a high voltage detecting circuit by forming a switch MOSFET to be turned on by an operation mode signal outputted from a memory circuit.
CONSTITUTION: In an EPROM operation mode state, an operation mode signal EPM is turned to the high level and a MOSFET Q5 is turned on. When an external terminal Ai is set up to about 12V higher than a power supply voltage such as about 5V in the EPROM operating state, a MOSFET Q1 is turned ON. In the operation mode state on the microcomputer side, the control signal EPM is turned to the low level and the MOSFET Q5 is turned OFF. Consequently, the generation of input leak current flowing into the external terminal Ai can be suppressed independently of the voltage supplied to the external terminal Ai or the process dispersion of the MOSFET Q1.
COPYRIGHT: (C)1987,JPO&Japio
JP20648385A 1985-09-20 1985-09-20 Semiconductor integrated circuit device Expired - Fee Related JPH0766672B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20648385A JPH0766672B2 (en) 1985-09-20 1985-09-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20648385A JPH0766672B2 (en) 1985-09-20 1985-09-20 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6267798A true JPS6267798A (en) 1987-03-27
JPH0766672B2 JPH0766672B2 (en) 1995-07-19

Family

ID=16524119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20648385A Expired - Fee Related JPH0766672B2 (en) 1985-09-20 1985-09-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0766672B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59135699A (en) * 1983-01-21 1984-08-03 Hitachi Ltd Semiconductor storage device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59135699A (en) * 1983-01-21 1984-08-03 Hitachi Ltd Semiconductor storage device

Also Published As

Publication number Publication date
JPH0766672B2 (en) 1995-07-19

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Legal Events

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