JP2659227B2 - MOS nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS-type nonvolatile semiconductor memory device, and more particularly to a MOS-type nonvolatile memory transistor having a floating gate electrode in a gate insulating film for instantaneously reading a MOS-type nonvolatile memory transistor. Type nonvolatile semiconductor memory device.

[Conventional technology]

Conventionally, a MOS nonvolatile semiconductor memory device having a MOS nonvolatile memory transistor having a floating gate in a gate insulating film (hereinafter referred to as a memory Tr) and writing or erasing information by emitting or injecting electrons. Is
In order to read information from the memory Tr, the memory Tr has a function of inputting an address signal from the outside and reading the information of the memory Tr via external terminals of the number of bits constituting a word one word at a time.

[Problems to be solved by the invention]

The conventional MOS nonvolatile semiconductor memory device described above
In order to read information from the memory Tr, an address signal is input from the outside to read out one word at a time. Therefore, in order to read information of all words, a time of (access time × number of words) is required.
There is a disadvantage that the time for reading information from the memory Tr increases and the power consumption also increases.

Further, an IC having a limited number of external terminals, for example, an IC built in an IC card, has a disadvantage that the number of external terminals is increased by the number of bits constituting a word.

An object of the present invention is to provide a MOS nonvolatile semiconductor memory device which can reduce the time required to read information from the memory Tr, reduce the power consumption for reading, and efficiently use the number of external terminals.

[Means for solving the problem]

A MOS nonvolatile semiconductor memory device according to the present invention has an EE in which MOS nonvolatile memory transistors are arranged in an array.
In a MOS nonvolatile semiconductor memory device in which a PROM and a read circuit for reading information of each MOS nonvolatile memory transistor of the EEPROM are formed on the same semiconductor substrate, an address signal and a chip enable signal are inputted. An address decoder that inputs the address decoder output and an erase signal to select an address; an address select control circuit that controls the address select circuit based on a read signal and an erase signal; The storage information of each MOS-type nonvolatile memory transistor of the EEPROM specified by the address selection circuit is read out in word line units, and the sense amplifiers provided as many as the number of digit lines are determined to match the respective outputs of the sense amplifiers, and all erasure is performed. A logical product circuit for outputting a signal, All the output signals of the address decoder are set to the selected state, and the output of the address selection circuit is supplied to the word line of the EEPROM to which the MOS-type nonvolatile memory transistor is connected.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a MOS nonvolatile semiconductor memory device showing one embodiment of the present invention.

As shown in FIG. 1, in this embodiment, a read terminal (RD) 1 for inputting a read signal, an erase terminal (▲ ▼) 2 for inputting an erase signal, and a chip enable terminal (▲ ▼)
3, an all erase terminal 4 indicating that the information of all the memory cells Tr has been erased, and an address decoder which inputs address signals A0 to A3 and decodes them into addresses on the memory by two-input NAND5A and four-input NAND5B. 5 and 2 inputs
An address selection circuit 6 having a NOR 6A and a level shifter 11, an address selection control circuit 7 having a level shifter 11 and controlling the address selection circuit 6, and a memory transistor 8B connected to a pair of selection transistors 8A and a word line 8C are provided. EEPROM8 output from the digit line 8D and E
It has each sense amplifier 9 connected to the EPROM 8 and an AND circuit 10 connected to each sense amplifier 9 and outputting a coincidence output of the erase state of the memory transistor 8B to the all erase terminal 4.

Next, a circuit operation of the memory device will be described.

First, when the “L” level is input to the chip enable terminal 3, all the outputs of the two-input NAND 5A become “H” level,
The output of the four-input NAND5B becomes "L" level. Next, when the “H” level is input to the read terminal 1 and the “L” level is input to the erase terminal 2, respectively, the two inputs NOR 6 of the address selection circuit 6 are input.
The output of A is at the "H" level, the line A which is the input of the address selection control circuit 7 is at the "H" level, the output B of the control circuit 7 is at the "L" level, and is another control output. Line C and line D which is the output of the address selection circuit 6
Output an “H” level. Therefore, the EEPROM
Since all the select transistors 8A are turned on, the first potential (power supply voltage) from the line E is applied to the gates of all the memory Trs 8B.

At this time, if all memories Tr8B are in the erased state,
Even if a potential is applied to the gate of 8B from the line E, the memory Tr8B remains off since the threshold level of the memory Tr8B in the erased state is higher than the potential of the line E. Therefore, no current flows through the line F connected to the digit line 8D of the EEPROM 8, and all the outputs of the sense amplifiers 9 go to the "H" level. Therefore, the output of the AND circuit 10 composed of NAND gates and inverters is It goes to the “H” level, and the “H” level is output to the all erase terminal 4.

On the other hand, if the memory Tr8B of at least one bit exists in the memory Tr8B of the EEPROM 8, the potential of the line E is applied to the gate of the memory Tr8B in the written state. That is, since the sun threshold level in the write state is lower than the potential of the line E, the memory Tr8B in the write state
Turns on and the digit line 8D to which the memory Tr8B is connected
Current flows through Due to this current, only the output of the sense amplifier 9 becomes “L” level, the “L” level is output to all the erasure terminals 4 via the AND circuit 10, and the existence of the memory Tr8B in the written state is one. It is determined by the output level of the external terminal.

As described above, in the present embodiment, it is possible to confirm at a time whether or not all the memories Tr8B of the EEPROM 8 are in the erased state. Therefore, it is possible to reduce the read time and the power consumption, In an IC built in an IC card or the like having a small number of terminals or a limited number of terminals, only one erase terminal is sufficient.

FIGS. 2A and 2B are a specific circuit diagram and an equivalent circuit diagram of the level shifter shown in FIG. 1, respectively.

As shown in FIGS. 2 (a) and 2 (b), the level shifter 11 (see FIG. 1) has two sets of P-channel MOS Tr P and N-channel MOS Tr N between the input side I and the output side O. And a circuit for shifting the level of a read signal and an address signal as input signals.

〔The invention's effect〕

As described above, the MOS-type nonvolatile semiconductor memory device of the present invention does not need to input an address signal from the outside, and enables to confirm at a time whether or not all the memory Trs are in the erased state. This has the effect of reducing the read time and the power consumption. In addition, the present invention relates to an IC having a limited number of external terminals, for example, an IC built in an IC card, in which all memory Trs are connected to one external terminal.
Has the effect that it can be determined that the device is in the erased state.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a MOS type nonvolatile semiconductor memory device showing an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are a specific circuit diagram and an equivalent circuit diagram of the level shifter shown in FIG. 1, respectively. It is. 1 ... Readout terminal, 2 ... Erase terminal, 3 ... Chip enable terminal, 4 ... All erase terminal, 5 ... Address decoder, 5A ... 2 input NAND, 5B ... 4 input NAND, 6 ... Address Selection circuit, 6A: 2-input NOR, 7: Address selection control circuit, 8: EEPROM, 8A: Selection Tr, 8B: MO
S-type nonvolatile memory Tr, 9: sense amplifier (current sense), 10: AND circuit, 11: level shifter, A0 to A3
…… Address signal, VDD …… Power supply voltage (first voltage), V
PP: High voltage (second voltage higher than power supply voltage), P: Pc
h, Tr, N ... NchTr.

Claims (1)

(57) [Claims] An EEPROM having MOS nonvolatile memory transistors arranged on an array and a read circuit for reading information of each MOS nonvolatile memory transistor of the EEPROM are formed on the same semiconductor substrate. An address decoder that inputs and decodes an address signal and a chip enable signal, an address selection circuit that inputs the address decoder output and an erase signal to select an address, and a read signal. And an address selection control circuit for controlling the address selection circuit based on the erase signal, and read out the storage information of each MOS type nonvolatile memory transistor of the EEPROM specified by the address selection circuit in word line units and read out the digit lines. The number of sense amplifiers provided matches the output of each of the sense amplifiers. And an AND circuit that outputs an all-erase signal, and sets all output signals of the address decoder to a selected state at the time of a good read operation, and outputs the output of the address selection circuit to a MOS nonvolatile memory of the EEPROM. A MOS non-volatile semiconductor memory device, which supplies a voltage to the word line to which a transistor is connected.