JP2918723B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically writable and erasable semiconductor memory device having a floating gate, and more particularly to a stable read operation even when a read voltage is lowered. The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art One of electrically rewritable semiconductor memory devices is a flash EEPROM (flash memory). This storage device is a batch erase type (all bits simultaneous erase type), and cannot be rewritten in byte units.
Since one memory cell can be constituted by one memory transistor, it can be an inexpensive semiconductor nonvolatile memory. Further, since the flash EEPROM can be erased in units of blocks, it has attracted much attention as a memory replacing a magnetic disk.

[0003] Figure 4 is a diagram showing a cross sectional structure of the memory transistor in the conventional flash EEPROM, in FIG, 1 is a P-type substrate, 2, the drain comprising a N ⁺ diffusion layer, 3 is the N ⁺ diffusion layer , A control gate, a floating gate, V _D , V _S ,
V _G is the drain 2 and the source 3, the voltage applied to the control gate 4, I _D is the current flowing into the drain 2. Here, the drain 2 and the source 3 are connected to a bit line and a source line in the matrix, respectively, and the control gate 4 is connected to a word line in the matrix. The floating gate 5 captures electrons by writing, retains electrons even when the power is turned off, and emits electrons during erasing. In addition, floating gate 5
An insulating film called a tunnel oxide film is formed between the substrate and the substrate 1, and usually has a thickness of about 100 angstroms. Then, this tunnel oxide film emits electrons in the floating gate 5 to the source 3 by a tunnel phenomenon. In addition, an insulating film is formed between the control gate 4 and the floating gate 5, which usually has a film pressure of 200 Å or more.

FIG. 5 is a graph showing the relationship between the _{ID of the} memory transistor and the _ID.
Is a diagram showing the V _G characteristics, in FIG., V _THE indicates the threshold value of the memory in the erased state, V _THP denotes a memory threshold after programming. When writing the memory, a positive high voltage is applied to the drain 2 and the control gate 4,
The source 3 is set to the ground potential. At this time, a channel is formed between the drain 2 and the source 3, a current flows, and hot electrons are generated in the depletion layer of the drain 2. The hot electrons are generated by the electric field generated by the positive voltage applied to the control gate 4 and the floating gate 5
Is pulled and captured. When hot electrons are injected into the floating gate 5, the threshold value V _THP of the memory after writing shifts to a higher value as shown in the figure. When erasing the memory, the control gate 4 is set to the ground potential, the drain 2 is set to the floating state or the ground potential, and a positive high voltage is applied to the source 3 so that the electrons trapped in the floating gate 5 are tunneled. Is released to the source 3.
Then, the threshold value V _THE of the memory after erasing returns to the original state as shown in the figure. At this time, if all the source lines in the matrix are electrically connected, a positive high voltage is simultaneously applied to the sources 3 of all the memory cells, so that the data is erased collectively.

FIG. 6 is a diagram showing a circuit configuration of a conventional semiconductor memory device having the above-mentioned memory transistors. In FIG. 6, a plurality of memory transistors are arranged in a matrix to form a memory cell array. , The drain of the memory transistor is connected to the bit line BLj for each column.
(J = 0 to n), the control gate is connected to a word line WLi (i = 0 to m) for each row, and the source is connected to a common source line S. Each word line has an X address for transmitting an input address signal to the word line.
A decoder XDi (i = 0 to m) is connected, and an output circuit 50 including P and N channel transistors in the X decoder XDi (i = 0 to m) is connected to the power supply circuit 20. The power supply circuit 20 includes a read external power supply V _CC
(Normal 5V) and write / erase the external high voltage power source V _PP N-channel transistor T ₁₀ which is disposed between the (usually 12V) to an external power source for reading V _CC and the write / erase external high voltage power source V _PP, T _11, the read signal is the input monkey input terminal 10 Prefecture, the input terminal 10 and the gate of the N-channel transistor T _10, and is connected to the gates of the N-channel transistor T ₁₁ via the inverter 30. When the read signal to this input terminal is "L", N
The channel transistors T ₁₀ and T ₁₁ are ON and O, respectively.
Outputs V _PP voltage by the power supply circuit 20 to the external high voltage power supply V _PP for programming / erasing becomes FF, also, the read signal becomes respectively T _10, T ₁₁ are OFF, ON when the "H" power V _CC due to the external power supply V _CC for reading from the circuit 20
A voltage is output, and these voltages become the voltage of the word line WLi selected by the address signal. Therefore, at the time of reading, the control gate voltage of the selected memory transistor becomes the V _CC voltage. Since the standard for the read voltage V _CC of a normal product is generally 5 V ± 10%, the memory is written and erased in a range of 4.5 V ≦ V _CC ≦ 5.5 V. It must be placed, when made to correspond to the V _THP and V _tHE in FIG 5, V _THP
> 5.5V, V _THE <4.5V. However, in order to operate stably with a margin, the product is generally set to 5 V ± 20% or more. In view of this point, V _THP > 6 V, V
It is necessary to satisfy the relation of _THE <4V. Also,
V _THE is necessary that also satisfies the relationship of 0 _V <V _THE <4V, this is because the drain of each memory transistor is connected to the bit line, the memory after erasure V
_{If THE} is made negative, the memory is turned on even when the word line is at the ground level in a non-selected state, so that reading of the selected memory is prevented, resulting in a so-called over-erased state. In this circuit, the source line S is at the ground level at the time of reading.

[0006] By the way, Hula Tsu Gerhard EEPROM is in the configuration to be erased because it is a collective erase, the whole bit at the same time electrically. That is, if the product has a memory capacity of 1 Mbit, about one million memories are simultaneously erased. However, in actuality, memory transistors constituting a memory cell have slightly different transistor characteristics such as electron injection speed and transistor size. , The erase characteristics are slightly different for individual transistors, and if the V _THE distribution is within 0 to 4 V from the relationship between the threshold values of the memory transistors described above, all bits can be erased satisfactorily. .

FIG. 7 is a diagram showing a distribution state of a threshold voltage V _TH of a memory transistor. In FIG.
The write area is area B standard areas of the product, area C erasure region, region D is over-erased area, for example, the distribution state of the threshold voltage V _TH is shown in FIG. 7 (a) of each memory transistor In this device, the device operates normally without being over-erased.

[0008]

In recent years, the read voltage V _CC
In order to drive the battery in the future, there is an increasing demand for a storage device that can operate with a read voltage smaller than 5 V, for example, a read voltage of about 3 V. However, in the conventional storage device, it is necessary to lower the upper limit of the threshold voltage V _THE of the memory transistor in the erased state, and the standard for the read voltage V _CC is 3V ± 10.
% And V _THE and V _THP are set to 3V ± 20%, the distribution state of the threshold voltage V _TH of the memory transistor becomes as shown in FIG. 7 (b). of the threshold voltage V _tHE must satisfy 0 <V _tHE <2.4V, the memory cell array obtained by the conventional manner of manufacturing conditions, the threshold at the time of erasing some of the memory transistor The voltage V _THE shows a negative value,
There is a case where normal operation cannot be performed due to an over-erased state. In order to properly operate, it is necessary to suppress than the variation in the V _TH of the memory transitional scan <br/> data in the past,
For this reason, strict restrictions are added to the manufacturing conditions at the time of manufacturing, and there is a problem that the yield is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can use a memory transistor (memory cell array) manufactured under the same manufacturing conditions as the conventional one, and can reduce the read power supply voltage. It is another object of the present invention to obtain a semiconductor memory device that can operate normally.

[0010]

A semiconductor memory device according to the present invention is provided with a constant voltage power supply circuit for applying a constant voltage to a selected word line at the time of reading.

[0011]

In the present invention, a constant voltage power supply circuit for applying a constant voltage to a selected word line at the time of reading is provided. Therefore, even if the external power supply for reading is lowered, the voltage level of the word line is constant. Since the output voltage is the output voltage of the power supply circuit, it is not necessary to extremely lower the threshold voltage of the memory transistor in the erased state, and the allowable range for the variation in the erase characteristics of the memory transistor can be increased.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of a semiconductor memory device according to an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 6 indicate the same or corresponding parts, and the memory device shown in FIG. constant-voltage power supply circuit 40 is provided between the N-channel transistor T ₁₁ and the read external power supply V _CC of the conventional memory device.

FIG. 2 is a diagram showing a circuit configuration of the constant voltage power supply circuit 40. In FIG. 2, the inverter I ₁ ,
_{I 2, I 3, I 4} , ring oscillator constituted by I ₅ is connected to the N-channel transistor T ₂ which is diode-connected through a boost capacitor C _1, the boost capacitor C ₁ and the diode-connected N A read external power supply V _CC is connected to a node N ₁ with the channel transistor T ₂ . The N-channel transistor T ₂ is connected to a voltage clamp composed of N-channel transistors T ₃ , T ₄ , T ₅ , T ₆ , and T ₇ which are diode-connected via the node N _2, and is shown in FIG. N
Between tea N'ne Le transistor T ₁₁ and the node N _2, a capacitor C _2, one end of which is grounded is provided, the node N ₂
Voltage is stabilized.

Next, the operation will be described. The N-channel transistor _{T 1, T 2, T 3} , T 4, T 5, T
_Assuming that the threshold voltage V _TH of T ₆ and T ₇ is 1 V, the node N
₁ is V _CC −V _TH by a ring oscillator constituted by inverters I ₁ , I ₂ , I ₃ , I ₄ , I ₅ , a capacitor C ₁ and an N-channel transistor T ₁ .
And between 2 V _{CC and} V _TH . Then, the high voltage at the node N ₁ by N-channel transistor T ₂ are supplied to the node N _2, node N ₂ is clamped to 5V,
5V at the node N ₂ is output to the N-channel transistor T ₁₁ shown in FIG. 1 is stabilized by the capacitor C _2. As a result, a power supply voltage is output from the power supply circuit 20 including the constant voltage power supply circuit 40 to the word line selected by the address signal.

[0015] In the semiconductor memory device of such a present embodiment, the constant voltage power supply circuit 40 shown in FIG. 2 is provided between the N-channel transistor T ₁₁ and the read external power supply V _CC, an external power supply V _CC for reading Is applied to the word line through the constant voltage power supply circuit 40. For example, if the output of the constant voltage power supply circuit 40 is set to 5V, the output voltage of the external power supply V _CC for reading is 5V. Similarly, the output level of the selected word line WLi becomes 5 V, but the output level of the selected word line WLi becomes 5 V even when the external read power supply V _CC is 3 V. The distribution of the voltage V _TH is close to that shown in FIG. 7A, and normal operation can be performed without being over-erased. Also, since the read voltage is actually a constant voltage, the area B in the figure is only 5 V, and the area C is further expanded.
Even if the variation in the distribution of the threshold voltage V _{THE in} the erased state is further widened, the malfunctioning operation is reduced, the allowable range of the variation in the erase characteristics of the individual memory transistors is widened, and the production yield is improved. .

FIG. 3 is a diagram showing a circuit configuration of a constant voltage power supply circuit in a semiconductor memory device according to a second embodiment of the present invention. In this embodiment, the voltage clamps are N-channel transistors T ₃ , T ₄ , _{6 of} T ₅ , T ₆ , T ₇ , T ₈
It is composed of stage transistors.

In the semiconductor memory device of this embodiment, the N-channel transistors T ₃ , T ₄ , T ₅ ,
Since the output of the constant-voltage power supply circuit composed of the six-stage transistors T ₆ , T ₇ , and T ₈ becomes 6 V, the distribution of the threshold voltages of the memory transistors becomes as shown in FIG. Here, the product standard is 6 V ± 10%, and V _THP and V _THE are 6 V ± 20%.) Since the area B is only 6 V, the area C is further expanded as compared with FIG. In addition, the allowable range for the variation in the erasing characteristics of the individual memory transistors is further expanded, and the yield in manufacturing is further improved.

[0018]

As described above, according to the semiconductor memory device of the present invention, at the time of reading, the constant voltage power supply circuit for applying a constant voltage to the selected word line is provided. Even if this is done, the memory transistors will not be over-erased and can operate normally, and the level of uniformity of the erasure characteristics of each memory transistor can be made the same as before, so that the production yield will be the same as before. The effect can be maintained.

Further, according to the semiconductor memory device of the present invention, when the output voltage of the constant voltage power supply circuit is higher than the readout external voltage, even if the erasing characteristics of the memory transistor are larger than those of the prior art, the memory transistor is overloaded. Erasure is reduced, and there is no need to uniform the erasure characteristics of the memory transistor at a high level, which has the effect of improving the production yield.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a constant voltage power supply circuit of the semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a constant voltage power supply circuit of a semiconductor memory device according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of a memory transistor in a semiconductor memory device.

FIG. 5 illustrates current-voltage characteristics of a memory transistor in a semiconductor memory device.

FIG. 6 is a diagram showing a circuit configuration of a conventional constant voltage power supply circuit of a semiconductor memory device.

FIG. 7 is a diagram showing a distribution state of a threshold voltage V _TH with respect to an external power supply voltage of a memory transistor in a semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Readout signal 20 Power supply circuit 30 Inverter 40 Constant voltage power supply circuit 50 Output circuit of X decoder 1 Substrate 2 Drain 3 Source 4 Control gate 5 Floating gate

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-3187 (JP, A) JP-A-1-259556 (JP, A) JP-A-1-307097 (JP, A) JP-A-62-1987 143297 (JP, A) JP-A-60-79598 (JP, A) JP-A-57-175098 (JP, A) JP-A-57-178897 (JP, U) (58) Fields investigated (Int. ⁶ , DB name) H01L 27/115 H01L 21/8247 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] A memory transistor having a floating gate and a control gate, which can be electrically written and erased; a memory cell array in which the memory transistors are arranged in a matrix in a plurality of rows and a plurality of columns; A plurality of word lines provided by connecting control gates of memory transistors for each row; a plurality of X decoders provided corresponding to each word line and selecting a corresponding word line according to an address signal; a constant voltage power supply circuit for generating a higher external read power constant voltage, receiving the read signal, the read signal is activated, is constant voltage generated from the constant-voltage power supply circuit when the read is instructed A read voltage is output, and when the read signal is inactivated, a write / erase different from the read voltage is performed. A power supply circuit for outputting an application voltage; and a control gate of a memory transistor provided in each of the plurality of X decoders, receiving an output from the power supply circuit and connected to a word line selected according to the address signal. An X-decoder output circuit for applying the read voltage which is the aforementioned constant voltage at the time of reading and the write / erase voltage at the time of writing.