JPS5929448A - Programmable read only memory - Google Patents

Abstract

PURPOSE:To shorten a channel, and to increase the capacitance of the memory by bringing only the potential of the source of a memory cell selected to a low level on writing while providing a bias applying means for keeping the source potential of all memory cells at low levels on reading. CONSTITUTION:When the memory cell M11 is written, the source voltage of an enhancement type MAS transistor T18 is at a high level as voltage Vc because a reading signal R is at a low level, and a T14 is conducted because a first row line 41 is at a high level. The currents and voltage of the M11 reach values obtaining practically sufficient writing speed because a bias line 46 is grounded by the T14 in the source of the M11. Since the reading signal R is at a high level on reading, the T18 is not conducted and a T19 is conducted, and both lines 46, 47 are brought to ground potential. Even when currents flow through the line 46 through the M11, the currents are suppressed because the T14 is conducted. Even when the potential of the line 47 rises, the potential can be returned rapidly to ground potential.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electrically writable programmable read-only memories.

Electrically writable programmable read-only memory cells include MNO8 structure memory cells that use traps at the interface between nitride and oxide films, and floating structure memory cells that inject charge into the floating gate. There is also a method using avalanche breakdown as a method for injecting charge to write data into a memory cell, a method using so-called channel injection in which a part of the charge flowing through the channel is injected into a trap or floating gate, and a method using thin insulation. By applying a strong electric field in the film, the Fowlcr-Nordhe
Although there are various methods such as injecting charge into a trap or a floating gate using an im current, the present invention is particularly applicable to a programmable read-only memory using a channel injection method memory cell with a floating gate structure. This is intended to improve the embedding characteristics.

First, the structure and characteristics of a channel injection type memory cell with a floating gate structure will be explained. FIG. 1 is a cross-sectional view of a channel injection type memory cell with a floating gate structure.

A floating gate 2 is formed on the upper surface of a source 5 and a drain 6 formed on a P-type silicon substrate 7 with a silicon oxide film 1 interposed therebetween.
A control gate 1 is formed on the upper surface of the cell via a silicon oxide film 4, and an electrode 3 is led out from an N-type source 5 and drain 6 to form an N-channel memory cell. When writing data νt, a high voltage is applied between the drain 6 and the source 50, and a positive voltage is applied to the control gate 1, thereby creating a channel on the surface of the P-type silicon substrate 7 below the floating gate 2. Electrons flow from the source 5 to the drain 6, and by injecting some of the electrons into the floating gate by the positive voltage applied to the control gate, the threshold voltage of the memory cell as seen from the control gate 1 is changed in the positive direction. It is something that moves. Therefore, the threshold voltage of a memory cell in which no data is written is low, and the threshold voltage of a memory cell in which data is written is high. Data ψ It is necessary to increase the voltage applied to the control gate 1. In particular, the voltage between the drain 6 and the source 5 is sensitive to the efficiency of injection into the loading gate 2. It is well known that by increasing the voltage between the source 6 and the source 5, the time required for data embedding is rapidly reduced.

When erasing data that has been omitted, in a floating memory cell like the one shown in Figure 1, ultraviolet rays are irradiated to increase the energy of the electrons in the floating gate and create an energy barrier between the floating gate and the silicon oxide film. A commonly used method is to release the electrons in the shifted floating gate by causing them to cross over. The threshold voltage of the memory cell after erasing by irradiation with ultraviolet rays drops to the threshold voltage before data writing.

FIG. 2 shows a conventional circuit of a 4-pit programmable read-only memory constructed using floating gate channel injection type memory cells. The drain is connected to the high voltage power supply for writing, and the gate is connected to the data signal terminal L)1 to the enhancement type for data input.
Oxide-8 semiconductor (for) transistors '■' 1 and 1' have drains connected to the sources of 1, gates connected to the first column selection signal terminal Y1, and sources connected to the first column line 23. The first column selection enforcement type MOS transistor T2 has its drain connected to the source of T1, its gate connected to the second column selection signal terminal Y2, and its source connected to the second column line 2.1. The second column selection enhancement type MOS transistor T3 and the drain thereof are connected to the first column line 23,
A control gate connects the row decoder 25 to the first row line 2.
] A first memory cell M of floating gate type channel injection type whose source is grounded
1, the drain is connected to the first column line 23, and the control gate connects the second row line 22 to the row decoder 25.
a second memory cell hfi2 whose source is grounded and whose drain is connected to the second column line 24;
A control gate connects the row decoder 25 to the first row line 2.
Turtle 3's memory cell M3 and Dore 1 were married through 1.
The programmable memory cell M4 of the conventional example shown in FIG. A read-only memory circuit is configured. In the conventional example shown in FIG. 2, for example, when writing data to Ml, D
The first column line 23 is reversely selected by setting I to DI, Y, to high level, and Y2 to ground potential,
The row decoder 25 sets the first row +121 to high level and the second row line 22 to the ground W7, so that the line is present at the intersection of the first column line 23 and the first row line 21. A high voltage is applied to both the drain and control gate of memory cell 841, allowing data to be loaded. In this case, ■, and I) T high level, Yl high level, first row IIi]21 high level is rF when writing data, and Isu is also 20V~
Setting the voltage to about 25V is temporary. When reading data, f/1tDI is set to the ground level, the voltages of Yl and the first row line 21 are set to the high level when reading, that is, the voltage of 5. The information stored in 1Ml can be read by injecting 1h current into the connection point from a path not shown. That is, when no data is written to Ml, the open voltage of Ml is lower than the voltage of the first row line 21 during reading, so l'vi1 is conductive, and as a result, the column line 23 of cylinder 1 is Because it will be low level'
The potential at the connection point of the drains of I' 2 and i' 3 also becomes low level, but if data is written into Ml, the voltage of the first row line 21 when the output is 1- than Ml
Since the threshold voltage of is high, it becomes non-conductive, and the potential at the connection point between the first column line 23 and the drains of T2 and T3 becomes high level.

However, in the conventional programmable read-only memory shown in FIG. #21. It will not operate as a programmable read-only memory unless the high-level voltage when the row line 22 of ff12 is blue is considerably higher than the voltage value determined from the evening characteristics of a single memory cell. There were drawbacks. The high voltage required for sliding in is a cause of inhibiting short channelization of VOS transistors, and short circuits are a barrier to increasing the capacity of programmable read-only memories. Channel MO
This is obvious from the fact that when a high voltage is applied to the drain of an S transistor, a large current due to a so-called pan-death through current may flow, leading to destruction. Using Fig. 3, we will explain the programmable read-only configuration of the conventional example shown in Fig. 2.
Explain why memory only works under high voltage. In FIG. 2, the first column #23 and the first row line #2
Assuming that 1 is selected and data is written to Ml,
The voltage/current characteristics of Ml can be expressed by curve 31 in Figure 3, and in order to write to Ml at a sufficiently fast speed, V
By applying a voltage higher than w to the drain of Ml, pM
It is assumed that it is necessary to flow a current of 1 W or more between the drain and the north of 1. By the way, when the load characteristics due to the resistance when conducting in series with T1 in FIG. 2 and 1゛2 are shown in FIG. 3, it can be displayed as a straight line 32, and the intersection with the characteristic curve of Ml is designated as B. If the voltage Vw and current Iw that allow writing at a practically sufficient speed are displayed on the Ml characteristic curve, and the point is A, then point B is on the right side of point A, that is, on the Ml characteristic curve, both the voltage and current are Vw. In this case, the data can be written at a sufficiently high speed since it is located in a larger portion than Iw and Iw. However, when memory cells are actually arranged in an array, the situation is different.

In other words, in the above case, only the memory cell M1 into which data is written was considered, but if memory cells are configured in an array, one memory cell into which data is written is one memory cell into which data is written. This is because the characteristics are adversely affected.

In Figure 2, 842 does not write data, so
The control gate is grounded by the second row line 22, but since the first column line 23 connected to the drain is at the no-y level, the floating gate and drain of M2 are automatically lapped. Since the potential of the floating gate increases due to the coupling due to the capacitance of M2, M2 becomes conductive when the voltage of the first column line 23 becomes higher than a certain value.

Since the curve 33 in FIG. 3 is the characteristic curve of M2,
As a result, the current flowing from the column wire 23 of cylinder 1 to the ground is the sum of the characteristic curve 31 of Ml and the characteristic curve 33 of M2, that is, curve 3
It becomes 4. For this purpose, the voltage at the intersection C between the load characteristic 32 and the characteristic curve 34 is determined by the memory cell formula 4 in which data is to be written.
The voltage and current values at this point are smaller than the voltage value VW and current value Iw at point A, which allows data to be written at a practical speed, so they are not practical in this case. In order to obtain a practical write speed, the load characteristic 32 must be moved to the right by increasing the write voltage. The voltage value is Vw
Therefore, when memory cells are configured in an array as a programmable read-only memory, a considerably higher write voltage is required than the write voltage for a single memory cell. This was hindering the increase in capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a programmable read-only memory that improves the above-mentioned drawbacks and is suitable for short channelization and increased memory capacity.

The programmable read-only memory of the present invention includes a plurality of row lines and a row decoder that selects the row lines;
A non-volatile device having a plurality of column lines, a column decoder for selecting the column lines, and a plurality of floating gates having a control gate connected to one of the row lines and a drain connected to one of the column lines. In a programmable read-only memory consisting of a memory cell array of memory cells, when data is written, the source of the selected memory cell is set to a low level, and the source potential of the other memory cells is set to a high level. The memory cell is characterized in that it is provided with bias application means for maintaining the source potential of all memory cells at the low level during data reading 7.

Next, the programmable read-only according to the present invention
The structure and operation of the memory will be explained in detail with reference to FIG. 4, which is a circuit diagram of an embodiment of the present invention, and FIG. 5, which is a characteristic diagram during its operation.

Figure 4 shows a 4-bit programmable read-only memory that is an embodiment of the present invention.
This is the same as the conventional example shown in the figure. The circuit of one embodiment of the present invention shown in FIG. 4 is a data input enforcement type M08) lunge, star Tl whose drain is connected to a high voltage power supply Vp for writing and whose gate is connected to a data signal terminal DI.
A first column selection encoder type MO8 whose drain is connected to the sources of 1 and 11, whose gate is connected to the first column selection signal terminal Y1, and whose source is connected to the first column line 43. ) transistors 1 and 12, and the drain is Tll.
The gate is connected to the source of the second column selection signal terminal Y
a second column selection enhancer IMO8) transistor T1 whose source is connected to the second column line 44;
3 and a drain connected to a first column line 43, a control gate connected to a row decoder 45 via a first row line 41, and a source connected to a first bias line 46. , the drain is connected to the first column line 43, and the control gate is connected to the row decoder 4.
5 via a second row line 42 and whose source is connected to a second bias line 47.
12, and a third memory whose drain is connected to the second column line 44, whose control gate is connected to the row decoder 45 via the first row line 41, and whose source is connected to the first bias line 46. Cell M13 and the drain is the second
a fourth memory cell M14 connected to the column line 44 of the memory cell M14, whose cost troll gate is connected to the row decoder 45 via the second row line 42, and whose source is connected to the second bias line 47; and an inverter I that receives as input a read signal R that becomes high level when reading data and becomes low level when writing data.
An enhancement type MO8 transistor T18 whose gate is connected to the output part of INV, whose gate is connected to the output part of INV, whose drain is connected to the source of 1 and 18, and whose gate is connected to the low voltage power supply VC for the read voltage. Enhancement type M with hole input and source grounded
O8) A transistor T19 whose drain is connected to the source of T18 and whose gate and source are connected to the first bias line 4
7) Deflation type MO8) transistor T connected to
16. ! , an enhancement type MOS transistor 'I' whose drain is connected to the first bias line 46, whose gate is connected to the first row line 41, and whose source is grounded.
14, the drain is connected to the source of 1118, and the gate and source are connected to the second bias line 47.8) The transistor 1117, the drain is connected to the second bias line 47, and the gate is connected to the second bias line 47.
The bias applying means 48 includes an enhancement type transistor T15 connected to the row line 42 and whose source is grounded.

In FIG. 4, for example, when writing Mll, the third
As in the case of the conventional example shown in the figure, writing is performed by applying the high level for writing to DI, Y2, and the first row line 41, but when writing, the read signal R is at low level. Therefore, the source voltage of T18 is at the high level of the VC voltage, and the first row line 41 is at the high level, so 'l'14 becomes conductive and the first bias line 46 becomes at the low level. ing. Also, the second line #
Since 42U is at low level, 1 and 15 are non-conductive, so the second bias line 47 is almost at Vclf.
t, the pressure is at a high level. The second bias line 47 is approximately Vc1! The fact that the voltage is at a high level means that even if the voltage of column #j43 becomes high and the voltage of the floating gate of M12 rises, the potential difference between the source and floating gate of M12 is
7, the voltage/current characteristics of M12 are shifted in the direction of higher voltage by about voltage 7c than in the conventional example shown in FIG. On the other hand, the source of the memory cell Mll into which data is to be written is almost at the ground voltage because the first bias line 46 is grounded by T14. This is the same as in the conventional example shown in the figure. As a result, as shown in FIG. 5, the Mll characteristic curve 51 is the same as the Mll characteristic curve 31 in FIG. 3, and the M12 characteristic curve 53 has a higher stain pressure than the M12 characteristic curve 33 in FIG. direction, move to the right in Figure 5, Mll and M1
2, i.e. the current flowing from the first column line 43 to ground, a characteristic curve 54 is obtained, but the characteristic curve 54
Compared to the characteristic curve 34 in FIG. 3, the point where the voltage suddenly rises is shifted to the right by approximately the Vc voltage. On the other hand, load characteristics due to resistance when Tll and Yt are conductive 52
is the same as the load characteristic 32 in FIG. 3, the characteristic curve 54
The intersection point of DA and the load characteristic 52 is C, and the current and voltage of the memory cell Mll to which writing is performed are displayed as dots, and compared to the conventional example shown in FIG. 3, DA is larger in both voltage and current. Since it is possible to set the value to a larger value than point A, where a practically sufficient writing speed can be obtained, the writing speed is lower than that of the conventional programmable read-only memory of the circuit shown in Figure 2. It is possible to set the voltage at a low voltage, which is advantageous for creating short channels and increasing capacity. When reading data, the read signal ratio is at the no-no level, so T18 is non-conductive and T19 is conductive.
First bias line 46, second bias line 47
Both are at ground potential, but current flows through the memory cell into the bias line to which the source of the selected memory cell is connected. For example, when Mll is selected, data is transferred to Mll as in the conventional example. The first result due to the current flowing through Mll when a current is applied from a path not shown in Fig. 4 when is not written.
Since the increase in the voltage of the bias line is suppressed by the conduction of i'14, the voltage of the bias line connected to the source of the selected memory cell remains at approximately the ground potential. Further, the potential of the bias line connected only to the sources of unselected memory cells, for example, the second bias line in FIG. 4, is that T13 is non-conductive, and M12. M13 is also non-conducting, while 1, 17 and 1, 19 are conducting, so they are always at ground potential, and the potential of the second bias line may rise due to external noise, leakage current, etc. Even if something happens, it can be quickly restored to the ground potential, so that the circuit stability during reading is equivalent to that of the conventional configuration shown in FIG. 2.

The above detailed explanation using one embodiment of the present invention,
The programmable read-only memory of the present invention can be written to at a lower voltage than conventional programmable read-only memories, so even if it is made into a seam channel, it will not be destroyed by punch-through current. We believe that it is suitable for large-capacity programmable read-only memory.

Although the embodiments have been explained using a 4-bit memory cell array, the effects of the present invention are not only effective when using a 4-bit memory cell array, but rather are effective when using a large capacity memory. It is clear that the effect of

Furthermore, for convenience of explanation, the explanation has been made using an N-channel MOS transistor, but it goes without saying that the effect will not be impaired even if the structure is constructed using a general insulated gate field effect transistor. Further, the bias applying means 48 in FIG. 5 is only an example, and any bias applying means configured according to the gist of the present invention may be used without using the circuit configuration shown in FIG. 4. It is clear that it is also included in the range.

[Brief explanation of the drawing]

Figure 1 is a structural diagram of a programmable read-only memory memory cell, Figure 2 is a diagram showing the configuration of a conventional programmable read-only memory, and Figure 3 is a diagram of a conventional programmable read-only memory. Programmable read only
An explanatory diagram of the characteristics when writing data to a memory, FIG. 4 is a diagram showing the configuration of an embodiment of the programmable read-only memory of the present invention, and FIG. 5 is a diagram of the programmable read-only memory of the present invention. FIG. 3 is a diagram showing characteristics when writing data. M1~M4・Old...Cell transistor. Agent Patent Attorney Uchihara Ubi 7 \+ Ba Kaya 1] Half 3 years

Claims (1)

[Claims] a plurality of row lines and a row decoder for selecting the row line, a plurality of column lines and a column decoder for selecting the column line, a control gate connected to one of the row lines, and a drain connected to one of the column lines. In a programmable read-only memory consisting of a memory cell array of non-volatile memory cells having multiple floating gates connected to each other, the source potential of the selected memory cell is set to a non-energized level when writing data. The programmable device is characterized in that it is equipped with a bias applying means for keeping the source potentials of other memory cells at an energizing level and keeping the source potentials of all memory cells at a non-energizing level when reading data. Read only memory.