JPH0834258B2 - Non-volatile semiconductor memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a non-volatile semiconductor memory, and more particularly to an electrically rewritable PROM, that is, an EEPROM, in which a floating gate composed of three polycrystalline silicon layers. , A memory element having a MOS transistor having an erase gate and a control gate.

[Prior Art] Conventionally, as this type of non-volatile memory, there is a so-called flash EERPOM as described in, for example, the July 29, 1985 issue of Nikkei Electronics.

9 is a plan view of a semiconductor chip showing a main part of a conventional example, FIG. 10 (a) is a plan view of a semiconductor chip showing a memory element of a conventional example, and FIGS. 10 (b) and 10 (c) are FIG. A sectional view taken along the line AA ′ and a sectional view taken along the line BB ′ of FIG.

Reference numeral 1 is a semiconductor substrate made of p-type silicon, 5 is an erase gate made of a first polycrystalline silicon layer, and 8 is a floating gate made of a second polycrystalline silicon layer. It faces the erase gate 5. Reference numeral 12 denotes a control gate formed of a third polycrystalline silicon layer, which faces the floating gate 8 with a floating gate inter-control gate oxide film 9 interposed therebetween. Reference numerals 3 and 13 are n-type source and drain diffusion layer regions, respectively. As shown in FIG. 9, the field effect transistor is used as a memory element to form a 2 × 2 matrix. The drain regions of the transistors Tr11 and Tr21 are connected to the bit line 22 through the contact holes to control Tr21 and Tr22. The gates are connected to each other in the direction perpendicular to the channel direction of the memory transistor to form a word line 27, and the source regions are connected to each other in parallel to the control gate to form a source line 25.
The erase gates of the transistors Tr11, Tr12, Tr21, Tr22 are connected in the vertical direction to the word line to form an erase line 29.

For example, when writing to Tr21, write the word line
About 18 V is applied to 27 and about 16 V is applied to the bit line 22, the erase line 29 and the source line 25 are grounded, and Tr21 is turned on to inject / accumulate hot electrons into the floating gate. In the erase operation, the word line 27, the source line 25, and the bit line 22 are grounded, and the erase line
Applying about 27V to 29, Fowler-Nordheim (Fowle
Electrons are emitted from the floating gate 8 to the erase line 29 by r-Nordheim) tunneling.

By the way, such a nonvolatile semiconductor memory has the following serious drawbacks because the erase line is arranged in parallel with the bit line. The erase gate 5 is placed on the thick field oxide film 2 due to its structure, but after the first polycrystalline silicon layer is formed on the field oxide film 2 in the manufacturing process and patterned, the floating gate inter-erasure gate oxide film 6 and the floating gate are formed. Before the oxide film 7 is formed, an oxide film etching process is required. At this time, an overhang can be formed under the erase gate 5 as shown in FIG. 11 (a). In this case, it is well known that the growth of the oxide film at the overhang portion is bad and is not preferable in terms of insulation characteristics. Since the subsequent second polycrystalline silicon layer is formed by vapor phase growth, it also grows in the overhang as shown in FIG. 11 (b), and if anisotropic etching is used for processing the floating gate 5. , As shown in FIG. 11 (c), it will remain in the overhang. Needless to say, this problem becomes more serious when the control gate floating gate oxide film 9 and the control gate oxide film 10 are formed and the control gate 12 made of the third polycrystalline silicon layer is formed. Since the erase gate is arranged on the field oxide film in this manner, not only the insulation characteristics between the erase gate and the floating gate and between the erase gate and the control gate become unstable, but also the floating gate degree due to the residue of polycrystalline silicon etching The short-circuiting between the wort lines and the short-circuiting between the wort lines are likely to occur, and the problem of the rubber that the deposited polycrystalline silicon peels off and adheres again is a serious problem in terms of yield and quality. This is a problem that occurs in connection with the manufacturing method, but there is also a problem that is based on the structure itself. That is, as the memory capacity increases, the erasing requirement is higher in byte units or page units (several bytes units) than in erasing all bits at once. However, in the conventional memory cell array configuration, in order to erase only the memory cells along a specific word line corresponding to a page unit, erasing cannot be prohibited unless the non-selected word line is set to a high potential according to the erase line. In this case, a high electric field is applied to the floating gate oxide film 7, and the source region 3 and the drain region 13 are
Alternatively, a problem of erroneous writing in which electrons are injected into the floating gate 8 from the inversion layer below the floating gate 8 becomes a problem.
Therefore, according to the prior art, reliable page partial erasure is difficult, and there is a major functional defect that it can only have an all-bit batch erase function.

[Problems to be solved by the invention]

In the conventional non-volatile semiconductor memory described above, the erase line provided on the field oxide film is arranged in parallel with the bit line (thus, orthogonal to the word line), so that the memory arranged along a specific word line. Since there is a high risk of malfunction when selecting and erasing cells, there is a drawback that page erasing is difficult and it has only an all-bit batch erasing function.

Further, since the erase gate is provided on the field oxide film, there is a drawback that a short circuit accident easily occurs in relation to the manufacturing method and the yield and reliability are poor.

[Means for solving problems]

A nonvolatile semiconductor memory according to the present invention includes a source region and a drain region, which are formed of a second conductivity type impurity-added layer selectively formed on a first conductivity type semiconductor substrate, the source region,
An erase gate made of a polycrystalline silicon film, which is provided between the drain regions on the semiconductor substrate via a first gate insulating film, and a polycrystalline silicon film facing the floating gate at least partly via a second gate insulating film. And a field effect transistor including a control gate provided on the floating gate via a third gate insulating film as a memory element in a non-volatile semiconductor memory, wherein the drain regions of the plurality of memory elements are provided. Bit lines which are connected to each other and run in a predetermined direction, word lines which connect control gates of the memory elements connected to different bit lines to each other and run in a direction perpendicular to the predetermined direction, and the respective word lines. A second conductive type impurity doped layer interconnecting the source regions of the memory elements connected to the line, and parallel to the word line A source line and an erase line formed of a polycrystalline silicon film which is provided on each of the source lines via an insulating film without protruding from the source line and interconnects the erase gates of the memory elements connected to the same word line; Is included.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 is a plan view of a semiconductor chip showing a main part of a first embodiment of the present invention, FIG. 2 (a) is a plan view showing a unit cell, and FIGS. 2 (b) and 2 (c) are respectively 2 A in Figure (a)
FIG. 6 is a cross-sectional view taken along the line A-A ′ and a line BB ′.

Reference numeral 1 is a semiconductor substrate made of p-type silicon, 2 is a field oxide film for insulation separation, 3 is an n-type source region, and 5 is an erase gate. The erase gate 5 is provided on the source region 3 via the erase gate-source oxide film 4 (insulating film) having a thickness of about 50 nm, and does not extend onto the field oxide film 2. 7 is a floating gate oxide film (first gate insulating film), 8 is a floating gate, 6 is an oxide film between floating gate erase gates (second gate insulating film) with a thickness of about 50 nm, and the floating gate 8 is Electrons in the floating gate are opposed to the erase gate 5 through the oxide film 6 between the floating gate and the erase gate of about 50 nm, and the electrons in the floating gate are drawn out to the erase gate by the Fowler-Nordheim tunneling at the facing portion. 10 is a control gate oxide film with a thickness of about 50 nm, 9 is a thickness of about 50 nm
Control gate floating inter-gate oxide film (third gate insulating film) having a thickness of 11 nm, control gate erase gate inter-oxide film having a thickness of about 50 nm, and control gate. Reference numeral 14 is an interlayer insulating film, 15 is a bit line made of aluminum wiring, and is connected to the drain region 13 via a contact 16.

FIG. 1 shows a 3 × 2 memory cell array. 22 and 23 are bit lines connected to the drain region of each memory cell, and 26, 27, and 28 are word lines connected to the control gate for each memory cell in the direction perpendicular to the bit line direction. Similarly, 25 is a source line in which a source region is connected to each memory cell that is in the direction perpendicular to the bit line direction, and 29 and 30 are erase gates for each memory cell that are also in the direction perpendicular to the bit line direction. It is a connected erase line. The erase lines 29, 30 are arranged in parallel with the word lines 26, 27, 28, and arranged vertically with the bit lines 22, 23.
Further, the erase lines 29, 30 are each narrower in width than the source region in the memory cell array, arranged on the source line, and do not extend over the field oxide film.

For example, to selectively write Tr21, about 18 V is applied to the word line 27 and about 16 V is applied to the bit line 22, and the bit line 23, the word line 26, the word line 28, and the source lines 24, 25 are grounded. Tr21
Only on, hot electrons are injected and accumulated in the floating gate. Erasing is performed by grounding the bit lines 22, 23, word lines 26, 27, 28 and source lines 24, 25, respectively, and applying about 27 V to the erase lines 29, 30 to cause electrons in the floating gate by Fowler-Nordheim tunneling to be applied. Is pulled out to the erase gate All transistors Tr11, Tr12, Tr21, Tr2
2, Tr31, Tr32 are erased at once. Further, since the erase line is arranged in parallel with the word line, only the memory transistor along the specific erase line can be erased. That is, it is possible to erase in page (several bytes) units. First
In the figure, for example, if a high potential of about 27V is applied only to the erase line 30 and the other erase line, that is, the erase line 29 is grounded, only Tr21, Tr22, Tr31, Tr32 along the erase line 30 are erased. . Since the control gate, erase gate, source region, and drain region are all at the ground potential in Tr11 and Tr12 in the erase-prohibited state, there is no risk of erroneous writing.

 Next, the manufacturing method of this embodiment will be described.

FIGS. 3 (a) and (b) to FIGS. 6 (a) and (b) show the first.
FIG. 2B is a cross-sectional view of a unit cell for explaining the manufacturing method of the embodiment of FIG.
It corresponds to FIG. 2 (c).

First, as shown in FIGS. 3A and 3B, a field oxide film 2 for insulation isolation having a thickness of about 1 μm is formed on a p-type semiconductor substrate 1 by a selective oxidation method, and a photoresist mask (not shown) is formed. Is provided and the source region 3 is formed by selectively ion-implanting n-type impurities.

Next, as shown in FIGS. 4A and 4B, an erase gate-source oxide film 4 is formed by a thermal oxidation method to form an n-type doped polycrystalline silicon film, and patterning is performed by a photolithography method. Then, the erase gate 5 is formed.

Next, as shown in FIGS. 5A and 5B, the oxide film 4 between the erase gate and the source other than under the erase gate 5 is removed by etching, and then the floating gate oxide film 7 and the oxide between the erase gate and the erase gate are oxidized by a thermal oxidation method. After forming the film 6, an n-type doped polycrystalline silicon film is grown and patterned to form the floating gate 8.

FIGS. 7 (a) and 7 (b) are sectional views of the portion corresponding to the line YY 'in FIG. 1 at this time. FIG. 7A shows a state in which the oxide film 4 between the erase gate and the source is etched in an overhang shape under the edge of the erase gate 5 after the oxide film other than under the erase gate is removed by etching. FIG. 7 (b) shows the state after the next thermal oxidation. The erase gate 5 is narrower than the width of the source region and is about 50 nm.
Since it is on the source region 3 through the erase gate-source oxide film 4 of the erase gate, the thermal oxide film of the source region semiconductor and the thermal oxide film of the erase gate polycrystalline silicon respectively grow during the thermal oxidation, and the area under the edge of the erase gate 5 is heated. It is filled with an oxide film and the overhang shape disappears. Therefore, the problem of the etching residue of the floating gate polycrystalline silicon at the overhang portion is solved. Further, there is no weak insulation between the floating gate and the erase gate, which is unique to the overhang portion. Next, as shown in FIG.
As shown in (b), after the exposed portion of the floating gate oxide film is removed by etching, a control gate oxide film 10 and a control gate floating gate inter-oxide film 9 are formed by a thermal oxidation method. 7th at this time
As described with reference to FIG. 5A, an overhang is formed just below the erase gate, but the overhang is eliminated by the thermal oxide films of the source region semiconductor and the erase gate polycrystalline silicon. Next, an n-type doped polycrystalline silicon film is formed and patterned to form a control gate 12
To form. At this time, there is no problem of etching residue of polycrystalline silicon in the overhang portion under the edge of the erase gate 5.
This is because there is no overhang. Next, after the drain region 13 is formed by the ion implantation method, for example, an interlayer film such as BPSG is grown and a contact is opened, an aluminum wiring is formed, and the state shown in FIG. 2 is obtained.

To restate, this manufacturing method forms an erase line on the source line formed of the source diffusion layer via a thin erase gate-source oxide film, removes this oxide film except under the erase gate, and then performs thermal oxidation. The floating gate oxide film and the floating gate erase gate inter-oxide film are formed to form the overhang part of the oxide film formed under the erase gate edge. It can be filled with a thermal oxide film. Therefore, the problem of polycrystalline silicon residue in the overhang portion, which has been a big drawback in the past, is solved, and further, the floating gate erase gate-gate insulating property and erase gate control gate-gate insulating property can be stabilized, and the nonvolatile semiconductor memory There is a feature that the problem of yield and quality is solved.

FIG. 8 is a plan view of a semiconductor chip showing a main part of the second embodiment of the present invention, showing a 2 × 2 memory cell matrix.

21 indicates a unit cell, 22 and 23 are bit lines, 2
6,27 are word lines, 29,30 are erase lines, 24
Is the source line.

In this embodiment, the erase line is divided into two on the source line, and the erase lines 29 and 39 are paired with the word lines 26 and 27, respectively, and only the memory cells along one specific word line can be erased. Therefore, there is an advantage that the one-page erasing function can be obtained.

[Effects of the Invention] As described above, according to the present invention, by disposing the erase line having a width smaller than that of the source line on the source line via the insulating film, the erase line can be arranged in parallel with the word line. The partial erasing of only the memory cells along the word line can be realized by a highly reliable method without any risk of erroneous writing, and the page erasing function can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor chip showing a main part of a first embodiment of the present invention, FIG. 2 (a) is a plan view of a unit cell part of the first embodiment, FIG. 2 (b), (C) is a cross-sectional view taken along the line AA ', BB' in FIG. 2 (a), and FIGS. 3 (a), (b) to 6 (a), (b) are shown in FIG. 2A and 2B are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the first embodiment, and FIGS. 2A and 2B correspond to FIGS. 2B and 2C, respectively. 7 (a), (b)
Similarly, FIG. 8 is a sectional view of the portion corresponding to the line YY ′ in FIG. 1 in the middle step, FIG. 8 is a plan view showing the main portion of the second embodiment of the present invention, and FIG. 9 is the main portion of the conventional example. FIG. 10A is a plan view of the semiconductor chip shown in FIG.
10 (b) and 10 (c) are sectional views taken along the line AA 'and BB' in FIG. 10 (a), and FIG. 11 is a semiconductor chip for explaining the conventional manufacturing method. Is a cross-sectional view showing the erase gate portion. 1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... Source region, 4 ... Erase gate Source oxide film (insulating film), 5 ... Erase gate, 6 ... Floating gate Erase gate insulating film ( Second gate insulating film), 7 ... Floating gate oxide film (first gate insulating film), 8 ... Floating gate, 9 ...
Floating gate Control gate oxide film (third gate insulating film), 10 ... Control gate oxide film, 11 ... Control gate erase gate oxide film, 12 ... Control gate, 13 ... Drain region, 14 ... … Interlayer insulation film, 15 …… bit line, 16 …… contact, 21 …… unit cell, 22,23 …… bit line, 24,25 ……
Source line, 26,27,28 ... Word line, 29,30 ... Erase line.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/788 29/792 G11C 11/40 101

Claims (1)

[Claims] 1. A first region on the semiconductor substrate between the source region and the drain region, and a source region and a drain region formed of a second conductivity type impurity-doped layer selectively formed on the first conductivity type semiconductor substrate. A floating gate provided through a gate insulating film of the second floating gate, the floating gate and at least a part of the floating gate;
Field-effect transistor including an erase gate made of a polycrystalline silicon film facing each other via a gate insulating film and a control gate provided on the floating gate via a third gate insulating film as a memory element in a matrix form. In the non-volatile semiconductor memory arranged as described above, the drain regions of the plurality of memory elements are mutually connected to run in a predetermined direction, and the control gates of the memory elements connected to different bit lines are mutually connected. A source line parallel to the word line, comprising a word line running in a direction perpendicular to the predetermined direction and a second conductivity type impurity doped layer interconnecting the source regions of the memory devices connected to the word lines. And a memory connected to the same word line provided on each source line via an insulating film without protruding from the source line. Nonvolatile semiconductor memory characterized by comprising an erasing line comprising a polycrystalline silicon film for connecting the erase gate of the elements to each other.