JPS6223396B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to semiconductor nonvolatile memory circuits.

Semiconductor memories are generally capable of high-speed writing and reading, but have the disadvantage that stored information is lost when the power is turned off. To overcome this drawback, various types of non-volatile memory have been developed that retain stored information even when the power is turned off. Normal RWM (read/write memory) has disadvantages such as restrictions.
At present, we cannot expect such behavior.

The present invention has been made in view of the above circumstances, and aims to provide a nonvolatile memory circuit that is capable of high-speed writing and reading and has no restriction on the number of rewrites. will be described in detail based on drawings showing examples thereof.

The drawing shows a part of a nonvolatile memory circuit according to the present invention which is integrated into an IC, that is, one bit of a cell constituting a memory array and a refresh circuit. In the figure, 11 is the write digit line, 12
is a read digit line, 13 is a read word line,
14 is a write word line, 15 is a refresh circuit, which connects write and read digit lines 11 and 12.
It is connected to.

Q ₁ , Q ₂ , and Q ₃ are all n-channel MIS type transistors, among which Q ₂ is a nonvolatile memory transistor having a floating gate structure. i.e. this transistor Q ₂
When the control gate 17 and the source 16 are both at the substrate potential V _S and a voltage higher than the predetermined critical voltage V _WC is applied to the drain 18, the threshold voltage Vth shifts in the negative direction, and the source When a voltage higher than a predetermined critical voltage V _EC is applied to the control gate 17 with the substrate potential V _S applied to the control gate 16 and the drain 18, the threshold voltage Vth shifts in the positive direction, and the control gate 17 is further applied with the critical voltage V _EC It has a property that the threshold voltage Vth does not change even if the source 16 is set to the substrate voltage V _S while a smaller predetermined voltage V _SUP is applied, and a voltage slightly higher than V _WC is applied to the drain 18.

Q ₁ is a write selection transistor that controls writing to transistor Q ₂ ;
The control gate 17 of Q ₂ is connected to the write digit line 11 and the write word line 14 . Further, Q ₃ is a read selection transistor that controls the readout of the transistor Q ₂ and connects the drain 18 of the transistor Q ₂ and the read digit line 12.
and the read word line 13.

Thus, this circuit operates in both dynamic memory operation and non-volatile memory operation modes. First, when the threshold voltage Vth of the transistor _Q2 is shifted in the positive direction as described above to make Vth>0 (enhancement type), a dynamic memory operation mode is established. In this mode, it operates exactly the same as a conventional dynamic read/write memory. In other words, the binary information of ON or OFF of the transistor Q ₂ corresponding to the charge accumulated in the stray capacitance of the control gate 17 of the transistor Q ₂ is read out via the read selection transistor Q ₃ and guided to the read digit line 12. Further, after the potential of the write digit line 11 is introduced to the control gate 17 of the transistor _Q2 via the write selection transistor _Q1 , writing or refreshing is performed by turning off the transistor _Q1 .
Note that since the voltages of various parts of the circuit used for this dynamic memory operation are lower than the above-mentioned V _WC and V _EC , the transistor Q ₅ operates in exactly the same way as a normal MIS transistor. However, the voltage of the charge accumulated in the stray capacitance of the control gate 17 is set to V volts (V _EC >V>V _SUP ) and the substrate potential V _S corresponding to binary data "1" and "0".

Next, transition to nonvolatile memory operation is performed as follows. That is, after writing or refreshing as described above, if a pulse of voltage exceeding the critical voltage _VWC (hereinafter referred to as a write pulse) is applied to the read digit line 12, and at the same time the read selection transistor _Q3 is turned on. V to the control gate 17 of transistor _Q2
When a charge of volts is stored, that is, when the stored information is "1", V< _VEC , and the voltage of the write pulse applied to the drain 18 via the transistor _Q3 is greater than _VWC . So,
For the reason mentioned above, no change occurs in the threshold voltage Vth of transistor _Q2 . Furthermore, when the control gate 17 of the transistor Q ₂ is at the substrate potential V _S , that is, when the stored information is "0", the voltage of the write pulse applied to the drain 18 is higher than V _WC , so the transistor
The threshold voltage Vth of Q ₂ will shift in the negative direction. In this way, in transistor _Q2 , the threshold voltage Vth does not change or does change in response to the charge accumulated in the control gate during dynamic operation, that is, the stored information during dynamic memory operation. become. The threshold voltage Vth of the transistor _Q2 of each cell determined in this manner is maintained even when the power is turned off. That is, binary information is stored nonvolatilely as two different values of threshold voltage Vth. And this difference in threshold voltage Vth is due to the difference in threshold voltage Vth between transistors.
Q ₁ is turned on, a voltage V _R between the above-mentioned binary threshold voltages Vth is applied to the write digit line 11, and the on/off state of the transistor Q ₂ is read out via the transistor Q _{3 and} the digit line 12, it can be read out.

The return from the above-described nonvolatile memory operation to the above-described dynamic memory operation is performed as follows. That is, the threshold voltage Vth of the transistor _Q2 , that is, the stored data is read out and latched in the refresh circuit 15, and the write digit line 1 is
A pulse of voltage exceeding the critical voltage V _EC (hereinafter referred to as an erase pulse) is applied to the transistor Q ₁ to turn on the transistor Q 1 , and the erase pulse is applied to the control gate 17 of the transistor Q ₂ via the transistor Q ₁ . This shifts the threshold voltage Vth of transistor _Q2 in the positive direction, and makes it equal to the positive value required for dynamic memory operation. Thereafter, the data latched in the refresh circuit 15 is used as write data to start the dynamic memory operation of the transistor _Q2 . By performing this operation for each word, the circuit returns to dynamic memory operation.

As described above, the circuit of the present invention uses a semiconductor non-volatile memory transistor as the MIS type transistor in a semiconductor dynamic memory circuit that utilizes the accumulation of charge in the stray capacitance of the gate of an MIS type transistor. Utilizing that writing of information to the semiconductor nonvolatile memory transistor is suppressed or not suppressed depending on the presence or absence of accumulated charge as a result,
Since it is characterized by making the results of dynamic memory operations nonvolatile, it overcomes the drawbacks of conventional dynamic memory, such as data volatility, and the drawbacks of conventional nonvolatile memory, such as long write times and Restrictions on the number of rewrites can be eliminated at once. This circuit also latches and writes to the refresh circuit.
This has the advantage that it can be easily realized by adding a few circuits such as an erase pulse generation circuit.

Furthermore, in the present invention, the storage contents of transistor _Q2 can be read out not only when operating as a dynamic memory but also when operating as a nonvolatile memory, and in that case, refreshing is not necessary.

Note that the circuit of the present invention can be similarly implemented in a P-channel type IC, and the non-volatile memory transistor may be of a type in which writing from the drain can be suppressed by the voltage of the control gate. Of course, it is not limited to the Teing gate type. Further, the format of the memory cell is not limited to that shown in the drawings, but may be any type of dynamic memory that can store charges in the stray capacitance of the gate of the MIS transistor.

As described above, according to the present invention, it is possible to realize a nonvolatile memory in which writing and reading can be performed at high speed and there is no restriction on the number of times of rewriting.

In addition, in the circuit of the present invention, since the information stored in the nonvolatile memory transistor is made nonvolatile by itself, the number of elements used is smaller than in a circuit in which the memory contents are saved to another element, and the circuit configuration is simpler. The present invention has excellent effects such as being able to be miniaturized and having high reliability.

[Brief explanation of the drawing]

The drawing is a circuit diagram schematically showing a part of a nonvolatile memory circuit according to the present invention. Q ₁ , Q ₂ , Q ₃ ...MIS type transistor, 11...
...Write digit line, 12...Read digit line, 13...Read word line, 14...Write word line, 15...Refresh circuit.

Claims (1)

[Claims] 1. An MIS type non-volatile memory transistor that performs a memory operation by accumulating charge in the stray capacitance of its gate, and an MIS-type non-volatile memory transistor connected to the gate of the non-volatile memory transistor to selectively apply charge to the gate. a write transistor;
A predetermined voltage is applied to the drain of the nonvolatile memory transistor, and the threshold voltage thereof is kept unchanged or changed depending on the presence or absence of accumulated charge as a result of the dynamic memory operation, thereby rendering the result of the dynamic memory operation nonvolatile. A non-volatile memory circuit that is characterized by its unique characteristics.