JPH0644395B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a static type memory (SRAM) in which memory cells are composed of insulated gate field effect transistors (MOSFETs). The word line drive circuit portion of a static memory having an internal power supply voltage down circuit is improved.

(Prior Art) In this type of semiconductor memory device, when the thickness of the gate oxide film becomes thinner as the miniaturization of the MOSFET progresses, the problem such as the breakdown voltage of the gate oxide film is reduced to the external level. The supply voltage of 5 V cannot be applied as it is between the gate and source of the MOSFET, and it is necessary to lower the IC external supply voltage by using the internal power supply voltage drop circuit to ensure the reliability of the MOSFET. The reason why the internal power supply voltage down circuit must be used is that the gate length is 0.6 μm or less. FIG. 6 shows an example of a circuit around a memory cell of a conventional SRAM assuming such a case. As a representative, one memory cell on one bit line is shown. M
C is a static memory cell, and N is cross-coupled.
Type MOSFET transistors Q ₃ and Q ₄ and a flip-flop composed of high resistance loads R ₁ and R ₂ connected to the internal power supply potential V _MM constitute a memory element, which is a word line WL.
Transfer gates Q ₁ and Q ₂ selectively controlled by
To the bit line pair BL, ▲ ▼. Therefore, complementary data is held in the internal nodes N ₁ and N ₂ of the flip-flop. This is called a high resistance load type static memory cell. The word line WL is driven through the word line drive circuit S ₁ and outputs “1” when selected. Bit line BL, ▲ ▼ are bit line loads Q ₅ , Q ₆
It has been pulled up with. Here, the output V _MM of the internal power supply voltage drop circuit is supplied to the word line drive circuit S ₁ , the bit line pull-up load, the high resistance load, and generally all the peripheral circuits. In this example, V _MM is driven by a source follower NMOS transistor Q _L whose internal power supply potential V _ref is used as a gate input and whose drain is connected to an external power supply voltage V _CC .

(Problems to be Solved by the Invention) FIG. 7 shows the characteristics of a general internal power supply down circuit. Internal reference voltage V _ref is consuming limiter exceeds a voltage V _ref0 there is an external voltage V _CC, a constant potential regardless of the external voltage V _CC. Accordingly, the voltage V _MM becomes a voltage of “V _REF −V _T ”, which is lowered by the threshold V _{T of the} transistor due to the characteristics of the source follower.

Therefore, in the static memory according to the conventional example, the output at the time of selecting the potential of the word line becomes V _T lower in the region lower than V _ref0 , as compared with the case where the internal power supply down circuit is not used. By the way, generally, the characteristics of the static memory cell according to FIG. 6 strongly depend on the word line voltage. That is, considering the case where the internal node N ₂ has a high potential and N ₁ has a low potential in the example of FIG. 6, the potential V _H of the internal node N ₂ at the time of writing is the word line potential V _WL , the transmission gate Q ₂ the V _H = V _WL -V _TT when the threshold to V _LL. This is because the resistance values of the high resistance loads R ₁ and R ₂ are very large. When this V _H is low, it becomes lower than the threshold value V _TD of the driver transistor Q ₃ on the low potential side, the transistor Q ₃ does not turn on, the potential on the low potential side disappears, and the safety as a flip-flop is achieved. Is not established and the cell MC cannot hold data.
Further, even if V _H > V _TD , if the difference is small, the driving force of the driver transistor Q ₃ becomes low, the cell current cannot be drawn, and the access time is delayed. Therefore, the conventional method has a drawback that the power supply voltage margin on the low potential side of the cell becomes small and the minimum operating power supply voltage V _CC min becomes worse than in the case where the internal power supply voltage down circuit is not used.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device in which the minimum operating voltage is not deteriorated even when an internal power supply down circuit is used.

[Configuration of the Invention] (Means and Actions for Solving the Problems) The present invention relates to a transmission gate in which a pair of input / output terminals holding flip-flops as storage elements for holding complementary data of the flip-flops are selectively controlled by word lines. A static type memory cell connected to a bit line pair through a word line drive circuit for driving the word line, and a power supply voltage drop circuit for stepping down an externally applied power supply potential and supplying it as an internal power supply potential of a circuit in a semiconductor chip. , A cell current monitor circuit of a dummy cell configuration for monitoring the bit line drive current of the static type memory cell in which an internal power supply potential is applied to the word line, and the internal power supply potential when the drive current of the dummy cell is a certain value or more. , When the value is equal to or less than the certain value, the power supply switching circuit that supplies the externally applied power supply potential to the word line drive circuit A semiconductor memory device characterized by being provided and.

That is, the present invention uses a dummy cell that monitors the cell pull-in current on the low potential side of the cell, detects that the cell pull-in current of this dummy cell is below a certain value, and determines the supply voltage of the word line drive circuit. By switching from the internal voltage drop V _MM to the external voltage V _CC , the word line potential is set to the external potential V _CC and the minimum operating voltage is not deteriorated.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
The figure is a circuit diagram of the same embodiment, but since this is an example of a case corresponding to that of FIG. 6, the same parts are designated by the same reference numerals and description thereof is omitted, and only the characteristic points are shown. Will be explained. That is, the supply voltage V _{WDRV of the} word line drive circuit S ₁
Is supplied by a source follower-connected NMOS transistor Q _L2 whose gate input is the internal reference potential V _ref, and a PMOS transistor Q _L3 connected in parallel with it. The gate of the transistor Q _L3, when the internal power supply potential V _MM is applied to the word line WL, and the inverted output V _MON cell current monitor circuit 1 for monitoring the cell current draw I _cell of the low potential side of the memory cell potential Has been entered. The potential V _MON is controlled so as to output "1" by detecting that the cell pull-in current I _cell is small enough for the read operation.

FIG. 2 shows an embodiment of the cell current monitor circuit according to the present invention. The transistors Q ₁ ′ and Q ₂ ′ have the same size as the cell transmission gate, and the transistor Q ₃ ′ has the same size as the cell driver transistors Q ₃ and Q ₄ . Q
Internal power supply potential V _MM is supplied to ₁ ′ and Q ₂ ′, and Q ₂ ′
Is grounded via a resistor R _N. The drain of Q ₁ ′ is connected to the internal power supply potential V _MM via the resistor R _M ,
The drain of Q ₂ 'is directly connected to V _MM . Resistance R
_{By making N} large enough, the voltage V _H ′ at the node N ₂ ′, which is the same as or slightly lower than the internal node V _H on the high potential side at the time of writing of the cell, appears, so that the transistor Q ₃ ′ is turned on. , The node N ₁ ′ imitates a low potential internal node. Thus, the transistors Q ₁ ′, Q ₂ ′, Q ₃ ′, and R _N form a dummy cell. Low anti- _RM is V _MM / _RM is cell draw current I _cell
Is an inadequate value for reading I _cell crit
Set it to be ical. By doing this,
When the current draw of V _MM is becoming lower cell becomes the voltage V _MMC become insufficient, the output V _MON monitor voltage V _MM
Is pulled up to. On the contrary, when V _MM is high and the cell pull-in current I _cell is sufficient, V _MON drops to the ground potential.

This is shown in FIG. By using the cell current monitor circuit having such characteristics, when the drive current of the dummy cell becomes insufficient, the output of the inverter S ₂ is output. Becomes "0", the PMOS transistor Q _L3 turns on and V
_WDRV is pulled up to the external potential V _CC . As a result, the word line potential rises from the internal step-down potential V _MM to the external potential V _CC , so that the stability of the cell MC is increased and the cell can be read. FIG. 4 shows the dependency of the word line supply potential V _{WDRV on} the external voltage V _CC according to the embodiment of FIGS. 2 and 3 of the present invention.
At point A, the output V _MON of the cell current monitor circuit 1 becomes "1", pulling up V _WDRV to the external voltage V _CC . As a result, the minimum operating voltage is improved by about the threshold voltage V _T 1V of Q _L2 as compared with the conventional method. Further, by monitoring the typical characteristics of the memory cell using the dummy cell in this way, it is possible to cancel the fluctuation of the memory cell characteristics due to the fluctuation of the process. Further, there is an effect that it is possible to cancel the change in the memory cell characteristic due to the change in the ambient temperature.

As another embodiment of the present invention, FIG. 5 shows a case where an emitter follower-connected NPN bipolar transistor Q _L ′ is used as an internal power source V _MM drive circuit instead of a source follower-connected NMOSFET. In this case, the operation is the first
Although it is the same as the example in the figure, V _ref −V _MM becomes the forward voltage V _f (0.8 V) of the bipolar transistor.

According to such a semiconductor memory device, by using the dummy cell 1 that monitors the cell pull-in current I _cell on the low potential side of the cell, it is detected that the cell pull-in current of this dummy cell is below a certain value. Word line drive circuit S ₁
By switching the supply voltage of the internal voltage drop V _MM from the external voltage V _CC to set the word line potential V _WL to V _CC , the threshold voltage V _T of the drive transistor of the internal potential drop circuit of the word line potential As a result, the minimum operating voltage is prevented from being deteriorated due to the drop due to the voltage drop, and the minimum operating voltage is improved by V _T, that is, about 1 V, as compared with the conventional static type memory using the internal power supply voltage dropping circuit.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device in which the minimum voltage for memory operation does not deteriorate even when an internal power supply down circuit is used.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a partial detailed view of the same circuit, FIG. 3 is its voltage characteristic diagram, and FIG. 4 is a power supply for a word line drive circuit of the same circuit. FIG. 5 is a characteristic diagram showing voltage dependence, FIG. 5 is a circuit diagram of another embodiment of the present invention, FIG. 6 is a circuit diagram of a conventional example, and FIG. 7 is a voltage characteristic diagram of an internal power supply down circuit of the circuit. . _{Q 1,} Q ₂ transmission gate of ...... memory _{cell, Q 3,} Q ₄ ...
... Memory cell driver transistors, R ₁ , R ₂ ...
High resistance load memory _{cell, Q} 5, Q 6 _...... bit line pull-up PMOSFET, Q L _...... internal supply voltage driving source follower NMOSFET, Q _L2 ...... word line power supply for driving the source follower NMOSFET, Q _L3 ... … Word line power supply drive PM
OSFET, S ₁ ... word line drive circuit, MC ... memory cell, WL ... word line, BL, ▲ ▼ ... bit line,
V _MM ... internal power supply potential, …… Cell current monitor output, V _ref …… Internal reference potential, V
_WDRV ...... word line drive circuit supply potential, ▲ ▼ ...... row decoder output, Q L _'...... internal supply voltage driving the emitter follower NPN bipolar transistor, Q _L2' ...... word line drive circuit supplies power for driving the emitter follower NPN bipolar Transistor, 1 ... Cell current monitor circuit (dummy cell).

Claims (5)

[Claims] 1. A static memory cell having a flip-flop as a storage element and a pair of input / output terminals for holding complementary data of the flip-flop connected to a bit line pair through a transmission gate selectively controlled by a word line, A word line drive circuit for driving a word line, a power supply voltage dropping circuit for stepping down an externally applied power supply potential and supplying it as an internal power supply potential of a circuit in a semiconductor chip, and the static memory in which the internal power supply potential is applied to the word line. A cell current monitor circuit of a dummy cell configuration that monitors the bit line drive current of the cell, and an internal power supply voltage when the dummy cell drive current is a certain value or more, and an externally applied power supply potential when the dummy cell drive current is a certain value or less. And a power supply switching circuit that supplies the word line drive circuit to the semiconductor memory device. 2. As the flip-flop, a first driver MOSFET whose source is grounded, a source is grounded, a gate is a drain of the first driver MOSFET, and a drain is a first
Second driver MO connected to the gate of the driver MOSFET of
SFET, a first load resistor connected between the drain of the first driver MOSFET and the internal power supply potential, and a second load resistor connected between the drain of the second driver MOSFET and the internal power supply potential 2. The semiconductor memory device according to claim 1, wherein a high resistance load type flip-flop consisting of is used. 3. A dummy driver MOSFET having the same dimensions as those of the first and second driver MOSFETs and having a source grounded, and a source having the same dimension as the transmission gate as the dummy cell. Above dummy driver
First dummy transmission gate MOSFET in which the gate is connected to the gate of the MOSFET and the drain is connected to the internal power potential
A second dummy transmission gate gate MOSFET having a source connected to the drain of the dummy driver MOSFET and a gate connected to an internal power supply potential; and the first dummy transmission gate MOSF.
It has a pull-down resistor connected between the source of ET and the ground potential, and a pull-up resistor connected between the drain of the second dummy transmission gate MOSFET and the internal power supply potential,
3. A circuit using the potential of the second dummy transmission gate MOSFET as an output monitor potential is used.
The semiconductor memory device according to 1. 4. A monitor circuit output is used as a gate input as a power supply switching circuit of the word line drive circuit,
A P-type MOSFET in which an external supply potential is connected to a source and a power supply potential of a word line drive circuit is connected to a drain, an internal power supply reference potential is connected to a gate, a drain is connected to an external supply potential, and a source is connected to a power supply potential of a word line drive circuit. The semiconductor memory device according to claim 1, wherein a circuit including a MOSFET is used. 5. A P-type MOSFET in which the monitor circuit output is used as a gate input and the external supply potential is connected to the source and the power supply potential of the word line drive circuit is connected to the drain, as a supply power switching circuit of the word line drive circuit, and a base. 2. The semiconductor memory device according to claim 1, wherein a circuit composed of an NPN bipolar transistor in which is connected to an internal power supply reference potential, a collector is connected to an external supply potential, and an emitter is connected to a power supply potential of a word line drive circuit is used.