JPH0325946B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of integrated circuits using semiconductors, particularly gallium arsenide (GaAs).

In realizing the static type memory cell shown in Figure 1 using gallium arsenide, the conventional structure was
The FET shown in Figure 2 was used. In FIG. 1, Q1 to Q4 are FETs, R1 and R2 are load resistors, and the four FETs and two load resistors constitute a 1-bit memory cell.
V _D is the power supply, W is the word line, D and are respectively
Represents DATA lines and lines.

In FIG. 2, 1 represents a GaAs semi-insulating substrate, 11 and 21, 12 and 22, 13 and 23 represent the drain electrode, gate electrode, and source electrode of the FET, respectively, and 14 and 24, 15 and 25 represent the FET drain electrode, gate electrode, and source electrode, respectively. A drain region and a source region are respectively formed in contact with the drain and source electrodes of the FET, and 16 and 26 are channel regions formed in contact with the gate electrode.

Next, the structure of the memory cell will be explained in detail using FIGS. 1 and 2. In the following, a case where a planar type n-channel MESFET is used will be described as an example.

As shown in FIG. 1, a static type memory cell has four FETs Q1 to Q4 and R1, R2.
It consists of two resistors. The gates of Q3 and Q4 are cross-connected to the drains of the other, and the sources are at ground potential. Resistor R1,
R2 is connected to the power supply potential V _D and the drains of Q3 and Q4 (hereinafter referred to as nodes N1 and N2). Q1 and Q2 are connected between the DATA line D and the node N1 and between the line and the node N2, respectively, and have gates connected to the word line W.
are commonly connected. The operation of this memory cell is as follows. Now, N1 is at a high potential, N
Suppose that the memory state is such that 2 is at ground potential. At this time, Q3 is non-conductive and Q4 is conductive. When the word line W is set to a high potential in this state, no current flows from the DATA line D to the memory cell because N1 is at a high potential and Q3 is off, but N2 is at ground potential. , and since Q4 is on, a current flows from line D to the memory cell. Conversely, in a storage state where N1 is at ground potential and N2 is at high potential, current flows from the DATA line D to the memory cell, but no current flows from the line to the memory cell. In this way, a sense amplifier (not shown) detects which of the DATA lines or lines current is flowing through, and the information stored in the memory cell is known. Writing is similarly performed by raising the potential of the word line W to a high potential while keeping the DATA line at a high potential, and by fixing one of the nodes N1 and N2 to a high potential.

The drain regions N1 and N2 of FETs Q3 and Q4, which are cross-connected to each other, are as shown in FIG.
Typically, n-type regions 14 and 24 are formed by ion implantation of silicon, sulfur, or the like onto a semi-insulating GaAs substrate. Drain electrodes 11 and 21 are formed on this n-type region, and are cross-connected to gate electrodes 12 and 22 of a mating FET by wiring (not shown).

In recent years, as semiconductor devices have become smaller and the area of memory cells has been reduced, the amount of accumulated charge that can be stored in memory cells as stored information has also become smaller. Most of the accumulated charges in the memory cell are stored in the N1 and N2 portions, which are type 2 regions. The conventional memory cell structure has the disadvantage that circuits malfunction due to electrons reaching the n-type region among electron-hole pairs generated by radiation incident on the GaAs substrate.

This malfunction is temporary, and if normal data is written in the next cycle, the device will operate normally again, so it is generally called a soft error.
Next, the cause of this soft error will be explained using FIG. 2.

Radiation that enters a GaAs substrate passes through the substrate several tens of micrometers until it stops, but before it stops, it generates many electron-hole pairs along its path. Among the generated electron-hole pairs, the electrons and holes generated within the substrate 1 are transferred to the substrate 1 by diffusion movement.
Some of the electrons move within the substrate and recombine, but some of the electrons are injected into the n-type region on the substrate surface. now,
Assume that N1 is at a high potential and N2 is at a low potential, and electrons generated by radiation are injected into the n-type region 14 of N1 by diffusion. in general
In MESFET, the capacitance of the n-type diffusion regions as the drain and source is only the junction capacitance with the substrate, and has an extremely small value.

Therefore, the amount of charge accumulated in each n-type region also becomes an extremely small value. Now, if the amount of accumulated charge when the n-type region is at a high potential is Q(H), and the amount of accumulated charge when the potential is low is Q(L), then generally Q(L)>Q(H). It works. If the difference in the amount of accumulated charge between these two states is Qcrit≡Q(L)-Q(H), then the n-type region 14,
If the charge Qα generated in 24 and the substrate 1 and injected into the n-type region by diffusion satisfies the relationship QαQ crit, the n-type region, which had been at a high potential, temporarily becomes a low potential. Or the potential drops to a lower level. When the potential of N1, which was at a high potential, falls and becomes lower than the potential of N2, an inversion of the latch occurs and the previously stored information is inverted. Furthermore, when the potential of N1 becomes low and becomes the same potential as N2, the latch becomes unstable and is easily reversed by even the slightest noise.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method, and the present invention was made by adding 10 ¹⁷ to 10 ¹⁹ conductive impurities different from that of the channel region to the lower part of the channel region of the FET formed on the substrate. Ions are implanted at a concentration of about cm ^-3 to form a junction capacitance with the channel region and add to the short key capacitance of the gate, increasing the capacitance of nodes cross-connected to the gate and causing soft errors. The purpose is to provide a structure that can prevent this.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, 1 represents a GaAs semi-insulating substrate, 11 and 21, 12 and 22, 13 and 23 represent the drain electrode, gate electrode, and source electrode of the FET, respectively, and 14, 24, 15
and 25 represent a drain region and a source region formed in contact with the drain electrode and source electrode of the FET, respectively, and 16 and 26 represent a channel region formed in contact with the gate electrode. Further, 17 and 27 represent regions having conductivity different from that of the channel region, which are formed under the channel region of the FET so as not to contact the drain region and the source region. Soft errors occur when charges generated by radiation entering the substrate are injected into the active region of the FET, temporarily changing the potential at that node.
When the active region is of n-type, malfunction is caused by the injection of electrons which temporarily lowers the potential of a node that has been kept at a high potential.

In this invention, a high concentration (10 ¹⁷ to 10 ¹⁹ cm ^-3 ) P-type region is formed below the channel region of the FET, and a junction capacitance is formed between the channel region and the gate capacitance. The present invention provides a structure in which the capacitance of the node connected to the gate is increased to reduce the potential drop caused by the injection of electrons generated by the incidence of radiation, thereby preventing the occurrence of soft errors. In the embodiment shown in FIG. 3, a P ⁺ region 27 is located below the n ⁺ region 26, which is a channel region.
By forming this, a junction capacitance is formed at the interface between these two regions, and is added to the Schottky capacitance that was formed between the gate electrode 22 and the channel region 26 of the MES structure. The gates and drains of FETs Q3 and Q4 constituting the flip-flop are cross-connected to each other, and by adding junction capacitance to the gate of Q4, the capacitance of node N1, which is the drain of Q3, also increases. Similarly, by adding a junction capacitance to the gate of Q3, the capacitance of node N2, which is the drain of Q4, also increases. As a result of the increase in the capacitance of nodes N1 and N2 of the flip-flop, the amount of accumulated charge in the memory cell increases, and even if electrons are injected into the node on the high potential side, the potential drop can be reduced, and the latch Reversal can be prevented.

That is, assume that the node _N1 is currently maintained at a high potential _VN1 , and the capacitance added to the node _N1 is C _N1 . Then, electrons generated by the radiation incident on the substrate are injected into node _N1 ,
If the voltage at node N ₁ drops by △V _N1 , then
Assuming that Q _N1 is the amount of accumulated charge at high potential V _N1 and △Q _N1 is the amount of charge increased due to electron injection, the relationship of V _N1 −△V _N1 = Q _N1 /C _N1 −△Q _N1 /C _N1 is Established.

Here, if the capacitance C _N1 has a sufficiently large value, the potential drop due to electron injection in the second term on the right side can be suppressed to a small value, and the potential will not approach the potential of the node _N2 or cause a potential reversal. That's not true.

Furthermore, the capacitance of the source and drain regions of the FET is
If C _SD is the accumulated charge, Q _CD is the amount of accumulated charge, I _SD is the operating current, T is the operating time, and V _SD is the applied voltage, then the relationship T=Q _SD /I _SD = C _SD・V _SD I _SD holds. . Therefore, channel areas 16, 2
The regions 17 and 27 having conductivity different from that of the source regions 15 and 25 and the drain region 14,
By forming these regions 15, 25, 14, and 24 so that they do not come into contact with each other to prevent their capacitance from increasing, the operating speed of FETs Q ₃ and Q ₄ constituting the flip-flop is prevented from decreasing. ing.

In addition, although the above-described embodiment shows an example in which the present invention is applied to a MESFET, the present invention does not depend on the structure of the electrode portion, and therefore can also be applied to a MOSFET. Furthermore, although the above embodiments have been described with respect to an n-channel device, the present invention can be similarly applied to a p-channel device by reversing the conductivity of each region and the sign of the voltage applied to each electrode.

As described above, according to the present invention, a region having a conductivity different from that of the channel region is formed below the channel region of the FET so as not to be in contact with the drain region and the source region. By adding a capacitor, the capacitance of the node is increased and the amount of stored charge is increased, and the potential drop caused by the injection of electrons can be reduced. Errors can be prevented, and furthermore, since the capacitance of the gate and drain regions does not increase, the operating speed of the transistors constituting the flip-flop does not decrease.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a static RAM memory cell, Figure 2 is a sectional view showing the structure of a conventional GaAs FET, and Figure 3 is an embodiment of the present invention.
1 is a cross-sectional view showing the structure of a GaAs FET. 1... GaAs semi-insulating substrate, 11, 12... Drain electrode, 12, 22... Gate electrode, 13,
23...source electrode, 14,24...drain region, 15,25...source region, 16,26...
Channel region, 17, 27...A region that has conductivity different from that of the channel region and is formed so as not to contact the drain region and the source region. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which a field effect transistor constituting a flip-flop is provided with a first conductivity type source/drain region near the main surface of a semi-insulating substrate and a channel region between the regions. , a region of a second conductivity type different from the first conductivity type is provided adjacent to the semi-insulating substrate side of the channel region and not in contact with the source/drain regions. Semiconductor integrated circuit.