JPS58148451A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the soft error generating from the incidented radioactive rays by a method wherein the impurities, having the conductivity different from that of the three regions below-mentioned, of 10<17>-10<19>cm<-3> or thereabout in density is ion-implanted at the lower part of the region on a substrate whereon an FET will be formed in such a manner that the drain, channel and source regions of the FET will be surrounded. CONSTITUTION:The numbers 14, 24 and 15, 28 in the diagram indicate the drain and source regions which were formed making contact with the drain and source electrodes of the FET respectively, and 16 and 26 indicate the channel regions which were formed making contact with the gate electrode. Also, 17 and 27 are the regions having different conductivity from that of the above-mentioned three regions which were formed surrounding the drain, channel and source regions of the FET. To be more precise, p type regions 17 and 27 of high density (10<17>- 10<19>cm<-3>) are formed in such a manner that they are surrounding the active region of the FET, the electron which was diffused from the substrate is recoupled in the p type region before it reaches the n type active region, thereby enabling to prevent the electron from being injected into the active region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of integrated circuits using semiconductors, particularly gallium arsenide (GaAs).

In order to realize the static type memory cell shown in Figure 1 using gallium arsenide, it is necessary to use t/X as a FET with a conventional structure.
There was one shown in 2111i. l! In Figure 1, Ql
-Q4 is FET%R1, R2 is load resistance, more than 4
A 1-bit memory cell is composed of two FETs and two load resistors. VD is the power supply, W is the word line, D and D
are each DATA! It represents the iJ and DATA lines.

In Figure 11!2, (1) represents the GaAs semiconductor substrate, (b) and (2), (2), (to), and (2) represent the drain electrode, gate electrode, and source IE electrode of the FET, respectively. , α◆, (c), (to), and (2) represent the drain region and source region formed in contact with the drain electrode and source electrode of the FET, respectively, and (to) and (g) represent the gate electrode. Represents a channel region formed in contact.

Next, the structure of the memory cell will be explained in detail using FIG. 1 and *g. In the following, a case where a Brehner type n-channel MESFET is used will be described as an example.

Static type memory cells are II! As shown in Figure 1, it consists of four FETs Ql-Q4 and two false resistors R1 and R2. The gates of Q8 and Q4 are cross-connected to the drains of the other, and the sources are at ground potential.・Resistors R1 and R2 are connected to power supply potential VD and Q8t
Drain of Q4 (hereinafter referred to as nodes Nl and N2)
and is connected to. Ql and Q2 are each DATA
Between wire and node Nl and DATA wire and node N
E-), and their gates are commonly connected to word line W. The operation of this memory cell is as follows. Assume that the storage state is now such that Nl is at a high potential %N16f ground potential. Konoto iQ
8 is in a non-conducting state, and Q4 is in a conducting state. When the word line W is set to a high potential in this state, N1 is at a high potential and Q
8 is off, no current flows from DATA *'a to the memory cell, but N2 is at ground potential and Q4 is on, so no current flows from the DATA line to the memory cell. Current flows towards. On the contrary, 'N
16 (ground potential, N line; In the case of a memory state where the potential is high, current flows from the DATA line to the memory cell, but no current flows from the DATA line to the memory cell.

In this way, a sense amplifier (not shown) detects which of the DATA lines and DATA lines the current is flowing through, and the information written in the memory cell is known. Writing is similarly performed by raising the potential of the word line W to a high potential while keeping either the DATA line or the DATA line at a high potential, and fixing either node Nl or N2 to a high potential.

The drain regions (N1, N2) of FETs (Q8 and Q412) which are cross-connected to each other are usually formed by instant implantation of silicon, sulfur, etc. onto a semi-insulating GaAs substrate, as shown in FIG. ) and form a ridge. Drain electrodes (b) and (2) are formed on this n-type region, and the gate electrode (6) of the mating FET is formed by wiring (not shown).
) and cross-connect with function.

In recent years, as semiconductor devices have become smaller and the area of memory cells has been reduced, the amount of accumulated charge that can be stored in memory cells as stored information has also become smaller. Most of the accumulated charge in the memory cell is stored in the N1 and M0 portions, which are n-type regions.

The conventional memory cell structure has a drawback in that circuits malfunction due to electrons reaching the n-type region among electron-hole pairs generated by radiation incident on the GaAs substrate.

This malfunction is temporary, and if normal data is written in the next cycle, it will operate normally again.
Generally called a soft error.

Next, let's look at the cause of this soft error! ! This will be explained using figures.

The radiation incident on the GaAl substrate passes through the substrate several tens of micrometers before stopping, but generates a large number of electron-hole pairs along its path before stopping. Among the generated electron-hole pairs, the electrons and holes generated within the substrate (1) move within the substrate (1) by diffusion movement, and some of them recombine, but some of them Electrons are injected into the n-type region of the substrate surface. Now, suppose that N1 is at a high potential, N2 is at a low potential, and electrons generated by radiation are injected into the Noon type region (b) by diffusion. Generally ME
In SFET, the capacitance of the n-type diffusion region as drain and source is only in the high junction state with the substrate,
It has an extremely small value.

Therefore, the charge accumulated in each n-type region also has an extremely small value. Now, let's look at the 811IiE charge when the n-type region is at a high potential. In general, if the amount of accumulated charge when the potential becomes low is Q(L), then Q(L)>Q@ generally holds, and the difference in the amount of accumulated charge between these two states is Q cr
If tmQ(L)-Q@-, then the n-type region (b), ■ and the substrate (charge Qad generated within υ and injected into the n-type region by diffusion) due to the incidence of radiation 5 Qa 〉Qcrit If this relationship is satisfied, the n-type region, which has been at a high potential, will temporarily drop to a low potential or a lower potential. When the potential of N1, which was high, is lowered, and the potential of N2 is also lower, the latch is inverted, and the previously stored information is inverted.

Furthermore, when the potential of Nl becomes low and becomes the same potential as Nz, the latch is in an unstable state and is easily reversed by even the slightest noise.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method, and a structure is provided below the region where the FET is formed on the substrate so as to surround each region of the drain, channel, and source of the FET. , an impurity with a conductivity different from that of these 8 regions is ion-implanted at a concentration of about 10!7 to 1 g19, and charges generated by radiation entering the substrate are injected into the above a region. It is an object of the present invention to provide a structure that can prevent soft errors by increasing the capacitance of the node by forming a junction capacitance with the drain region.

Hereinafter, one embodiment of the invention will be described with reference to the drawings. 8th
In the figure, (1) is G! represents a semiconductor substrate of lAs, and (2), (2) and (a), ni) and (
2) respectively represent the drain electrode, gate electrode, and source electrode of the FET, and 04, (foundation), (t), and so are the drain region and source region formed in contact with the drain electrode and source IIIE electrode of the FET, respectively. represents,
(2) and - represent the channel region formed in contact with the 11E electrode; This region has a different conductivity from the above eight regions. Soft errors are caused by the injection of charge into the active region of the FET, which is generated by radiation incident into the substrate. When the active region is n-type, malfunctions are caused by electron injection. This invention forms a P sub-region with a high heat concentration (1,17 to 10 "al-") to surround the active region of the FET, so that electrons diffused from the substrate are absorbed into the n-type active region. This provides a structure in which the ions are recombined within the P-type region and are not implanted into the active region.

Furthermore, in order to prevent malfunction of the memory cell latch, the latch node N1. If the additional capacitance of N2 is increased, even if electrons are injected into the node on the high potential side, the potential drop will be small, and it is possible to prevent the latch from inverting. In this invention, 101
By forming a P sub-region with a high concentration of about 7~l Q 1'cli' and adding a junk capacitance formed between it and the n-type active region to each node of the FET, the capacitance of the node can be reduced. This increases i, suppresses potential drop due to incidence of radiation, and prevents erroneous creation of FETs.

In the above embodiment, an example is shown in which the present invention is applied to a MESFET, but since the present invention does not depend on the structure of the WIt pole portion, it can also be applied to a MOSFET.

Further, as another embodiment of the present invention, a mesa-type λ (ESF
An example of application to ET is shown in the fourth factor.Although there are slight differences in the manufacturing method, it can be similarly applied to mesa type. Further, although the above embodiments have been described with respect to an n-channel device, if the conductivity of each region and the sign of the voltage applied to each electrode are all reversed, the same applies to a p-channel device.

As described above, according to the present invention, a region having a conductivity different from the eight regions described above is formed so as to surround the drain region, channel region, and source region of the FET, so that radiation is transmitted into the substrate. It is possible to prevent the charges generated by being incident on the substrate from being diffused in the substrate and injected into the above eight regions, and a new junk capacitance is added between the above eight regions, and the memory Since the storage capacity of the latch portion of the cell can be increased, soft errors caused by radiation incident on the private collector circuit can be prevented.

[Brief explanation of drawings]

Figure 1 is a memory circuit diagram of a static RAM, Figure 2 is a cross-sectional diagram showing the structure of a conventional GaAs FET,
I! Figure 8 shows a G1As FET according to an embodiment of the present invention.
FIG. 1114 is a cross-sectional view showing the structure of a GaAs FET according to another embodiment of the present invention. (1)...GaAs semiconductor substrate, (2), @...
・Drain electrode, @... Gate electrode, So, @
...Source electrode, (b). (Foundation)...Drain area, a! , (2)...source region, (to), so...channel region, (goods), @...
- Regions with conductivity different from those of the drain region, channel region, and source region Note that in the drawings, the same reference numerals indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 1 νJ Procedural Amendment (Voluntary λ) Commissioner of the Japan Patent Office 1, Indication of Case Patent Application No. 11007-1987 2,
Name of the invention: Semiconductor integrated circuit 3, Person making the amendment 6, Detailed description of the invention in the specification to be amended. 6. r DATA line or DATA on page 4, line 16 of the revised FF3 specification
Correct the phrase "line" to "rDATA line or DATA line". that's all

Claims (1)

Scope of Claims: (1) In a semiconductor integrated circuit formed on a semi-insulating substrate, an impurity having a first conductivity of 1011 to 1019 is added.
A first region is formed by implanting and diffusing to a concentration of about 1'3, and impurities of a second conductivity different from the first conductivity are added to the first region (1017 to 1017) so as to surround this first region. IQ”
A semiconductor integrated circuit characterized by having a second region formed by implantation and diffusion to a concentration of about ['. (2) The semiconductor integrated circuit according to claim 1, characterized in that an FET is formed on a semi-insulating substrate. (3) The first region is a cross-connected flip-flop circuit. The semiconductor #l product circuit according to claim 1, which is used as a node. (4) The semiconductor #1 product circuit according to claim 1, which is used as a node. The semiconductor integrated circuit according to claim 1. (5) The semiconductor integrated circuit according to claim 1 of the patent, characterized in that a semi-insulating gallium arsenide substrate is used as the semi-insulating substrate. (6) The second 2. The semiconductor integrated circuit according to claim 1, wherein the region is a groove formed to surround all or part of the periphery of the first region.