JPH0513444A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a high-performance FET having a small short-gate effect. CONSTITUTION:The resistance values of regions 20 and 20' on the sides near a channel 2 between source and drain regions are made larger than those of regions 19 and 19' on the sides far from the channel. Whereby an electric field strength between a high-resistance region and a semiconductor GaAs substrate is reduced and as a result, an injection of carriers from the source region into the substrate is reduced and a short-gate effect can be made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky gate field effect transistor (MESFET), and more particularly to providing a high performance FET suitable for ultra high speed computers and communication circuits.

[0002]

2. Description of the Related Art FIG. 1 is a sectional view of a conventional high performance FET. In this FET, the gate electrode 3 formed on the channel layer 2 formed on the surface of the semi-insulating GaAs substrate 1 and the n + source / drain regions 4 and 4'are self-aligned, and the parasitic resistance is reduced. As a result, high performance has been achieved. Reference numerals 5 and 6 are source / drain electrodes, respectively.

[0003]

However, in the FET of the conventional structure, as shown in FIG. 2, the gate length 7 is 1 μm.
When it is less than m, there is a phenomenon that the threshold voltage value shifts to the negative side as the gate length becomes shorter. This is ME
This is called the short gate effect of SFET, and the cause is n
+ Due to the proximity of the source / drain regions, the channel layer 2
It is considered that electrons are injected into the lower substrate side and a current flows between the source 5 and the drain 6 through the substrate. Further, when this phenomenon becomes remarkable, the gate voltage required for pinch-off increases, and the performance of the FET deteriorates.

It is an object of the present invention to provide a high performance FET with a short gate effect.

[0005]

The above object can be achieved by making the resistance value of the region of the source / drain region closer to the channel larger than the resistance value of the region far from the channel.

[0006]

By providing the high resistance region, the electric field strength between the high resistance region and the semi-insulating semiconductor substrate is reduced.
As a result, injection of carriers from the source region into the semi-insulating semiconductor substrate is reduced, and the short gate effect can be reduced.

[0007]

Embodiments of the present invention will be described below with reference to FIGS.
This will be described with reference to (e). Although this embodiment is an example in which the present invention is applied to a self-aligned MESFET formed on a semi-insulating GaAs substrate, the substrate is not limited to GaAs, and In
A compound semiconductor such as P, InGaAs, GaAlAs, InGaAsP or a semiconductor such as SiGe may be used.
3A to 3E show a manufacturing process of the element of this example and a sectional structure at the time of completion. In manufacturing the device of this example, first, as shown in FIG. 3A, ion implantation is performed using the pattern of the photoresist film 10 as a mask to form the channel 2 on the semi-insulating GaAs substrate 1. When Si + is used as the implanted ions, the implantation energy is 30 KeV, and the dose is the normally-off type 2.
5 × 10 ¹² cm ^-2 , normally on type 5.5 × 10 ¹² c
m ^-2 . Reference numeral 10 is a photoresist film for masking the area outside the FET. The ion-implanted layer 2 is thereafter activated by annealing. The annealing may be performed under the conditions (800 ° C., 15 minutes) that are usually performed. The atmosphere is As
A mixed gas of H ₃ gas and H ₂ gas is used.

Next, the photoresist patterns 18, 18 '
As a mask for the first source / drain regions 19, 19 '
Ion implantation is performed. Therefore, although the gates of these regions 19 and 19 'are not self-aligned with the electrodes, since they can be annealed without the gate electrodes, they can be annealed at a high temperature and low resistance regions can be formed. When ion implantation is Si + and implantation is 100 KeV and 2 × 10 ¹³ cm ^-2 , annealing is performed at 800 ° C. for 15 minutes to obtain 130Ω
A sheet resistance as low as / □ is obtained (Fig. 3 (b)).
However, since the alignment with the gate electrode is performed only by the mask aligner, it is necessary to set a gap with the gate electrode in view of the margin of alignment accuracy. It is necessary to separate them by 1 μm. When an electron beam exposure apparatus is used, it is easy to separate the gate length by 0.5 μm by about 0.5 μm. Adopting this method is optional.

Next, a refractory metal gate 11 is formed on the above channel layer by using a photolithography process (FIG. 3C). A WSi alloy film formed by CVD (pyrolysis chemical vapor deposition) is used for the refractory metal gate 11, and a gate electrode is formed by reactive dry etching using a photoresist pattern (not shown) as a mask. NF ₃ gas is used for WSi etching. In addition to the above materials, sputter WSi, CVD-
W, sputter W, MoSi, TiW or the like may be used.

Next, a photoresist mask 10 'for ion implantation is newly formed, and ion implantation for the second source / drain regions 20 and 20' is performed using this and the gate electrode as a mask. , 60 KeV, 8 ×
It is 10 ¹² cm ^-2 . The annealing conditions are 750 ° C. and 20 minutes as in the case of the first embodiment, whereby 400 to 50
Sheet resistance of 0Ω / □ and shallow source / drain regions can be obtained. Next, the p-type layers 16 and 16 '(see FIG.
(D)) is formed by implanting impurity ions 17. Be is used as the impurity ions, and the implantation condition is 60 Ke.
V, 2 × 10 ¹⁸ cm ^-2 . The center depth of the injection layer at this time is about 0.16 μm. Also, for this dose amount,
Since the p layer is depleted, the capacitance does not substantially increase as compared with the semi-insulating GaAs substrate. 7 after this ion implantation
Annealing is performed under the conditions of 00 ° C. and 20 minutes. This annealing is performed using a protective film such as AlN or in an AsH ₃ gas atmosphere. Also, a flash lamp or the like was used.
It may be activated by annealing at a high temperature (950 to 100 ° C.) and a short time (5 to 30 seconds). Further, Mg or C may be used as the impurity ions for forming the p-type layer, and the p-type layer can be formed by the same annealing.

Finally, the source / drain electrodes 5, 5 are formed on the source / drain regions by a conventional lift-off process.
The FET is completed by forming 6 (FIG. 3E).

According to the present embodiment, as shown in FIG. 3E, the source / drain regions are formed in two steps of the low resistance regions 19 and 19 'and the high resistance regions 20 and 20', and the short gate effect is obtained. The gate breakdown voltage is increased as well as being held down.

Also, the n + source / drain regions 19 and 1
Since the p-type layers 16 and 16 'can be formed so as to surround 9'and the injection of carriers from the source region to the substrate 1 can be prevented, it is possible to form an FET with a shorter gate effect.

Furthermore, since the p-type layer can be annealed after the activation annealing for the n-type channel and the n + -type source / drain regions, the low temperature annealing necessary for activation of only this layer is possible. Since the diffusion of the p-type layer during annealing is suppressed, the FET can be formed in a stable process with good controllability of the threshold voltage.

[0015]

As described above with reference to the embodiments, according to the present invention, in the FET in which the gate electrode and the source / drain regions are self-aligned using the refractory gate metal, the short gate is formed. It is possible to manufacture a high-performance FET with little effect.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a conventional self-aligned FET.

FIG. 2 is a diagram illustrating a short gate effect of a conventional self-aligned FET.

FIG. 3 is a cross-sectional view showing a manufacturing procedure of an FET according to an example of the present invention.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... Channel layer, 3 ... Gate electrode, 4
/ 4 ', 19/19', 20/20 '... Source / drain regions, 5, 6 ... Source / drain electrodes, 16/16'
... p-type buried layer.

Front page continuation (72) Inventor Yasunari Umemoto 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (1)

Claim: What is claimed is: 1. In a field effect transistor formed on a semi-insulating semiconductor substrate, a source / drain region has different resistance values in a region near a channel and a region far from the channel. The field effect transistor is characterized in that the resistance value in the region near the channel is larger than the resistance value in the region far from the channel.